[303] | 1 | /**
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| 2 | ******************************************************************************
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| 3 | * @file stm32f4xx_hal_pwr_ex.c
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| 4 | * @author MCD Application Team
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| 5 | * @version V1.4.1
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| 6 | * @date 09-October-2015
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| 7 | * @brief Extended PWR HAL module driver.
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| 8 | * This file provides firmware functions to manage the following
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| 9 | * functionalities of PWR extension peripheral:
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| 10 | * + Peripheral Extended features functions
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| 11 | *
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| 12 | ******************************************************************************
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| 13 | * @attention
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| 14 | *
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| 15 | * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
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| 16 | *
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| 17 | * Redistribution and use in source and binary forms, with or without modification,
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| 18 | * are permitted provided that the following conditions are met:
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| 19 | * 1. Redistributions of source code must retain the above copyright notice,
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| 20 | * this list of conditions and the following disclaimer.
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| 21 | * 2. Redistributions in binary form must reproduce the above copyright notice,
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| 22 | * this list of conditions and the following disclaimer in the documentation
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| 23 | * and/or other materials provided with the distribution.
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| 24 | * 3. Neither the name of STMicroelectronics nor the names of its contributors
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| 25 | * may be used to endorse or promote products derived from this software
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| 26 | * without specific prior written permission.
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| 27 | *
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| 28 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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| 29 | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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| 30 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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| 31 | * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
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| 32 | * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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| 33 | * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
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| 34 | * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
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| 35 | * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
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| 36 | * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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| 37 | * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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| 38 | *
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| 39 | ******************************************************************************
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| 40 | */
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| 41 |
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| 42 | /* Includes ------------------------------------------------------------------*/
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| 43 | #include "stm32f4xx_hal.h"
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| 44 |
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| 45 | /** @addtogroup STM32F4xx_HAL_Driver
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| 46 | * @{
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| 47 | */
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| 48 |
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| 49 | /** @defgroup PWREx PWREx
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| 50 | * @brief PWR HAL module driver
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| 51 | * @{
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| 52 | */
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| 53 |
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| 54 | #ifdef HAL_PWR_MODULE_ENABLED
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| 55 |
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| 56 | /* Private typedef -----------------------------------------------------------*/
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| 57 | /* Private define ------------------------------------------------------------*/
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| 58 | /** @addtogroup PWREx_Private_Constants
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| 59 | * @{
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| 60 | */
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| 61 | #define PWR_OVERDRIVE_TIMEOUT_VALUE 1000
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| 62 | #define PWR_UDERDRIVE_TIMEOUT_VALUE 1000
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| 63 | #define PWR_BKPREG_TIMEOUT_VALUE 1000
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| 64 | #define PWR_VOSRDY_TIMEOUT_VALUE 1000
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| 65 | /**
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| 66 | * @}
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| 67 | */
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| 68 |
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| 69 |
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| 70 | /* Private macro -------------------------------------------------------------*/
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| 71 | /* Private variables ---------------------------------------------------------*/
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| 72 | /* Private function prototypes -----------------------------------------------*/
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| 73 | /* Private functions ---------------------------------------------------------*/
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| 74 | /** @defgroup PWREx_Exported_Functions PWREx Exported Functions
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| 75 | * @{
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| 76 | */
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| 77 |
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| 78 | /** @defgroup PWREx_Exported_Functions_Group1 Peripheral Extended features functions
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| 79 | * @brief Peripheral Extended features functions
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| 80 | *
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| 81 | @verbatim
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| 82 |
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| 83 | ===============================================================================
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| 84 | ##### Peripheral extended features functions #####
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| 85 | ===============================================================================
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| 86 |
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| 87 | *** Main and Backup Regulators configuration ***
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| 88 | ================================================
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| 89 | [..]
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| 90 | (+) The backup domain includes 4 Kbytes of backup SRAM accessible only from
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| 91 | the CPU, and address in 32-bit, 16-bit or 8-bit mode. Its content is
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| 92 | retained even in Standby or VBAT mode when the low power backup regulator
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| 93 | is enabled. It can be considered as an internal EEPROM when VBAT is
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| 94 | always present. You can use the HAL_PWREx_EnableBkUpReg() function to
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| 95 | enable the low power backup regulator.
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| 96 |
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| 97 | (+) When the backup domain is supplied by VDD (analog switch connected to VDD)
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| 98 | the backup SRAM is powered from VDD which replaces the VBAT power supply to
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| 99 | save battery life.
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| 100 |
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| 101 | (+) The backup SRAM is not mass erased by a tamper event. It is read
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| 102 | protected to prevent confidential data, such as cryptographic private
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| 103 | key, from being accessed. The backup SRAM can be erased only through
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| 104 | the Flash interface when a protection level change from level 1 to
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| 105 | level 0 is requested.
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| 106 | -@- Refer to the description of Read protection (RDP) in the Flash
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| 107 | programming manual.
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| 108 |
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| 109 | (+) The main internal regulator can be configured to have a tradeoff between
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| 110 | performance and power consumption when the device does not operate at
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| 111 | the maximum frequency. This is done through __HAL_PWR_MAINREGULATORMODE_CONFIG()
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| 112 | macro which configure VOS bit in PWR_CR register
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| 113 |
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| 114 | Refer to the product datasheets for more details.
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| 115 |
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| 116 | *** FLASH Power Down configuration ****
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| 117 | =======================================
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| 118 | [..]
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| 119 | (+) By setting the FPDS bit in the PWR_CR register by using the
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| 120 | HAL_PWREx_EnableFlashPowerDown() function, the Flash memory also enters power
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| 121 | down mode when the device enters Stop mode. When the Flash memory
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| 122 | is in power down mode, an additional startup delay is incurred when
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| 123 | waking up from Stop mode.
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| 124 |
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| 125 | (+) For STM32F42xxx/43xxx/446xx/469xx/479xx Devices, the scale can be modified only when the PLL
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| 126 | is OFF and the HSI or HSE clock source is selected as system clock.
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| 127 | The new value programmed is active only when the PLL is ON.
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| 128 | When the PLL is OFF, the voltage scale 3 is automatically selected.
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| 129 | Refer to the datasheets for more details.
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| 130 |
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| 131 | *** Over-Drive and Under-Drive configuration ****
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| 132 | =================================================
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| 133 | [..]
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| 134 | (+) For STM32F42xxx/43xxx/446xx/469xx/479xx Devices, in Run mode: the main regulator has
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| 135 | 2 operating modes available:
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| 136 | (++) Normal mode: The CPU and core logic operate at maximum frequency at a given
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| 137 | voltage scaling (scale 1, scale 2 or scale 3)
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| 138 | (++) Over-drive mode: This mode allows the CPU and the core logic to operate at a
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| 139 | higher frequency than the normal mode for a given voltage scaling (scale 1,
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| 140 | scale 2 or scale 3). This mode is enabled through HAL_PWREx_EnableOverDrive() function and
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| 141 | disabled by HAL_PWREx_DisableOverDrive() function, to enter or exit from Over-drive mode please follow
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| 142 | the sequence described in Reference manual.
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| 143 |
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| 144 | (+) For STM32F42xxx/43xxx/446xx/469xx/479xx Devices, in Stop mode: the main regulator or low power regulator
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| 145 | supplies a low power voltage to the 1.2V domain, thus preserving the content of registers
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| 146 | and internal SRAM. 2 operating modes are available:
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| 147 | (++) Normal mode: the 1.2V domain is preserved in nominal leakage mode. This mode is only
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| 148 | available when the main regulator or the low power regulator is used in Scale 3 or
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| 149 | low voltage mode.
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| 150 | (++) Under-drive mode: the 1.2V domain is preserved in reduced leakage mode. This mode is only
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| 151 | available when the main regulator or the low power regulator is in low voltage mode.
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| 152 |
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| 153 | @endverbatim
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| 154 | * @{
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| 155 | */
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| 156 |
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| 157 | /**
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| 158 | * @brief Enables the Backup Regulator.
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| 159 | * @retval HAL status
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| 160 | */
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| 161 | HAL_StatusTypeDef HAL_PWREx_EnableBkUpReg(void)
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| 162 | {
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| 163 | uint32_t tickstart = 0;
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| 164 |
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| 165 | *(__IO uint32_t *) CSR_BRE_BB = (uint32_t)ENABLE;
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| 166 |
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| 167 | /* Get tick */
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| 168 | tickstart = HAL_GetTick();
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| 169 |
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| 170 | /* Wait till Backup regulator ready flag is set */
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| 171 | while(__HAL_PWR_GET_FLAG(PWR_FLAG_BRR) == RESET)
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| 172 | {
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| 173 | if((HAL_GetTick() - tickstart ) > PWR_BKPREG_TIMEOUT_VALUE)
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| 174 | {
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| 175 | return HAL_TIMEOUT;
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| 176 | }
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| 177 | }
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| 178 | return HAL_OK;
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| 179 | }
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| 180 |
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| 181 | /**
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| 182 | * @brief Disables the Backup Regulator.
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| 183 | * @retval HAL status
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| 184 | */
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| 185 | HAL_StatusTypeDef HAL_PWREx_DisableBkUpReg(void)
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| 186 | {
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| 187 | uint32_t tickstart = 0;
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| 188 |
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| 189 | *(__IO uint32_t *) CSR_BRE_BB = (uint32_t)DISABLE;
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| 190 |
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| 191 | /* Get tick */
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| 192 | tickstart = HAL_GetTick();
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| 193 |
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| 194 | /* Wait till Backup regulator ready flag is set */
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| 195 | while(__HAL_PWR_GET_FLAG(PWR_FLAG_BRR) != RESET)
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| 196 | {
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| 197 | if((HAL_GetTick() - tickstart ) > PWR_BKPREG_TIMEOUT_VALUE)
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| 198 | {
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| 199 | return HAL_TIMEOUT;
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| 200 | }
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| 201 | }
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| 202 | return HAL_OK;
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| 203 | }
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| 204 |
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| 205 | /**
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| 206 | * @brief Enables the Flash Power Down in Stop mode.
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| 207 | * @retval None
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| 208 | */
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| 209 | void HAL_PWREx_EnableFlashPowerDown(void)
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| 210 | {
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| 211 | *(__IO uint32_t *) CR_FPDS_BB = (uint32_t)ENABLE;
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| 212 | }
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| 213 |
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| 214 | /**
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| 215 | * @brief Disables the Flash Power Down in Stop mode.
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| 216 | * @retval None
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| 217 | */
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| 218 | void HAL_PWREx_DisableFlashPowerDown(void)
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| 219 | {
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| 220 | *(__IO uint32_t *) CR_FPDS_BB = (uint32_t)DISABLE;
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| 221 | }
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| 222 |
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| 223 | /**
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| 224 | * @brief Return Voltage Scaling Range.
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| 225 | * @retval The configured scale for the regulator voltage(VOS bit field).
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| 226 | * The returned value can be one of the following:
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| 227 | * - @arg PWR_REGULATOR_VOLTAGE_SCALE1: Regulator voltage output Scale 1 mode
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| 228 | * - @arg PWR_REGULATOR_VOLTAGE_SCALE2: Regulator voltage output Scale 2 mode
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| 229 | * - @arg PWR_REGULATOR_VOLTAGE_SCALE3: Regulator voltage output Scale 3 mode
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| 230 | */
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| 231 | uint32_t HAL_PWREx_GetVoltageRange(void)
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| 232 | {
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| 233 | return (PWR->CR & PWR_CR_VOS);
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| 234 | }
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| 235 |
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| 236 | #if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx)
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| 237 | /**
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| 238 | * @brief Configures the main internal regulator output voltage.
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| 239 | * @param VoltageScaling: specifies the regulator output voltage to achieve
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| 240 | * a tradeoff between performance and power consumption.
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| 241 | * This parameter can be one of the following values:
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| 242 | * @arg PWR_REGULATOR_VOLTAGE_SCALE1: Regulator voltage output range 1 mode,
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| 243 | * the maximum value of fHCLK = 168 MHz.
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| 244 | * @arg PWR_REGULATOR_VOLTAGE_SCALE2: Regulator voltage output range 2 mode,
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| 245 | * the maximum value of fHCLK = 144 MHz.
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| 246 | * @note When moving from Range 1 to Range 2, the system frequency must be decreased to
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| 247 | * a value below 144 MHz before calling HAL_PWREx_ConfigVoltageScaling() API.
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| 248 | * When moving from Range 2 to Range 1, the system frequency can be increased to
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| 249 | * a value up to 168 MHz after calling HAL_PWREx_ConfigVoltageScaling() API.
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| 250 | * @retval HAL Status
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| 251 | */
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| 252 | HAL_StatusTypeDef HAL_PWREx_ControlVoltageScaling(uint32_t VoltageScaling)
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| 253 | {
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| 254 | uint32_t tickstart = 0;
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| 255 |
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| 256 | assert_param(IS_PWR_VOLTAGE_SCALING_RANGE(VoltageScaling));
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| 257 |
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| 258 | /* Enable PWR RCC Clock Peripheral */
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| 259 | __HAL_RCC_PWR_CLK_ENABLE();
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| 260 |
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| 261 | /* Set Range */
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| 262 | __HAL_PWR_VOLTAGESCALING_CONFIG(VoltageScaling);
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| 263 |
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| 264 | /* Get Start Tick*/
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| 265 | tickstart = HAL_GetTick();
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| 266 | while((__HAL_PWR_GET_FLAG(PWR_FLAG_VOSRDY) == RESET))
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| 267 | {
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| 268 | if((HAL_GetTick() - tickstart ) > PWR_VOSRDY_TIMEOUT_VALUE)
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| 269 | {
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| 270 | return HAL_TIMEOUT;
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| 271 | }
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| 272 | }
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| 273 |
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| 274 | return HAL_OK;
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| 275 | }
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| 276 |
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| 277 | #elif defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || \
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| 278 | defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F410Tx) || defined(STM32F410Cx) || \
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| 279 | defined(STM32F410Rx) || defined(STM32F411xE) || defined(STM32F446xx) || defined(STM32F469xx) || \
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| 280 | defined(STM32F479xx)
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| 281 | /**
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| 282 | * @brief Configures the main internal regulator output voltage.
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| 283 | * @param VoltageScaling: specifies the regulator output voltage to achieve
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| 284 | * a tradeoff between performance and power consumption.
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| 285 | * This parameter can be one of the following values:
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| 286 | * @arg PWR_REGULATOR_VOLTAGE_SCALE1: Regulator voltage output range 1 mode,
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| 287 | * the maximum value of fHCLK is 168 MHz. It can be extended to
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| 288 | * 180 MHz by activating the over-drive mode.
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| 289 | * @arg PWR_REGULATOR_VOLTAGE_SCALE2: Regulator voltage output range 2 mode,
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| 290 | * the maximum value of fHCLK is 144 MHz. It can be extended to,
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| 291 | * 168 MHz by activating the over-drive mode.
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| 292 | * @arg PWR_REGULATOR_VOLTAGE_SCALE3: Regulator voltage output range 3 mode,
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| 293 | * the maximum value of fHCLK is 120 MHz.
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| 294 | * @note To update the system clock frequency(SYSCLK):
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| 295 | * - Set the HSI or HSE as system clock frequency using the HAL_RCC_ClockConfig().
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| 296 | * - Call the HAL_RCC_OscConfig() to configure the PLL.
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| 297 | * - Call HAL_PWREx_ConfigVoltageScaling() API to adjust the voltage scale.
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| 298 | * - Set the new system clock frequency using the HAL_RCC_ClockConfig().
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| 299 | * @note The scale can be modified only when the HSI or HSE clock source is selected
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| 300 | * as system clock source, otherwise the API returns HAL_ERROR.
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| 301 | * @note When the PLL is OFF, the voltage scale 3 is automatically selected and the VOS bits
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| 302 | * value in the PWR_CR1 register are not taken in account.
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| 303 | * @note This API forces the PLL state ON to allow the possibility to configure the voltage scale 1 or 2.
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| 304 | * @note The new voltage scale is active only when the PLL is ON.
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| 305 | * @retval HAL Status
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| 306 | */
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| 307 | HAL_StatusTypeDef HAL_PWREx_ControlVoltageScaling(uint32_t VoltageScaling)
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| 308 | {
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| 309 | uint32_t tickstart = 0;
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| 310 |
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| 311 | assert_param(IS_PWR_VOLTAGE_SCALING_RANGE(VoltageScaling));
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| 312 |
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| 313 | /* Enable PWR RCC Clock Peripheral */
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| 314 | __HAL_RCC_PWR_CLK_ENABLE();
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| 315 |
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| 316 | /* Check if the PLL is used as system clock or not */
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| 317 | if(__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_CFGR_SWS_PLL)
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| 318 | {
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| 319 | /* Disable the main PLL */
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| 320 | __HAL_RCC_PLL_DISABLE();
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| 321 |
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| 322 | /* Get Start Tick */
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| 323 | tickstart = HAL_GetTick();
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| 324 | /* Wait till PLL is disabled */
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| 325 | while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET)
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| 326 | {
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| 327 | if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE)
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| 328 | {
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| 329 | return HAL_TIMEOUT;
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| 330 | }
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| 331 | }
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| 332 |
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| 333 | /* Set Range */
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| 334 | __HAL_PWR_VOLTAGESCALING_CONFIG(VoltageScaling);
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| 335 |
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| 336 | /* Enable the main PLL */
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| 337 | __HAL_RCC_PLL_ENABLE();
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| 338 |
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| 339 | /* Get Start Tick */
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| 340 | tickstart = HAL_GetTick();
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| 341 | /* Wait till PLL is ready */
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| 342 | while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET)
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| 343 | {
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| 344 | if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE)
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| 345 | {
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| 346 | return HAL_TIMEOUT;
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| 347 | }
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| 348 | }
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| 349 |
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| 350 | /* Get Start Tick */
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| 351 | tickstart = HAL_GetTick();
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| 352 | while((__HAL_PWR_GET_FLAG(PWR_FLAG_VOSRDY) == RESET))
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| 353 | {
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| 354 | if((HAL_GetTick() - tickstart ) > PWR_VOSRDY_TIMEOUT_VALUE)
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| 355 | {
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| 356 | return HAL_TIMEOUT;
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| 357 | }
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| 358 | }
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| 359 | }
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| 360 | else
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| 361 | {
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| 362 | return HAL_ERROR;
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| 363 | }
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| 364 |
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| 365 | return HAL_OK;
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| 366 | }
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| 367 | #endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx */
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| 368 |
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| 369 | #if defined(STM32F469xx) || defined(STM32F479xx)
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| 370 | /**
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| 371 | * @brief Enables Wakeup Pin Detection on high level (rising edge).
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| 372 | * @retval None
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| 373 | */
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| 374 | void HAL_PWREx_EnableWakeUpPinPolarityRisingEdge(void)
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| 375 | {
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| 376 | *(__IO uint32_t *) CSR_WUPP_BB = (uint32_t)DISABLE;
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| 377 | }
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| 378 |
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| 379 | /**
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| 380 | * @brief Enables Wakeup Pin Detection on low level (falling edge).
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| 381 | * @retval None
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| 382 | */
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| 383 | void HAL_PWREx_EnableWakeUpPinPolarityFallingEdge(void)
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| 384 | {
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| 385 | *(__IO uint32_t *) CSR_WUPP_BB = (uint32_t)ENABLE;
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| 386 | }
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| 387 | #endif /* STM32F469xx || STM32F479xx */
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| 388 |
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| 389 | #if defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx) ||\
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| 390 | defined(STM32F411xE)
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| 391 | /**
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| 392 | * @brief Enables Main Regulator low voltage mode.
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| 393 | * @note This mode is only available for STM32F401xx/STM32F410xx/STM32F411xx devices.
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| 394 | * @retval None
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| 395 | */
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| 396 | void HAL_PWREx_EnableMainRegulatorLowVoltage(void)
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| 397 | {
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| 398 | *(__IO uint32_t *) CR_MRLVDS_BB = (uint32_t)ENABLE;
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| 399 | }
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| 400 |
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| 401 | /**
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| 402 | * @brief Disables Main Regulator low voltage mode.
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| 403 | * @note This mode is only available for STM32F401xx/STM32F410xx/STM32F411xx devices.
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| 404 | * @retval None
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| 405 | */
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| 406 | void HAL_PWREx_DisableMainRegulatorLowVoltage(void)
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| 407 | {
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| 408 | *(__IO uint32_t *) CR_MRLVDS_BB = (uint32_t)DISABLE;
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| 409 | }
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| 410 |
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| 411 | /**
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| 412 | * @brief Enables Low Power Regulator low voltage mode.
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| 413 | * @note This mode is only available for STM32F401xx/STM32F410xx/STM32F411xx devices.
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| 414 | * @retval None
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| 415 | */
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| 416 | void HAL_PWREx_EnableLowRegulatorLowVoltage(void)
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| 417 | {
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| 418 | *(__IO uint32_t *) CR_LPLVDS_BB = (uint32_t)ENABLE;
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| 419 | }
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| 420 |
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| 421 | /**
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| 422 | * @brief Disables Low Power Regulator low voltage mode.
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| 423 | * @note This mode is only available for STM32F401xx/STM32F410xx/STM32F411xx devices.
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| 424 | * @retval None
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| 425 | */
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| 426 | void HAL_PWREx_DisableLowRegulatorLowVoltage(void)
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| 427 | {
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| 428 | *(__IO uint32_t *) CR_LPLVDS_BB = (uint32_t)DISABLE;
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| 429 | }
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| 430 |
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| 431 | #endif /* STM32F401xC || STM32F401xE || STM32F410xx || STM32F411xE */
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| 432 |
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| 433 | #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) ||\
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| 434 | defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx)
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| 435 | /**
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| 436 | * @brief Activates the Over-Drive mode.
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| 437 | * @note This function can be used only for STM32F42xx/STM32F43xx/STM32F446xx/STM32F469xx/STM32F479xx devices.
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| 438 | * This mode allows the CPU and the core logic to operate at a higher frequency
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| 439 | * than the normal mode for a given voltage scaling (scale 1, scale 2 or scale 3).
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| 440 | * @note It is recommended to enter or exit Over-drive mode when the application is not running
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| 441 | * critical tasks and when the system clock source is either HSI or HSE.
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| 442 | * During the Over-drive switch activation, no peripheral clocks should be enabled.
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| 443 | * The peripheral clocks must be enabled once the Over-drive mode is activated.
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| 444 | * @retval HAL status
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| 445 | */
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| 446 | HAL_StatusTypeDef HAL_PWREx_EnableOverDrive(void)
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| 447 | {
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| 448 | uint32_t tickstart = 0;
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| 449 |
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| 450 | __HAL_RCC_PWR_CLK_ENABLE();
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| 451 |
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| 452 | /* Enable the Over-drive to extend the clock frequency to 180 Mhz */
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| 453 | __HAL_PWR_OVERDRIVE_ENABLE();
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| 454 |
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| 455 | /* Get tick */
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| 456 | tickstart = HAL_GetTick();
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| 457 |
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| 458 | while(!__HAL_PWR_GET_FLAG(PWR_FLAG_ODRDY))
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| 459 | {
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| 460 | if((HAL_GetTick() - tickstart ) > PWR_OVERDRIVE_TIMEOUT_VALUE)
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| 461 | {
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| 462 | return HAL_TIMEOUT;
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| 463 | }
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| 464 | }
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| 465 |
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| 466 | /* Enable the Over-drive switch */
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| 467 | __HAL_PWR_OVERDRIVESWITCHING_ENABLE();
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| 468 |
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| 469 | /* Get tick */
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| 470 | tickstart = HAL_GetTick();
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| 471 |
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| 472 | while(!__HAL_PWR_GET_FLAG(PWR_FLAG_ODSWRDY))
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| 473 | {
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| 474 | if((HAL_GetTick() - tickstart ) > PWR_OVERDRIVE_TIMEOUT_VALUE)
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| 475 | {
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| 476 | return HAL_TIMEOUT;
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| 477 | }
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| 478 | }
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| 479 | return HAL_OK;
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| 480 | }
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| 481 |
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| 482 | /**
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| 483 | * @brief Deactivates the Over-Drive mode.
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| 484 | * @note This function can be used only for STM32F42xx/STM32F43xx/STM32F446xx/STM32F469xx/STM32F479xx devices.
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| 485 | * This mode allows the CPU and the core logic to operate at a higher frequency
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| 486 | * than the normal mode for a given voltage scaling (scale 1, scale 2 or scale 3).
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| 487 | * @note It is recommended to enter or exit Over-drive mode when the application is not running
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| 488 | * critical tasks and when the system clock source is either HSI or HSE.
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| 489 | * During the Over-drive switch activation, no peripheral clocks should be enabled.
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| 490 | * The peripheral clocks must be enabled once the Over-drive mode is activated.
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| 491 | * @retval HAL status
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| 492 | */
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| 493 | HAL_StatusTypeDef HAL_PWREx_DisableOverDrive(void)
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| 494 | {
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| 495 | uint32_t tickstart = 0;
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| 496 |
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| 497 | __HAL_RCC_PWR_CLK_ENABLE();
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| 498 |
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| 499 | /* Disable the Over-drive switch */
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| 500 | __HAL_PWR_OVERDRIVESWITCHING_DISABLE();
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| 501 |
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| 502 | /* Get tick */
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| 503 | tickstart = HAL_GetTick();
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| 504 |
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| 505 | while(__HAL_PWR_GET_FLAG(PWR_FLAG_ODSWRDY))
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| 506 | {
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| 507 | if((HAL_GetTick() - tickstart ) > PWR_OVERDRIVE_TIMEOUT_VALUE)
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| 508 | {
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| 509 | return HAL_TIMEOUT;
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| 510 | }
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| 511 | }
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| 512 |
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| 513 | /* Disable the Over-drive */
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| 514 | __HAL_PWR_OVERDRIVE_DISABLE();
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| 515 |
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| 516 | /* Get tick */
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| 517 | tickstart = HAL_GetTick();
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| 518 |
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| 519 | while(__HAL_PWR_GET_FLAG(PWR_FLAG_ODRDY))
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| 520 | {
|
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| 521 | if((HAL_GetTick() - tickstart ) > PWR_OVERDRIVE_TIMEOUT_VALUE)
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| 522 | {
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| 523 | return HAL_TIMEOUT;
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| 524 | }
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| 525 | }
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| 526 |
|
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| 527 | return HAL_OK;
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| 528 | }
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| 529 |
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| 530 | /**
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| 531 | * @brief Enters in Under-Drive STOP mode.
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| 532 | *
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| 533 | * @note This mode is only available for STM32F42xxx/STM324F3xxx/STM32F446xx/STM32F469xx/STM32F479xx devices.
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| 534 | *
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| 535 | * @note This mode can be selected only when the Under-Drive is already active
|
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| 536 | *
|
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| 537 | * @note This mode is enabled only with STOP low power mode.
|
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| 538 | * In this mode, the 1.2V domain is preserved in reduced leakage mode. This
|
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| 539 | * mode is only available when the main regulator or the low power regulator
|
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| 540 | * is in low voltage mode
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| 541 | *
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| 542 | * @note If the Under-drive mode was enabled, it is automatically disabled after
|
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| 543 | * exiting Stop mode.
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---|
| 544 | * When the voltage regulator operates in Under-drive mode, an additional
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| 545 | * startup delay is induced when waking up from Stop mode.
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---|
| 546 | *
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---|
| 547 | * @note In Stop mode, all I/O pins keep the same state as in Run mode.
|
---|
| 548 | *
|
---|
| 549 | * @note When exiting Stop mode by issuing an interrupt or a wake-up event,
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| 550 | * the HSI RC oscillator is selected as system clock.
|
---|
| 551 | *
|
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| 552 | * @note When the voltage regulator operates in low power mode, an additional
|
---|
| 553 | * startup delay is incurred when waking up from Stop mode.
|
---|
| 554 | * By keeping the internal regulator ON during Stop mode, the consumption
|
---|
| 555 | * is higher although the startup time is reduced.
|
---|
| 556 | *
|
---|
| 557 | * @param Regulator: specifies the regulator state in STOP mode.
|
---|
| 558 | * This parameter can be one of the following values:
|
---|
| 559 | * @arg PWR_MAINREGULATOR_UNDERDRIVE_ON: Main Regulator in under-drive mode
|
---|
| 560 | * and Flash memory in power-down when the device is in Stop under-drive mode
|
---|
| 561 | * @arg PWR_LOWPOWERREGULATOR_UNDERDRIVE_ON: Low Power Regulator in under-drive mode
|
---|
| 562 | * and Flash memory in power-down when the device is in Stop under-drive mode
|
---|
| 563 | * @param STOPEntry: specifies if STOP mode in entered with WFI or WFE instruction.
|
---|
| 564 | * This parameter can be one of the following values:
|
---|
| 565 | * @arg PWR_SLEEPENTRY_WFI: enter STOP mode with WFI instruction
|
---|
| 566 | * @arg PWR_SLEEPENTRY_WFE: enter STOP mode with WFE instruction
|
---|
| 567 | * @retval None
|
---|
| 568 | */
|
---|
| 569 | HAL_StatusTypeDef HAL_PWREx_EnterUnderDriveSTOPMode(uint32_t Regulator, uint8_t STOPEntry)
|
---|
| 570 | {
|
---|
| 571 | uint32_t tmpreg1 = 0;
|
---|
| 572 | uint32_t tickstart = 0;
|
---|
| 573 |
|
---|
| 574 | /* Check the parameters */
|
---|
| 575 | assert_param(IS_PWR_REGULATOR_UNDERDRIVE(Regulator));
|
---|
| 576 | assert_param(IS_PWR_STOP_ENTRY(STOPEntry));
|
---|
| 577 |
|
---|
| 578 | /* Enable Power ctrl clock */
|
---|
| 579 | __HAL_RCC_PWR_CLK_ENABLE();
|
---|
| 580 | /* Enable the Under-drive Mode ---------------------------------------------*/
|
---|
| 581 | /* Clear Under-drive flag */
|
---|
| 582 | __HAL_PWR_CLEAR_ODRUDR_FLAG();
|
---|
| 583 |
|
---|
| 584 | /* Enable the Under-drive */
|
---|
| 585 | __HAL_PWR_UNDERDRIVE_ENABLE();
|
---|
| 586 |
|
---|
| 587 | /* Get tick */
|
---|
| 588 | tickstart = HAL_GetTick();
|
---|
| 589 |
|
---|
| 590 | /* Wait for UnderDrive mode is ready */
|
---|
| 591 | while(__HAL_PWR_GET_FLAG(PWR_FLAG_UDRDY))
|
---|
| 592 | {
|
---|
| 593 | if((HAL_GetTick() - tickstart ) > PWR_UDERDRIVE_TIMEOUT_VALUE)
|
---|
| 594 | {
|
---|
| 595 | return HAL_TIMEOUT;
|
---|
| 596 | }
|
---|
| 597 | }
|
---|
| 598 |
|
---|
| 599 | /* Select the regulator state in STOP mode ---------------------------------*/
|
---|
| 600 | tmpreg1 = PWR->CR;
|
---|
| 601 | /* Clear PDDS, LPDS, MRLUDS and LPLUDS bits */
|
---|
| 602 | tmpreg1 &= (uint32_t)~(PWR_CR_PDDS | PWR_CR_LPDS | PWR_CR_LPUDS | PWR_CR_MRUDS);
|
---|
| 603 |
|
---|
| 604 | /* Set LPDS, MRLUDS and LPLUDS bits according to PWR_Regulator value */
|
---|
| 605 | tmpreg1 |= Regulator;
|
---|
| 606 |
|
---|
| 607 | /* Store the new value */
|
---|
| 608 | PWR->CR = tmpreg1;
|
---|
| 609 |
|
---|
| 610 | /* Set SLEEPDEEP bit of Cortex System Control Register */
|
---|
| 611 | SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk;
|
---|
| 612 |
|
---|
| 613 | /* Select STOP mode entry --------------------------------------------------*/
|
---|
| 614 | if(STOPEntry == PWR_SLEEPENTRY_WFI)
|
---|
| 615 | {
|
---|
| 616 | /* Request Wait For Interrupt */
|
---|
| 617 | __WFI();
|
---|
| 618 | }
|
---|
| 619 | else
|
---|
| 620 | {
|
---|
| 621 | /* Request Wait For Event */
|
---|
| 622 | __WFE();
|
---|
| 623 | }
|
---|
| 624 | /* Reset SLEEPDEEP bit of Cortex System Control Register */
|
---|
| 625 | SCB->SCR &= (uint32_t)~((uint32_t)SCB_SCR_SLEEPDEEP_Msk);
|
---|
| 626 |
|
---|
| 627 | return HAL_OK;
|
---|
| 628 | }
|
---|
| 629 |
|
---|
| 630 | #endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F446xx || STM32F469xx || STM32F479xx */
|
---|
| 631 | /**
|
---|
| 632 | * @}
|
---|
| 633 | */
|
---|
| 634 |
|
---|
| 635 | /**
|
---|
| 636 | * @}
|
---|
| 637 | */
|
---|
| 638 |
|
---|
| 639 | #endif /* HAL_PWR_MODULE_ENABLED */
|
---|
| 640 | /**
|
---|
| 641 | * @}
|
---|
| 642 | */
|
---|
| 643 |
|
---|
| 644 | /**
|
---|
| 645 | * @}
|
---|
| 646 | */
|
---|
| 647 |
|
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| 648 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
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