1 | /**
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2 | ******************************************************************************
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3 | * @file stm32f4xx_hal_cortex.h
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4 | * @author MCD Application Team
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5 | * @version V1.4.1
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6 | * @date 09-October-2015
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7 | * @brief Header file of CORTEX HAL module.
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8 | ******************************************************************************
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9 | * @attention
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10 | *
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11 | * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
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12 | *
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13 | * Redistribution and use in source and binary forms, with or without modification,
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14 | * are permitted provided that the following conditions are met:
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15 | * 1. Redistributions of source code must retain the above copyright notice,
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16 | * this list of conditions and the following disclaimer.
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17 | * 2. Redistributions in binary form must reproduce the above copyright notice,
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18 | * this list of conditions and the following disclaimer in the documentation
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19 | * and/or other materials provided with the distribution.
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20 | * 3. Neither the name of STMicroelectronics nor the names of its contributors
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21 | * may be used to endorse or promote products derived from this software
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22 | * without specific prior written permission.
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23 | *
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24 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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25 | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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26 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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27 | * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
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28 | * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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29 | * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
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30 | * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
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31 | * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
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32 | * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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33 | * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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34 | *
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35 | ******************************************************************************
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36 | */
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37 |
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38 | /* Define to prevent recursive inclusion -------------------------------------*/
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39 | #ifndef __STM32F4xx_HAL_CORTEX_H
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40 | #define __STM32F4xx_HAL_CORTEX_H
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41 |
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42 | #ifdef __cplusplus
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43 | extern "C" {
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44 | #endif
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45 |
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46 | /* Includes ------------------------------------------------------------------*/
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47 | #include "stm32f4xx_hal_def.h"
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48 |
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49 | /** @addtogroup STM32F4xx_HAL_Driver
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50 | * @{
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51 | */
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52 |
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53 | /** @addtogroup CORTEX
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54 | * @{
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55 | */
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56 | /* Exported types ------------------------------------------------------------*/
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57 | /** @defgroup CORTEX_Exported_Types Cortex Exported Types
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58 | * @{
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59 | */
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60 |
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61 | #if (__MPU_PRESENT == 1)
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62 | /** @defgroup CORTEX_MPU_Region_Initialization_Structure_definition MPU Region Initialization Structure Definition
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63 | * @brief MPU Region initialization structure
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64 | * @{
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65 | */
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66 | typedef struct
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67 | {
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68 | uint8_t Enable; /*!< Specifies the status of the region.
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69 | This parameter can be a value of @ref CORTEX_MPU_Region_Enable */
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70 | uint8_t Number; /*!< Specifies the number of the region to protect.
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71 | This parameter can be a value of @ref CORTEX_MPU_Region_Number */
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72 | uint32_t BaseAddress; /*!< Specifies the base address of the region to protect. */
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73 | uint8_t Size; /*!< Specifies the size of the region to protect.
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74 | This parameter can be a value of @ref CORTEX_MPU_Region_Size */
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75 | uint8_t SubRegionDisable; /*!< Specifies the number of the subregion protection to disable.
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76 | This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF */
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77 | uint8_t TypeExtField; /*!< Specifies the TEX field level.
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78 | This parameter can be a value of @ref CORTEX_MPU_TEX_Levels */
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79 | uint8_t AccessPermission; /*!< Specifies the region access permission type.
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80 | This parameter can be a value of @ref CORTEX_MPU_Region_Permission_Attributes */
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81 | uint8_t DisableExec; /*!< Specifies the instruction access status.
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82 | This parameter can be a value of @ref CORTEX_MPU_Instruction_Access */
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83 | uint8_t IsShareable; /*!< Specifies the shareability status of the protected region.
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84 | This parameter can be a value of @ref CORTEX_MPU_Access_Shareable */
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85 | uint8_t IsCacheable; /*!< Specifies the cacheable status of the region protected.
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86 | This parameter can be a value of @ref CORTEX_MPU_Access_Cacheable */
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87 | uint8_t IsBufferable; /*!< Specifies the bufferable status of the protected region.
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88 | This parameter can be a value of @ref CORTEX_MPU_Access_Bufferable */
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89 | }MPU_Region_InitTypeDef;
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90 | /**
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91 | * @}
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92 | */
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93 | #endif /* __MPU_PRESENT */
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94 |
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95 | /**
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96 | * @}
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97 | */
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98 |
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99 | /* Exported constants --------------------------------------------------------*/
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100 |
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101 | /** @defgroup CORTEX_Exported_Constants CORTEX Exported Constants
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102 | * @{
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103 | */
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104 |
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105 | /** @defgroup CORTEX_Preemption_Priority_Group CORTEX Preemption Priority Group
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106 | * @{
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107 | */
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108 | #define NVIC_PRIORITYGROUP_0 ((uint32_t)0x00000007) /*!< 0 bits for pre-emption priority
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109 | 4 bits for subpriority */
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110 | #define NVIC_PRIORITYGROUP_1 ((uint32_t)0x00000006) /*!< 1 bits for pre-emption priority
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111 | 3 bits for subpriority */
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112 | #define NVIC_PRIORITYGROUP_2 ((uint32_t)0x00000005) /*!< 2 bits for pre-emption priority
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113 | 2 bits for subpriority */
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114 | #define NVIC_PRIORITYGROUP_3 ((uint32_t)0x00000004) /*!< 3 bits for pre-emption priority
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115 | 1 bits for subpriority */
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116 | #define NVIC_PRIORITYGROUP_4 ((uint32_t)0x00000003) /*!< 4 bits for pre-emption priority
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117 | 0 bits for subpriority */
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118 | /**
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119 | * @}
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120 | */
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121 |
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122 | /** @defgroup CORTEX_SysTick_clock_source CORTEX _SysTick clock source
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123 | * @{
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124 | */
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125 | #define SYSTICK_CLKSOURCE_HCLK_DIV8 ((uint32_t)0x00000000)
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126 | #define SYSTICK_CLKSOURCE_HCLK ((uint32_t)0x00000004)
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127 |
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128 | /**
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129 | * @}
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130 | */
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131 |
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132 | #if (__MPU_PRESENT == 1)
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133 | /** @defgroup CORTEX_MPU_HFNMI_PRIVDEF_Control MPU HFNMI and PRIVILEGED Access control
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134 | * @{
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135 | */
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136 | #define MPU_HFNMI_PRIVDEF_NONE ((uint32_t)0x00000000)
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137 | #define MPU_HARDFAULT_NMI ((uint32_t)0x00000002)
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138 | #define MPU_PRIVILEGED_DEFAULT ((uint32_t)0x00000004)
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139 | #define MPU_HFNMI_PRIVDEF ((uint32_t)0x00000006)
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140 | /**
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141 | * @}
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142 | */
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143 |
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144 | /** @defgroup CORTEX_MPU_Region_Enable CORTEX MPU Region Enable
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145 | * @{
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146 | */
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147 | #define MPU_REGION_ENABLE ((uint8_t)0x01)
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148 | #define MPU_REGION_DISABLE ((uint8_t)0x00)
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149 | /**
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150 | * @}
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151 | */
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152 |
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153 | /** @defgroup CORTEX_MPU_Instruction_Access CORTEX MPU Instruction Access
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154 | * @{
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155 | */
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156 | #define MPU_INSTRUCTION_ACCESS_ENABLE ((uint8_t)0x00)
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157 | #define MPU_INSTRUCTION_ACCESS_DISABLE ((uint8_t)0x01)
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158 | /**
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159 | * @}
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160 | */
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161 |
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162 | /** @defgroup CORTEX_MPU_Access_Shareable CORTEX MPU Instruction Access Shareable
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163 | * @{
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164 | */
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165 | #define MPU_ACCESS_SHAREABLE ((uint8_t)0x01)
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166 | #define MPU_ACCESS_NOT_SHAREABLE ((uint8_t)0x00)
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167 | /**
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168 | * @}
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169 | */
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170 |
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171 | /** @defgroup CORTEX_MPU_Access_Cacheable CORTEX MPU Instruction Access Cacheable
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172 | * @{
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173 | */
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174 | #define MPU_ACCESS_CACHEABLE ((uint8_t)0x01)
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175 | #define MPU_ACCESS_NOT_CACHEABLE ((uint8_t)0x00)
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176 | /**
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177 | * @}
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178 | */
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179 |
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180 | /** @defgroup CORTEX_MPU_Access_Bufferable CORTEX MPU Instruction Access Bufferable
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181 | * @{
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182 | */
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183 | #define MPU_ACCESS_BUFFERABLE ((uint8_t)0x01)
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184 | #define MPU_ACCESS_NOT_BUFFERABLE ((uint8_t)0x00)
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185 | /**
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186 | * @}
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187 | */
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188 |
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189 | /** @defgroup CORTEX_MPU_TEX_Levels MPU TEX Levels
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190 | * @{
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191 | */
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192 | #define MPU_TEX_LEVEL0 ((uint8_t)0x00)
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193 | #define MPU_TEX_LEVEL1 ((uint8_t)0x01)
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194 | #define MPU_TEX_LEVEL2 ((uint8_t)0x02)
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195 | /**
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196 | * @}
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197 | */
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198 |
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199 | /** @defgroup CORTEX_MPU_Region_Size CORTEX MPU Region Size
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200 | * @{
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201 | */
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202 | #define MPU_REGION_SIZE_32B ((uint8_t)0x04)
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203 | #define MPU_REGION_SIZE_64B ((uint8_t)0x05)
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204 | #define MPU_REGION_SIZE_128B ((uint8_t)0x06)
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205 | #define MPU_REGION_SIZE_256B ((uint8_t)0x07)
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206 | #define MPU_REGION_SIZE_512B ((uint8_t)0x08)
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207 | #define MPU_REGION_SIZE_1KB ((uint8_t)0x09)
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208 | #define MPU_REGION_SIZE_2KB ((uint8_t)0x0A)
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209 | #define MPU_REGION_SIZE_4KB ((uint8_t)0x0B)
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210 | #define MPU_REGION_SIZE_8KB ((uint8_t)0x0C)
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211 | #define MPU_REGION_SIZE_16KB ((uint8_t)0x0D)
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212 | #define MPU_REGION_SIZE_32KB ((uint8_t)0x0E)
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213 | #define MPU_REGION_SIZE_64KB ((uint8_t)0x0F)
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214 | #define MPU_REGION_SIZE_128KB ((uint8_t)0x10)
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215 | #define MPU_REGION_SIZE_256KB ((uint8_t)0x11)
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216 | #define MPU_REGION_SIZE_512KB ((uint8_t)0x12)
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217 | #define MPU_REGION_SIZE_1MB ((uint8_t)0x13)
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218 | #define MPU_REGION_SIZE_2MB ((uint8_t)0x14)
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219 | #define MPU_REGION_SIZE_4MB ((uint8_t)0x15)
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220 | #define MPU_REGION_SIZE_8MB ((uint8_t)0x16)
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221 | #define MPU_REGION_SIZE_16MB ((uint8_t)0x17)
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222 | #define MPU_REGION_SIZE_32MB ((uint8_t)0x18)
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223 | #define MPU_REGION_SIZE_64MB ((uint8_t)0x19)
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224 | #define MPU_REGION_SIZE_128MB ((uint8_t)0x1A)
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225 | #define MPU_REGION_SIZE_256MB ((uint8_t)0x1B)
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226 | #define MPU_REGION_SIZE_512MB ((uint8_t)0x1C)
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227 | #define MPU_REGION_SIZE_1GB ((uint8_t)0x1D)
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228 | #define MPU_REGION_SIZE_2GB ((uint8_t)0x1E)
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229 | #define MPU_REGION_SIZE_4GB ((uint8_t)0x1F)
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230 | /**
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231 | * @}
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232 | */
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233 |
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234 | /** @defgroup CORTEX_MPU_Region_Permission_Attributes CORTEX MPU Region Permission Attributes
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235 | * @{
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236 | */
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237 | #define MPU_REGION_NO_ACCESS ((uint8_t)0x00)
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238 | #define MPU_REGION_PRIV_RW ((uint8_t)0x01)
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239 | #define MPU_REGION_PRIV_RW_URO ((uint8_t)0x02)
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240 | #define MPU_REGION_FULL_ACCESS ((uint8_t)0x03)
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241 | #define MPU_REGION_PRIV_RO ((uint8_t)0x05)
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242 | #define MPU_REGION_PRIV_RO_URO ((uint8_t)0x06)
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243 | /**
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244 | * @}
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245 | */
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246 |
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247 | /** @defgroup CORTEX_MPU_Region_Number CORTEX MPU Region Number
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248 | * @{
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249 | */
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250 | #define MPU_REGION_NUMBER0 ((uint8_t)0x00)
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251 | #define MPU_REGION_NUMBER1 ((uint8_t)0x01)
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252 | #define MPU_REGION_NUMBER2 ((uint8_t)0x02)
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253 | #define MPU_REGION_NUMBER3 ((uint8_t)0x03)
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254 | #define MPU_REGION_NUMBER4 ((uint8_t)0x04)
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255 | #define MPU_REGION_NUMBER5 ((uint8_t)0x05)
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256 | #define MPU_REGION_NUMBER6 ((uint8_t)0x06)
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257 | #define MPU_REGION_NUMBER7 ((uint8_t)0x07)
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258 | /**
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259 | * @}
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260 | */
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261 | #endif /* __MPU_PRESENT */
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262 |
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263 | /**
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264 | * @}
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265 | */
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266 |
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267 |
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268 | /* Exported Macros -----------------------------------------------------------*/
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269 | /** @defgroup CORTEX_Exported_Macros CORTEX Exported Macros
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270 | * @{
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271 | */
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272 |
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273 | /** @brief Configures the SysTick clock source.
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274 | * @param __CLKSRC__: specifies the SysTick clock source.
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275 | * This parameter can be one of the following values:
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276 | * @arg SYSTICK_CLKSOURCE_HCLK_DIV8: AHB clock divided by 8 selected as SysTick clock source.
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277 | * @arg SYSTICK_CLKSOURCE_HCLK: AHB clock selected as SysTick clock source.
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278 | * @retval None
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279 | */
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280 | #define __HAL_CORTEX_SYSTICKCLK_CONFIG(__CLKSRC__) \
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281 | do { \
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282 | if ((__CLKSRC__) == SYSTICK_CLKSOURCE_HCLK) \
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283 | { \
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284 | SysTick->CTRL |= SYSTICK_CLKSOURCE_HCLK; \
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285 | } \
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286 | else \
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287 | SysTick->CTRL &= ~SYSTICK_CLKSOURCE_HCLK; \
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288 | } while(0)
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289 | /**
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290 | * @}
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291 | */
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292 |
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293 | /* Exported functions --------------------------------------------------------*/
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294 | /** @addtogroup CORTEX_Exported_Functions
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295 | * @{
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296 | */
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297 |
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298 | /** @addtogroup CORTEX_Exported_Functions_Group1
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299 | * @{
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300 | */
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301 | /* Initialization and de-initialization functions *****************************/
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302 | void HAL_NVIC_SetPriorityGrouping(uint32_t PriorityGroup);
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303 | void HAL_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority);
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304 | void HAL_NVIC_EnableIRQ(IRQn_Type IRQn);
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305 | void HAL_NVIC_DisableIRQ(IRQn_Type IRQn);
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306 | void HAL_NVIC_SystemReset(void);
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307 | uint32_t HAL_SYSTICK_Config(uint32_t TicksNumb);
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308 | /**
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309 | * @}
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310 | */
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311 |
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312 | /** @addtogroup CORTEX_Exported_Functions_Group2
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313 | * @{
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314 | */
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315 | /* Peripheral Control functions ***********************************************/
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316 | #if (__MPU_PRESENT == 1)
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317 | void HAL_MPU_ConfigRegion(MPU_Region_InitTypeDef *MPU_Init);
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318 | #endif /* __MPU_PRESENT */
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319 | uint32_t HAL_NVIC_GetPriorityGrouping(void);
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320 | void HAL_NVIC_GetPriority(IRQn_Type IRQn, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority);
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321 | uint32_t HAL_NVIC_GetPendingIRQ(IRQn_Type IRQn);
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322 | void HAL_NVIC_SetPendingIRQ(IRQn_Type IRQn);
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323 | void HAL_NVIC_ClearPendingIRQ(IRQn_Type IRQn);
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324 | uint32_t HAL_NVIC_GetActive(IRQn_Type IRQn);
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325 | void HAL_SYSTICK_CLKSourceConfig(uint32_t CLKSource);
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326 | void HAL_SYSTICK_IRQHandler(void);
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327 | void HAL_SYSTICK_Callback(void);
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328 | /**
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329 | * @}
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330 | */
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331 |
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332 | /**
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333 | * @}
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334 | */
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335 |
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336 | /* Private types -------------------------------------------------------------*/
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337 | /* Private variables ---------------------------------------------------------*/
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338 | /* Private constants ---------------------------------------------------------*/
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339 | /* Private macros ------------------------------------------------------------*/
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340 | /** @defgroup CORTEX_Private_Macros CORTEX Private Macros
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341 | * @{
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342 | */
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343 | #define IS_NVIC_PRIORITY_GROUP(GROUP) (((GROUP) == NVIC_PRIORITYGROUP_0) || \
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344 | ((GROUP) == NVIC_PRIORITYGROUP_1) || \
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345 | ((GROUP) == NVIC_PRIORITYGROUP_2) || \
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346 | ((GROUP) == NVIC_PRIORITYGROUP_3) || \
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347 | ((GROUP) == NVIC_PRIORITYGROUP_4))
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348 |
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349 | #define IS_NVIC_PREEMPTION_PRIORITY(PRIORITY) ((PRIORITY) < 0x10)
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350 |
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351 | #define IS_NVIC_SUB_PRIORITY(PRIORITY) ((PRIORITY) < 0x10)
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352 |
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353 | #define IS_NVIC_DEVICE_IRQ(IRQ) ((IRQ) >= 0x00)
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354 |
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355 | #define IS_SYSTICK_CLK_SOURCE(SOURCE) (((SOURCE) == SYSTICK_CLKSOURCE_HCLK) || \
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356 | ((SOURCE) == SYSTICK_CLKSOURCE_HCLK_DIV8))
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357 |
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358 | #if (__MPU_PRESENT == 1)
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359 | #define IS_MPU_REGION_ENABLE(STATE) (((STATE) == MPU_REGION_ENABLE) || \
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360 | ((STATE) == MPU_REGION_DISABLE))
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361 |
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362 | #define IS_MPU_INSTRUCTION_ACCESS(STATE) (((STATE) == MPU_INSTRUCTION_ACCESS_ENABLE) || \
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363 | ((STATE) == MPU_INSTRUCTION_ACCESS_DISABLE))
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364 |
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365 | #define IS_MPU_ACCESS_SHAREABLE(STATE) (((STATE) == MPU_ACCESS_SHAREABLE) || \
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366 | ((STATE) == MPU_ACCESS_NOT_SHAREABLE))
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367 |
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368 | #define IS_MPU_ACCESS_CACHEABLE(STATE) (((STATE) == MPU_ACCESS_CACHEABLE) || \
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369 | ((STATE) == MPU_ACCESS_NOT_CACHEABLE))
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370 |
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371 | #define IS_MPU_ACCESS_BUFFERABLE(STATE) (((STATE) == MPU_ACCESS_BUFFERABLE) || \
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372 | ((STATE) == MPU_ACCESS_NOT_BUFFERABLE))
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373 |
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374 | #define IS_MPU_TEX_LEVEL(TYPE) (((TYPE) == MPU_TEX_LEVEL0) || \
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375 | ((TYPE) == MPU_TEX_LEVEL1) || \
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376 | ((TYPE) == MPU_TEX_LEVEL2))
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377 |
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378 | #define IS_MPU_REGION_PERMISSION_ATTRIBUTE(TYPE) (((TYPE) == MPU_REGION_NO_ACCESS) || \
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379 | ((TYPE) == MPU_REGION_PRIV_RW) || \
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380 | ((TYPE) == MPU_REGION_PRIV_RW_URO) || \
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381 | ((TYPE) == MPU_REGION_FULL_ACCESS) || \
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382 | ((TYPE) == MPU_REGION_PRIV_RO) || \
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383 | ((TYPE) == MPU_REGION_PRIV_RO_URO))
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384 |
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385 | #define IS_MPU_REGION_NUMBER(NUMBER) (((NUMBER) == MPU_REGION_NUMBER0) || \
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386 | ((NUMBER) == MPU_REGION_NUMBER1) || \
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387 | ((NUMBER) == MPU_REGION_NUMBER2) || \
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388 | ((NUMBER) == MPU_REGION_NUMBER3) || \
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389 | ((NUMBER) == MPU_REGION_NUMBER4) || \
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390 | ((NUMBER) == MPU_REGION_NUMBER5) || \
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391 | ((NUMBER) == MPU_REGION_NUMBER6) || \
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392 | ((NUMBER) == MPU_REGION_NUMBER7))
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393 |
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394 | #define IS_MPU_REGION_SIZE(SIZE) (((SIZE) == MPU_REGION_SIZE_32B) || \
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395 | ((SIZE) == MPU_REGION_SIZE_64B) || \
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396 | ((SIZE) == MPU_REGION_SIZE_128B) || \
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397 | ((SIZE) == MPU_REGION_SIZE_256B) || \
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398 | ((SIZE) == MPU_REGION_SIZE_512B) || \
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399 | ((SIZE) == MPU_REGION_SIZE_1KB) || \
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400 | ((SIZE) == MPU_REGION_SIZE_2KB) || \
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401 | ((SIZE) == MPU_REGION_SIZE_4KB) || \
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402 | ((SIZE) == MPU_REGION_SIZE_8KB) || \
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403 | ((SIZE) == MPU_REGION_SIZE_16KB) || \
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404 | ((SIZE) == MPU_REGION_SIZE_32KB) || \
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405 | ((SIZE) == MPU_REGION_SIZE_64KB) || \
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406 | ((SIZE) == MPU_REGION_SIZE_128KB) || \
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407 | ((SIZE) == MPU_REGION_SIZE_256KB) || \
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408 | ((SIZE) == MPU_REGION_SIZE_512KB) || \
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409 | ((SIZE) == MPU_REGION_SIZE_1MB) || \
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410 | ((SIZE) == MPU_REGION_SIZE_2MB) || \
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411 | ((SIZE) == MPU_REGION_SIZE_4MB) || \
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412 | ((SIZE) == MPU_REGION_SIZE_8MB) || \
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413 | ((SIZE) == MPU_REGION_SIZE_16MB) || \
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414 | ((SIZE) == MPU_REGION_SIZE_32MB) || \
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415 | ((SIZE) == MPU_REGION_SIZE_64MB) || \
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416 | ((SIZE) == MPU_REGION_SIZE_128MB) || \
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417 | ((SIZE) == MPU_REGION_SIZE_256MB) || \
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418 | ((SIZE) == MPU_REGION_SIZE_512MB) || \
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419 | ((SIZE) == MPU_REGION_SIZE_1GB) || \
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420 | ((SIZE) == MPU_REGION_SIZE_2GB) || \
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421 | ((SIZE) == MPU_REGION_SIZE_4GB))
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422 |
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423 | #define IS_MPU_SUB_REGION_DISABLE(SUBREGION) ((SUBREGION) < (uint16_t)0x00FF)
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424 | #endif /* __MPU_PRESENT */
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425 |
|
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426 | /**
|
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427 | * @}
|
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428 | */
|
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429 |
|
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430 | /* Private functions ---------------------------------------------------------*/
|
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431 | /** @defgroup CORTEX_Private_Functions CORTEX Private Functions
|
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432 | * @brief CORTEX private functions
|
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433 | * @{
|
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434 | */
|
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435 |
|
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436 | #if (__MPU_PRESENT == 1)
|
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437 | /**
|
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438 | * @brief Disables the MPU
|
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439 | * @retval None
|
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440 | */
|
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441 | __STATIC_INLINE void HAL_MPU_Disable(void)
|
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442 | {
|
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443 | /* Disable fault exceptions */
|
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444 | SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk;
|
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445 |
|
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446 | /* Disable the MPU */
|
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447 | MPU->CTRL &= ~MPU_CTRL_ENABLE_Msk;
|
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448 | }
|
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449 |
|
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450 | /**
|
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451 | * @brief Enables the MPU
|
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452 | * @param MPU_Control: Specifies the control mode of the MPU during hard fault,
|
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453 | * NMI, FAULTMASK and privileged access to the default memory
|
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454 | * This parameter can be one of the following values:
|
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455 | * @arg MPU_HFNMI_PRIVDEF_NONE
|
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456 | * @arg MPU_HARDFAULT_NMI
|
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457 | * @arg MPU_PRIVILEGED_DEFAULT
|
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458 | * @arg MPU_HFNMI_PRIVDEF
|
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459 | * @retval None
|
---|
460 | */
|
---|
461 | __STATIC_INLINE void HAL_MPU_Enable(uint32_t MPU_Control)
|
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462 | {
|
---|
463 | /* Enable the MPU */
|
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464 | MPU->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk;
|
---|
465 |
|
---|
466 | /* Enable fault exceptions */
|
---|
467 | SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk;
|
---|
468 | }
|
---|
469 | #endif /* __MPU_PRESENT */
|
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470 |
|
---|
471 | /**
|
---|
472 | * @}
|
---|
473 | */
|
---|
474 |
|
---|
475 | /**
|
---|
476 | * @}
|
---|
477 | */
|
---|
478 |
|
---|
479 | /**
|
---|
480 | * @}
|
---|
481 | */
|
---|
482 |
|
---|
483 | #ifdef __cplusplus
|
---|
484 | }
|
---|
485 | #endif
|
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486 |
|
---|
487 | #endif /* __STM32F4xx_HAL_CORTEX_H */
|
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488 |
|
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489 |
|
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490 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
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