[303] | 1 | /**
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| 2 | ******************************************************************************
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| 3 | * @file stm32f4xx_hal_adc.h
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| 4 | * @author MCD Application Team
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| 5 | * @version V1.4.1
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| 6 | * @date 09-October-2015
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| 7 | * @brief Header file containing functions prototypes of ADC HAL library.
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| 8 | ******************************************************************************
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| 9 | * @attention
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| 10 | *
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| 11 | * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
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| 12 | *
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| 13 | * Redistribution and use in source and binary forms, with or without modification,
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| 14 | * are permitted provided that the following conditions are met:
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| 15 | * 1. Redistributions of source code must retain the above copyright notice,
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| 16 | * this list of conditions and the following disclaimer.
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| 17 | * 2. Redistributions in binary form must reproduce the above copyright notice,
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| 18 | * this list of conditions and the following disclaimer in the documentation
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| 19 | * and/or other materials provided with the distribution.
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| 20 | * 3. Neither the name of STMicroelectronics nor the names of its contributors
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| 21 | * may be used to endorse or promote products derived from this software
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| 22 | * without specific prior written permission.
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| 23 | *
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| 24 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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| 25 | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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| 26 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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| 27 | * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
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| 28 | * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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| 29 | * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
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| 30 | * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
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| 31 | * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
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| 32 | * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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| 33 | * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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| 34 | *
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| 35 | ******************************************************************************
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| 36 | */
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| 37 |
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| 38 | /* Define to prevent recursive inclusion -------------------------------------*/
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| 39 | #ifndef __STM32F4xx_ADC_H
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| 40 | #define __STM32F4xx_ADC_H
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| 41 |
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| 42 | #ifdef __cplusplus
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| 43 | extern "C" {
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| 44 | #endif
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| 45 |
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| 46 | /* Includes ------------------------------------------------------------------*/
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| 47 | #include "stm32f4xx_hal_def.h"
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| 48 |
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| 49 | /** @addtogroup STM32F4xx_HAL_Driver
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| 50 | * @{
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| 51 | */
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| 52 |
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| 53 | /** @addtogroup ADC
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| 54 | * @{
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| 55 | */
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| 56 |
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| 57 | /* Exported types ------------------------------------------------------------*/
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| 58 | /** @defgroup ADC_Exported_Types ADC Exported Types
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| 59 | * @{
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| 60 | */
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| 61 |
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| 62 | /**
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| 63 | * @brief HAL State structures definition
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| 64 | */
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| 65 | typedef enum
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| 66 | {
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| 67 | HAL_ADC_STATE_RESET = 0x00, /*!< ADC not yet initialized or disabled */
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| 68 | HAL_ADC_STATE_READY = 0x01, /*!< ADC peripheral ready for use */
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| 69 | HAL_ADC_STATE_BUSY = 0x02, /*!< An internal process is ongoing */
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| 70 | HAL_ADC_STATE_BUSY_REG = 0x12, /*!< Regular conversion is ongoing */
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| 71 | HAL_ADC_STATE_BUSY_INJ = 0x22, /*!< Injected conversion is ongoing */
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| 72 | HAL_ADC_STATE_BUSY_INJ_REG = 0x32, /*!< Injected and regular conversion are ongoing */
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| 73 | HAL_ADC_STATE_TIMEOUT = 0x03, /*!< Timeout state */
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| 74 | HAL_ADC_STATE_ERROR = 0x04, /*!< ADC state error */
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| 75 | HAL_ADC_STATE_EOC = 0x05, /*!< Conversion is completed */
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| 76 | HAL_ADC_STATE_EOC_REG = 0x15, /*!< Regular conversion is completed */
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| 77 | HAL_ADC_STATE_EOC_INJ = 0x25, /*!< Injected conversion is completed */
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| 78 | HAL_ADC_STATE_EOC_INJ_REG = 0x35, /*!< Injected and regular conversion are completed */
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| 79 | HAL_ADC_STATE_AWD = 0x06 /*!< ADC state analog watchdog */
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| 80 |
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| 81 | }HAL_ADC_StateTypeDef;
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| 82 |
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| 83 | /**
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| 84 | * @brief ADC Init structure definition
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| 85 | */
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| 86 | typedef struct
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| 87 | {
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| 88 | uint32_t ClockPrescaler; /*!< Select the frequency of the clock to the ADC. The clock is common for
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| 89 | all the ADCs.
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| 90 | This parameter can be a value of @ref ADC_ClockPrescaler */
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| 91 | uint32_t Resolution; /*!< Configures the ADC resolution dual mode.
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| 92 | This parameter can be a value of @ref ADC_Resolution */
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| 93 | uint32_t DataAlign; /*!< Specifies whether the ADC data alignment is left or right.
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| 94 | This parameter can be a value of @ref ADC_data_align */
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| 95 | uint32_t ScanConvMode; /*!< Specifies whether the conversion is performed in Scan (multi channels) or
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| 96 | Single (one channel) mode.
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| 97 | This parameter can be set to ENABLE or DISABLE */
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| 98 | uint32_t EOCSelection; /*!< Specifies whether the EOC flag is set
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| 99 | at the end of single channel conversion or at the end of all conversions.
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| 100 | This parameter can be a value of @ref ADC_EOCSelection
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| 101 | Note: Impact on overrun when not using DMA: When EOCSelection is set to ADC_EOC_SINGLE_CONV,
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| 102 | overrun detection is automatically enabled, in this case each conversion data must be read.
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| 103 | To perform ADC conversions without having to read all conversion data, this parameter must
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| 104 | be set to ADC_EOC_SEQ_CONV */
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| 105 | uint32_t ContinuousConvMode; /*!< Specifies whether the conversion is performed in Continuous or Single mode.
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| 106 | This parameter can be set to ENABLE or DISABLE. */
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| 107 | uint32_t DMAContinuousRequests; /*!< Specifies whether the DMA requests is performed in Continuous or in Single mode.
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| 108 | This parameter can be set to ENABLE or DISABLE. */
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| 109 | uint32_t NbrOfConversion; /*!< Specifies the number of ADC conversions that will be done using the sequencer for
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| 110 | regular channel group.
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| 111 | This parameter must be a number between Min_Data = 1 and Max_Data = 16. */
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| 112 | uint32_t DiscontinuousConvMode; /*!< Specifies whether the conversion is performed in Discontinuous or not
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| 113 | for regular channels.
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| 114 | This parameter can be set to ENABLE or DISABLE. */
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| 115 | uint32_t NbrOfDiscConversion; /*!< Specifies the number of ADC discontinuous conversions that will be done
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| 116 | using the sequencer for regular channel group.
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| 117 | This parameter must be a number between Min_Data = 1 and Max_Data = 8. */
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| 118 | uint32_t ExternalTrigConv; /*!< Selects the external event used to trigger the conversion start of regular group.
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| 119 | If set to ADC_SOFTWARE_START, external triggers are disabled.
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| 120 | This parameter can be a value of @ref ADC_External_trigger_Source_Regular
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| 121 | Note: This parameter can be modified only if there is no conversion is ongoing. */
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| 122 | uint32_t ExternalTrigConvEdge; /*!< Selects the external trigger edge of regular group.
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| 123 | If trigger is set to ADC_SOFTWARE_START, this parameter is discarded.
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| 124 | This parameter can be a value of @ref ADC_External_trigger_edge_Regular
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| 125 | Note: This parameter can be modified only if there is no conversion is ongoing. */
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| 126 | }ADC_InitTypeDef;
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| 127 |
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| 128 | /**
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| 129 | * @brief ADC handle Structure definition
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| 130 | */
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| 131 | typedef struct
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| 132 | {
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| 133 | ADC_TypeDef *Instance; /*!< Register base address */
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| 134 |
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| 135 | ADC_InitTypeDef Init; /*!< ADC required parameters */
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| 136 |
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| 137 | __IO uint32_t NbrOfCurrentConversionRank; /*!< ADC number of current conversion rank */
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| 138 |
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| 139 | DMA_HandleTypeDef *DMA_Handle; /*!< Pointer DMA Handler */
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| 140 |
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| 141 | HAL_LockTypeDef Lock; /*!< ADC locking object */
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| 142 |
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| 143 | __IO HAL_ADC_StateTypeDef State; /*!< ADC communication state */
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| 144 |
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| 145 | __IO uint32_t ErrorCode; /*!< ADC Error code */
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| 146 | }ADC_HandleTypeDef;
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| 147 |
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| 148 | /**
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| 149 | * @brief ADC Configuration regular Channel structure definition
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| 150 | */
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| 151 | typedef struct
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| 152 | {
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| 153 | uint32_t Channel; /*!< The ADC channel to configure.
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| 154 | This parameter can be a value of @ref ADC_channels */
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| 155 | uint32_t Rank; /*!< The rank in the regular group sequencer.
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| 156 | This parameter must be a number between Min_Data = 1 and Max_Data = 16 */
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| 157 | uint32_t SamplingTime; /*!< The sample time value to be set for the selected channel.
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| 158 | This parameter can be a value of @ref ADC_sampling_times */
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| 159 | uint32_t Offset; /*!< Reserved for future use, can be set to 0 */
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| 160 | }ADC_ChannelConfTypeDef;
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| 161 |
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| 162 | /**
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| 163 | * @brief ADC Configuration multi-mode structure definition
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| 164 | */
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| 165 | typedef struct
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| 166 | {
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| 167 | uint32_t WatchdogMode; /*!< Configures the ADC analog watchdog mode.
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| 168 | This parameter can be a value of @ref ADC_analog_watchdog_selection */
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| 169 | uint32_t HighThreshold; /*!< Configures the ADC analog watchdog High threshold value.
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| 170 | This parameter must be a 12-bit value. */
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| 171 | uint32_t LowThreshold; /*!< Configures the ADC analog watchdog High threshold value.
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| 172 | This parameter must be a 12-bit value. */
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| 173 | uint32_t Channel; /*!< Configures ADC channel for the analog watchdog.
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| 174 | This parameter has an effect only if watchdog mode is configured on single channel
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| 175 | This parameter can be a value of @ref ADC_channels */
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| 176 | uint32_t ITMode; /*!< Specifies whether the analog watchdog is configured
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| 177 | is interrupt mode or in polling mode.
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| 178 | This parameter can be set to ENABLE or DISABLE */
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| 179 | uint32_t WatchdogNumber; /*!< Reserved for future use, can be set to 0 */
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| 180 | }ADC_AnalogWDGConfTypeDef;
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| 181 | /**
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| 182 | * @}
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| 183 | */
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| 184 |
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| 185 | /* Exported constants --------------------------------------------------------*/
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| 186 | /** @defgroup ADC_Exported_Constants ADC Exported Constants
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| 187 | * @{
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| 188 | */
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| 189 |
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| 190 | /** @defgroup ADC_Error_Code ADC Error Code
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| 191 | * @{
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| 192 | */
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| 193 | #define HAL_ADC_ERROR_NONE ((uint32_t)0x00) /*!< No error */
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| 194 | #define HAL_ADC_ERROR_OVR ((uint32_t)0x01) /*!< OVR error */
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| 195 | #define HAL_ADC_ERROR_DMA ((uint32_t)0x02) /*!< DMA transfer error */
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| 196 | /**
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| 197 | * @}
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| 198 | */
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| 199 |
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| 200 |
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| 201 | /** @defgroup ADC_ClockPrescaler ADC Clock Prescaler
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| 202 | * @{
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| 203 | */
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| 204 | #define ADC_CLOCK_SYNC_PCLK_DIV2 ((uint32_t)0x00000000)
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| 205 | #define ADC_CLOCK_SYNC_PCLK_DIV4 ((uint32_t)ADC_CCR_ADCPRE_0)
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| 206 | #define ADC_CLOCK_SYNC_PCLK_DIV6 ((uint32_t)ADC_CCR_ADCPRE_1)
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| 207 | #define ADC_CLOCK_SYNC_PCLK_DIV8 ((uint32_t)ADC_CCR_ADCPRE)
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| 208 | /**
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| 209 | * @}
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| 210 | */
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| 211 |
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| 212 | /** @defgroup ADC_delay_between_2_sampling_phases ADC Delay Between 2 Sampling Phases
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| 213 | * @{
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| 214 | */
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| 215 | #define ADC_TWOSAMPLINGDELAY_5CYCLES ((uint32_t)0x00000000)
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| 216 | #define ADC_TWOSAMPLINGDELAY_6CYCLES ((uint32_t)ADC_CCR_DELAY_0)
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| 217 | #define ADC_TWOSAMPLINGDELAY_7CYCLES ((uint32_t)ADC_CCR_DELAY_1)
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| 218 | #define ADC_TWOSAMPLINGDELAY_8CYCLES ((uint32_t)(ADC_CCR_DELAY_1 | ADC_CCR_DELAY_0))
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| 219 | #define ADC_TWOSAMPLINGDELAY_9CYCLES ((uint32_t)ADC_CCR_DELAY_2)
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| 220 | #define ADC_TWOSAMPLINGDELAY_10CYCLES ((uint32_t)(ADC_CCR_DELAY_2 | ADC_CCR_DELAY_0))
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| 221 | #define ADC_TWOSAMPLINGDELAY_11CYCLES ((uint32_t)(ADC_CCR_DELAY_2 | ADC_CCR_DELAY_1))
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| 222 | #define ADC_TWOSAMPLINGDELAY_12CYCLES ((uint32_t)(ADC_CCR_DELAY_2 | ADC_CCR_DELAY_1 | ADC_CCR_DELAY_0))
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| 223 | #define ADC_TWOSAMPLINGDELAY_13CYCLES ((uint32_t)ADC_CCR_DELAY_3)
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| 224 | #define ADC_TWOSAMPLINGDELAY_14CYCLES ((uint32_t)(ADC_CCR_DELAY_3 | ADC_CCR_DELAY_0))
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| 225 | #define ADC_TWOSAMPLINGDELAY_15CYCLES ((uint32_t)(ADC_CCR_DELAY_3 | ADC_CCR_DELAY_1))
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| 226 | #define ADC_TWOSAMPLINGDELAY_16CYCLES ((uint32_t)(ADC_CCR_DELAY_3 | ADC_CCR_DELAY_1 | ADC_CCR_DELAY_0))
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| 227 | #define ADC_TWOSAMPLINGDELAY_17CYCLES ((uint32_t)(ADC_CCR_DELAY_3 | ADC_CCR_DELAY_2))
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| 228 | #define ADC_TWOSAMPLINGDELAY_18CYCLES ((uint32_t)(ADC_CCR_DELAY_3 | ADC_CCR_DELAY_2 | ADC_CCR_DELAY_0))
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| 229 | #define ADC_TWOSAMPLINGDELAY_19CYCLES ((uint32_t)(ADC_CCR_DELAY_3 | ADC_CCR_DELAY_2 | ADC_CCR_DELAY_1))
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| 230 | #define ADC_TWOSAMPLINGDELAY_20CYCLES ((uint32_t)ADC_CCR_DELAY)
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| 231 | /**
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| 232 | * @}
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| 233 | */
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| 234 |
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| 235 | /** @defgroup ADC_Resolution ADC Resolution
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| 236 | * @{
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| 237 | */
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| 238 | #define ADC_RESOLUTION_12B ((uint32_t)0x00000000)
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| 239 | #define ADC_RESOLUTION_10B ((uint32_t)ADC_CR1_RES_0)
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| 240 | #define ADC_RESOLUTION_8B ((uint32_t)ADC_CR1_RES_1)
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| 241 | #define ADC_RESOLUTION_6B ((uint32_t)ADC_CR1_RES)
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| 242 | /**
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| 243 | * @}
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| 244 | */
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| 245 |
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| 246 | /** @defgroup ADC_External_trigger_edge_Regular ADC External Trigger Edge Regular
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| 247 | * @{
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| 248 | */
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| 249 | #define ADC_EXTERNALTRIGCONVEDGE_NONE ((uint32_t)0x00000000)
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| 250 | #define ADC_EXTERNALTRIGCONVEDGE_RISING ((uint32_t)ADC_CR2_EXTEN_0)
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| 251 | #define ADC_EXTERNALTRIGCONVEDGE_FALLING ((uint32_t)ADC_CR2_EXTEN_1)
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| 252 | #define ADC_EXTERNALTRIGCONVEDGE_RISINGFALLING ((uint32_t)ADC_CR2_EXTEN)
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| 253 | /**
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| 254 | * @}
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| 255 | */
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| 256 |
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| 257 | /** @defgroup ADC_External_trigger_Source_Regular ADC External Trigger Source Regular
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| 258 | * @{
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| 259 | */
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| 260 | /* Note: Parameter ADC_SOFTWARE_START is a software parameter used for */
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| 261 | /* compatibility with other STM32 devices. */
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| 262 | #define ADC_EXTERNALTRIGCONV_T1_CC1 ((uint32_t)0x00000000)
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| 263 | #define ADC_EXTERNALTRIGCONV_T1_CC2 ((uint32_t)ADC_CR2_EXTSEL_0)
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| 264 | #define ADC_EXTERNALTRIGCONV_T1_CC3 ((uint32_t)ADC_CR2_EXTSEL_1)
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| 265 | #define ADC_EXTERNALTRIGCONV_T2_CC2 ((uint32_t)(ADC_CR2_EXTSEL_1 | ADC_CR2_EXTSEL_0))
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| 266 | #define ADC_EXTERNALTRIGCONV_T2_CC3 ((uint32_t)ADC_CR2_EXTSEL_2)
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| 267 | #define ADC_EXTERNALTRIGCONV_T2_CC4 ((uint32_t)(ADC_CR2_EXTSEL_2 | ADC_CR2_EXTSEL_0))
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| 268 | #define ADC_EXTERNALTRIGCONV_T2_TRGO ((uint32_t)(ADC_CR2_EXTSEL_2 | ADC_CR2_EXTSEL_1))
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| 269 | #define ADC_EXTERNALTRIGCONV_T3_CC1 ((uint32_t)(ADC_CR2_EXTSEL_2 | ADC_CR2_EXTSEL_1 | ADC_CR2_EXTSEL_0))
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| 270 | #define ADC_EXTERNALTRIGCONV_T3_TRGO ((uint32_t)ADC_CR2_EXTSEL_3)
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| 271 | #define ADC_EXTERNALTRIGCONV_T4_CC4 ((uint32_t)(ADC_CR2_EXTSEL_3 | ADC_CR2_EXTSEL_0))
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| 272 | #define ADC_EXTERNALTRIGCONV_T5_CC1 ((uint32_t)(ADC_CR2_EXTSEL_3 | ADC_CR2_EXTSEL_1))
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| 273 | #define ADC_EXTERNALTRIGCONV_T5_CC2 ((uint32_t)(ADC_CR2_EXTSEL_3 | ADC_CR2_EXTSEL_1 | ADC_CR2_EXTSEL_0))
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| 274 | #define ADC_EXTERNALTRIGCONV_T5_CC3 ((uint32_t)(ADC_CR2_EXTSEL_3 | ADC_CR2_EXTSEL_2))
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| 275 | #define ADC_EXTERNALTRIGCONV_T8_CC1 ((uint32_t)(ADC_CR2_EXTSEL_3 | ADC_CR2_EXTSEL_2 | ADC_CR2_EXTSEL_0))
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| 276 | #define ADC_EXTERNALTRIGCONV_T8_TRGO ((uint32_t)(ADC_CR2_EXTSEL_3 | ADC_CR2_EXTSEL_2 | ADC_CR2_EXTSEL_1))
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| 277 | #define ADC_EXTERNALTRIGCONV_Ext_IT11 ((uint32_t)ADC_CR2_EXTSEL)
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| 278 | #define ADC_SOFTWARE_START ((uint32_t)ADC_CR2_EXTSEL + 1)
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| 279 | /**
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| 280 | * @}
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| 281 | */
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| 282 |
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| 283 | /** @defgroup ADC_data_align ADC Data Align
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| 284 | * @{
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| 285 | */
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| 286 | #define ADC_DATAALIGN_RIGHT ((uint32_t)0x00000000)
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| 287 | #define ADC_DATAALIGN_LEFT ((uint32_t)ADC_CR2_ALIGN)
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| 288 | /**
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| 289 | * @}
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| 290 | */
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| 291 |
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| 292 | /** @defgroup ADC_channels ADC Common Channels
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| 293 | * @{
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| 294 | */
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| 295 | #define ADC_CHANNEL_0 ((uint32_t)0x00000000)
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| 296 | #define ADC_CHANNEL_1 ((uint32_t)ADC_CR1_AWDCH_0)
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| 297 | #define ADC_CHANNEL_2 ((uint32_t)ADC_CR1_AWDCH_1)
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| 298 | #define ADC_CHANNEL_3 ((uint32_t)(ADC_CR1_AWDCH_1 | ADC_CR1_AWDCH_0))
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| 299 | #define ADC_CHANNEL_4 ((uint32_t)ADC_CR1_AWDCH_2)
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| 300 | #define ADC_CHANNEL_5 ((uint32_t)(ADC_CR1_AWDCH_2 | ADC_CR1_AWDCH_0))
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| 301 | #define ADC_CHANNEL_6 ((uint32_t)(ADC_CR1_AWDCH_2 | ADC_CR1_AWDCH_1))
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| 302 | #define ADC_CHANNEL_7 ((uint32_t)(ADC_CR1_AWDCH_2 | ADC_CR1_AWDCH_1 | ADC_CR1_AWDCH_0))
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| 303 | #define ADC_CHANNEL_8 ((uint32_t)ADC_CR1_AWDCH_3)
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| 304 | #define ADC_CHANNEL_9 ((uint32_t)(ADC_CR1_AWDCH_3 | ADC_CR1_AWDCH_0))
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| 305 | #define ADC_CHANNEL_10 ((uint32_t)(ADC_CR1_AWDCH_3 | ADC_CR1_AWDCH_1))
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| 306 | #define ADC_CHANNEL_11 ((uint32_t)(ADC_CR1_AWDCH_3 | ADC_CR1_AWDCH_1 | ADC_CR1_AWDCH_0))
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| 307 | #define ADC_CHANNEL_12 ((uint32_t)(ADC_CR1_AWDCH_3 | ADC_CR1_AWDCH_2))
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| 308 | #define ADC_CHANNEL_13 ((uint32_t)(ADC_CR1_AWDCH_3 | ADC_CR1_AWDCH_2 | ADC_CR1_AWDCH_0))
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| 309 | #define ADC_CHANNEL_14 ((uint32_t)(ADC_CR1_AWDCH_3 | ADC_CR1_AWDCH_2 | ADC_CR1_AWDCH_1))
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| 310 | #define ADC_CHANNEL_15 ((uint32_t)(ADC_CR1_AWDCH_3 | ADC_CR1_AWDCH_2 | ADC_CR1_AWDCH_1 | ADC_CR1_AWDCH_0))
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| 311 | #define ADC_CHANNEL_16 ((uint32_t)ADC_CR1_AWDCH_4)
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| 312 | #define ADC_CHANNEL_17 ((uint32_t)(ADC_CR1_AWDCH_4 | ADC_CR1_AWDCH_0))
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| 313 | #define ADC_CHANNEL_18 ((uint32_t)(ADC_CR1_AWDCH_4 | ADC_CR1_AWDCH_1))
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| 314 |
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| 315 | #define ADC_CHANNEL_VREFINT ((uint32_t)ADC_CHANNEL_17)
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| 316 | #define ADC_CHANNEL_VBAT ((uint32_t)ADC_CHANNEL_18)
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| 317 | /**
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| 318 | * @}
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| 319 | */
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| 320 |
|
---|
| 321 | /** @defgroup ADC_sampling_times ADC Sampling Times
|
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| 322 | * @{
|
---|
| 323 | */
|
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| 324 | #define ADC_SAMPLETIME_3CYCLES ((uint32_t)0x00000000)
|
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| 325 | #define ADC_SAMPLETIME_15CYCLES ((uint32_t)ADC_SMPR1_SMP10_0)
|
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| 326 | #define ADC_SAMPLETIME_28CYCLES ((uint32_t)ADC_SMPR1_SMP10_1)
|
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| 327 | #define ADC_SAMPLETIME_56CYCLES ((uint32_t)(ADC_SMPR1_SMP10_1 | ADC_SMPR1_SMP10_0))
|
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| 328 | #define ADC_SAMPLETIME_84CYCLES ((uint32_t)ADC_SMPR1_SMP10_2)
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| 329 | #define ADC_SAMPLETIME_112CYCLES ((uint32_t)(ADC_SMPR1_SMP10_2 | ADC_SMPR1_SMP10_0))
|
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| 330 | #define ADC_SAMPLETIME_144CYCLES ((uint32_t)(ADC_SMPR1_SMP10_2 | ADC_SMPR1_SMP10_1))
|
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| 331 | #define ADC_SAMPLETIME_480CYCLES ((uint32_t)ADC_SMPR1_SMP10)
|
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| 332 | /**
|
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| 333 | * @}
|
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| 334 | */
|
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| 335 |
|
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| 336 | /** @defgroup ADC_EOCSelection ADC EOC Selection
|
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| 337 | * @{
|
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| 338 | */
|
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| 339 | #define ADC_EOC_SEQ_CONV ((uint32_t)0x00000000)
|
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| 340 | #define ADC_EOC_SINGLE_CONV ((uint32_t)0x00000001)
|
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| 341 | #define ADC_EOC_SINGLE_SEQ_CONV ((uint32_t)0x00000002) /*!< reserved for future use */
|
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| 342 | /**
|
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| 343 | * @}
|
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| 344 | */
|
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| 345 |
|
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| 346 | /** @defgroup ADC_Event_type ADC Event Type
|
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| 347 | * @{
|
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| 348 | */
|
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| 349 | #define ADC_AWD_EVENT ((uint32_t)ADC_FLAG_AWD)
|
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| 350 | #define ADC_OVR_EVENT ((uint32_t)ADC_FLAG_OVR)
|
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| 351 | /**
|
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| 352 | * @}
|
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| 353 | */
|
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| 354 |
|
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| 355 | /** @defgroup ADC_analog_watchdog_selection ADC Analog Watchdog Selection
|
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| 356 | * @{
|
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| 357 | */
|
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| 358 | #define ADC_ANALOGWATCHDOG_SINGLE_REG ((uint32_t)(ADC_CR1_AWDSGL | ADC_CR1_AWDEN))
|
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| 359 | #define ADC_ANALOGWATCHDOG_SINGLE_INJEC ((uint32_t)(ADC_CR1_AWDSGL | ADC_CR1_JAWDEN))
|
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| 360 | #define ADC_ANALOGWATCHDOG_SINGLE_REGINJEC ((uint32_t)(ADC_CR1_AWDSGL | ADC_CR1_AWDEN | ADC_CR1_JAWDEN))
|
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| 361 | #define ADC_ANALOGWATCHDOG_ALL_REG ((uint32_t)ADC_CR1_AWDEN)
|
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| 362 | #define ADC_ANALOGWATCHDOG_ALL_INJEC ((uint32_t)ADC_CR1_JAWDEN)
|
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| 363 | #define ADC_ANALOGWATCHDOG_ALL_REGINJEC ((uint32_t)(ADC_CR1_AWDEN | ADC_CR1_JAWDEN))
|
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| 364 | #define ADC_ANALOGWATCHDOG_NONE ((uint32_t)0x00000000)
|
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| 365 | /**
|
---|
| 366 | * @}
|
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| 367 | */
|
---|
| 368 |
|
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| 369 | /** @defgroup ADC_interrupts_definition ADC Interrupts Definition
|
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| 370 | * @{
|
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| 371 | */
|
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| 372 | #define ADC_IT_EOC ((uint32_t)ADC_CR1_EOCIE)
|
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| 373 | #define ADC_IT_AWD ((uint32_t)ADC_CR1_AWDIE)
|
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| 374 | #define ADC_IT_JEOC ((uint32_t)ADC_CR1_JEOCIE)
|
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| 375 | #define ADC_IT_OVR ((uint32_t)ADC_CR1_OVRIE)
|
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| 376 | /**
|
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| 377 | * @}
|
---|
| 378 | */
|
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| 379 |
|
---|
| 380 | /** @defgroup ADC_flags_definition ADC Flags Definition
|
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| 381 | * @{
|
---|
| 382 | */
|
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| 383 | #define ADC_FLAG_AWD ((uint32_t)ADC_SR_AWD)
|
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| 384 | #define ADC_FLAG_EOC ((uint32_t)ADC_SR_EOC)
|
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| 385 | #define ADC_FLAG_JEOC ((uint32_t)ADC_SR_JEOC)
|
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| 386 | #define ADC_FLAG_JSTRT ((uint32_t)ADC_SR_JSTRT)
|
---|
| 387 | #define ADC_FLAG_STRT ((uint32_t)ADC_SR_STRT)
|
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| 388 | #define ADC_FLAG_OVR ((uint32_t)ADC_SR_OVR)
|
---|
| 389 | /**
|
---|
| 390 | * @}
|
---|
| 391 | */
|
---|
| 392 |
|
---|
| 393 | /** @defgroup ADC_channels_type ADC Channels Type
|
---|
| 394 | * @{
|
---|
| 395 | */
|
---|
| 396 | #define ADC_ALL_CHANNELS ((uint32_t)0x00000001)
|
---|
| 397 | #define ADC_REGULAR_CHANNELS ((uint32_t)0x00000002) /*!< reserved for future use */
|
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| 398 | #define ADC_INJECTED_CHANNELS ((uint32_t)0x00000003) /*!< reserved for future use */
|
---|
| 399 | /**
|
---|
| 400 | * @}
|
---|
| 401 | */
|
---|
| 402 |
|
---|
| 403 | /**
|
---|
| 404 | * @}
|
---|
| 405 | */
|
---|
| 406 |
|
---|
| 407 | /* Exported macro ------------------------------------------------------------*/
|
---|
| 408 | /** @defgroup ADC_Exported_Macros ADC Exported Macros
|
---|
| 409 | * @{
|
---|
| 410 | */
|
---|
| 411 |
|
---|
| 412 | /** @brief Reset ADC handle state
|
---|
| 413 | * @param __HANDLE__: ADC handle
|
---|
| 414 | * @retval None
|
---|
| 415 | */
|
---|
| 416 | #define __HAL_ADC_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_ADC_STATE_RESET)
|
---|
| 417 |
|
---|
| 418 | /**
|
---|
| 419 | * @brief Enable the ADC peripheral.
|
---|
| 420 | * @param __HANDLE__: ADC handle
|
---|
| 421 | * @retval None
|
---|
| 422 | */
|
---|
| 423 | #define __HAL_ADC_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR2 |= ADC_CR2_ADON)
|
---|
| 424 |
|
---|
| 425 | /**
|
---|
| 426 | * @brief Disable the ADC peripheral.
|
---|
| 427 | * @param __HANDLE__: ADC handle
|
---|
| 428 | * @retval None
|
---|
| 429 | */
|
---|
| 430 | #define __HAL_ADC_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR2 &= ~ADC_CR2_ADON)
|
---|
| 431 |
|
---|
| 432 | /**
|
---|
| 433 | * @brief Enable the ADC end of conversion interrupt.
|
---|
| 434 | * @param __HANDLE__: specifies the ADC Handle.
|
---|
| 435 | * @param __INTERRUPT__: ADC Interrupt.
|
---|
| 436 | * @retval None
|
---|
| 437 | */
|
---|
| 438 | #define __HAL_ADC_ENABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CR1) |= (__INTERRUPT__))
|
---|
| 439 |
|
---|
| 440 | /**
|
---|
| 441 | * @brief Disable the ADC end of conversion interrupt.
|
---|
| 442 | * @param __HANDLE__: specifies the ADC Handle.
|
---|
| 443 | * @param __INTERRUPT__: ADC interrupt.
|
---|
| 444 | * @retval None
|
---|
| 445 | */
|
---|
| 446 | #define __HAL_ADC_DISABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CR1) &= ~(__INTERRUPT__))
|
---|
| 447 |
|
---|
| 448 | /** @brief Check if the specified ADC interrupt source is enabled or disabled.
|
---|
| 449 | * @param __HANDLE__: specifies the ADC Handle.
|
---|
| 450 | * @param __INTERRUPT__: specifies the ADC interrupt source to check.
|
---|
| 451 | * @retval The new state of __IT__ (TRUE or FALSE).
|
---|
| 452 | */
|
---|
| 453 | #define __HAL_ADC_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CR1 & (__INTERRUPT__)) == (__INTERRUPT__))
|
---|
| 454 |
|
---|
| 455 | /**
|
---|
| 456 | * @brief Clear the ADC's pending flags.
|
---|
| 457 | * @param __HANDLE__: specifies the ADC Handle.
|
---|
| 458 | * @param __FLAG__: ADC flag.
|
---|
| 459 | * @retval None
|
---|
| 460 | */
|
---|
| 461 | #define __HAL_ADC_CLEAR_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR) = ~(__FLAG__))
|
---|
| 462 |
|
---|
| 463 | /**
|
---|
| 464 | * @brief Get the selected ADC's flag status.
|
---|
| 465 | * @param __HANDLE__: specifies the ADC Handle.
|
---|
| 466 | * @param __FLAG__: ADC flag.
|
---|
| 467 | * @retval None
|
---|
| 468 | */
|
---|
| 469 | #define __HAL_ADC_GET_FLAG(__HANDLE__, __FLAG__) ((((__HANDLE__)->Instance->SR) & (__FLAG__)) == (__FLAG__))
|
---|
| 470 |
|
---|
| 471 | /**
|
---|
| 472 | * @}
|
---|
| 473 | */
|
---|
| 474 |
|
---|
| 475 | /* Include ADC HAL Extension module */
|
---|
| 476 | #include "stm32f4xx_hal_adc_ex.h"
|
---|
| 477 |
|
---|
| 478 | /* Exported functions --------------------------------------------------------*/
|
---|
| 479 | /** @addtogroup ADC_Exported_Functions
|
---|
| 480 | * @{
|
---|
| 481 | */
|
---|
| 482 |
|
---|
| 483 | /** @addtogroup ADC_Exported_Functions_Group1
|
---|
| 484 | * @{
|
---|
| 485 | */
|
---|
| 486 | /* Initialization/de-initialization functions ***********************************/
|
---|
| 487 | HAL_StatusTypeDef HAL_ADC_Init(ADC_HandleTypeDef* hadc);
|
---|
| 488 | HAL_StatusTypeDef HAL_ADC_DeInit(ADC_HandleTypeDef *hadc);
|
---|
| 489 | void HAL_ADC_MspInit(ADC_HandleTypeDef* hadc);
|
---|
| 490 | void HAL_ADC_MspDeInit(ADC_HandleTypeDef* hadc);
|
---|
| 491 | /**
|
---|
| 492 | * @}
|
---|
| 493 | */
|
---|
| 494 |
|
---|
| 495 | /** @addtogroup ADC_Exported_Functions_Group2
|
---|
| 496 | * @{
|
---|
| 497 | */
|
---|
| 498 | /* I/O operation functions ******************************************************/
|
---|
| 499 | HAL_StatusTypeDef HAL_ADC_Start(ADC_HandleTypeDef* hadc);
|
---|
| 500 | HAL_StatusTypeDef HAL_ADC_Stop(ADC_HandleTypeDef* hadc);
|
---|
| 501 | HAL_StatusTypeDef HAL_ADC_PollForConversion(ADC_HandleTypeDef* hadc, uint32_t Timeout);
|
---|
| 502 |
|
---|
| 503 | HAL_StatusTypeDef HAL_ADC_PollForEvent(ADC_HandleTypeDef* hadc, uint32_t EventType, uint32_t Timeout);
|
---|
| 504 |
|
---|
| 505 | HAL_StatusTypeDef HAL_ADC_Start_IT(ADC_HandleTypeDef* hadc);
|
---|
| 506 | HAL_StatusTypeDef HAL_ADC_Stop_IT(ADC_HandleTypeDef* hadc);
|
---|
| 507 |
|
---|
| 508 | void HAL_ADC_IRQHandler(ADC_HandleTypeDef* hadc);
|
---|
| 509 |
|
---|
| 510 | HAL_StatusTypeDef HAL_ADC_Start_DMA(ADC_HandleTypeDef* hadc, uint32_t* pData, uint32_t Length);
|
---|
| 511 | HAL_StatusTypeDef HAL_ADC_Stop_DMA(ADC_HandleTypeDef* hadc);
|
---|
| 512 |
|
---|
| 513 | uint32_t HAL_ADC_GetValue(ADC_HandleTypeDef* hadc);
|
---|
| 514 |
|
---|
| 515 | void HAL_ADC_ConvCpltCallback(ADC_HandleTypeDef* hadc);
|
---|
| 516 | void HAL_ADC_ConvHalfCpltCallback(ADC_HandleTypeDef* hadc);
|
---|
| 517 | void HAL_ADC_LevelOutOfWindowCallback(ADC_HandleTypeDef* hadc);
|
---|
| 518 | void HAL_ADC_ErrorCallback(ADC_HandleTypeDef *hadc);
|
---|
| 519 | /**
|
---|
| 520 | * @}
|
---|
| 521 | */
|
---|
| 522 |
|
---|
| 523 | /** @addtogroup ADC_Exported_Functions_Group3
|
---|
| 524 | * @{
|
---|
| 525 | */
|
---|
| 526 | /* Peripheral Control functions *************************************************/
|
---|
| 527 | HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef* hadc, ADC_ChannelConfTypeDef* sConfig);
|
---|
| 528 | HAL_StatusTypeDef HAL_ADC_AnalogWDGConfig(ADC_HandleTypeDef* hadc, ADC_AnalogWDGConfTypeDef* AnalogWDGConfig);
|
---|
| 529 | /**
|
---|
| 530 | * @}
|
---|
| 531 | */
|
---|
| 532 |
|
---|
| 533 | /** @addtogroup ADC_Exported_Functions_Group4
|
---|
| 534 | * @{
|
---|
| 535 | */
|
---|
| 536 | /* Peripheral State functions ***************************************************/
|
---|
| 537 | HAL_ADC_StateTypeDef HAL_ADC_GetState(ADC_HandleTypeDef* hadc);
|
---|
| 538 | uint32_t HAL_ADC_GetError(ADC_HandleTypeDef *hadc);
|
---|
| 539 | /**
|
---|
| 540 | * @}
|
---|
| 541 | */
|
---|
| 542 |
|
---|
| 543 | /**
|
---|
| 544 | * @}
|
---|
| 545 | */
|
---|
| 546 | /* Private types -------------------------------------------------------------*/
|
---|
| 547 | /* Private variables ---------------------------------------------------------*/
|
---|
| 548 | /* Private constants ---------------------------------------------------------*/
|
---|
| 549 | /** @defgroup ADC_Private_Constants ADC Private Constants
|
---|
| 550 | * @{
|
---|
| 551 | */
|
---|
| 552 | /* Delay for ADC stabilization time. */
|
---|
| 553 | /* Maximum delay is 1us (refer to device datasheet, parameter tSTAB). */
|
---|
| 554 | /* Unit: us */
|
---|
| 555 | #define ADC_STAB_DELAY_US ((uint32_t) 3)
|
---|
| 556 | /* Delay for temperature sensor stabilization time. */
|
---|
| 557 | /* Maximum delay is 10us (refer to device datasheet, parameter tSTART). */
|
---|
| 558 | /* Unit: us */
|
---|
| 559 | #define ADC_TEMPSENSOR_DELAY_US ((uint32_t) 10)
|
---|
| 560 | /**
|
---|
| 561 | * @}
|
---|
| 562 | */
|
---|
| 563 |
|
---|
| 564 | /* Private macros ------------------------------------------------------------*/
|
---|
| 565 | /** @defgroup ADC_Private_Macros ADC Private Macros
|
---|
| 566 | * @{
|
---|
| 567 | */
|
---|
| 568 | #define IS_ADC_CLOCKPRESCALER(ADC_CLOCK) (((ADC_CLOCK) == ADC_CLOCK_SYNC_PCLK_DIV2) || \
|
---|
| 569 | ((ADC_CLOCK) == ADC_CLOCK_SYNC_PCLK_DIV4) || \
|
---|
| 570 | ((ADC_CLOCK) == ADC_CLOCK_SYNC_PCLK_DIV6) || \
|
---|
| 571 | ((ADC_CLOCK) == ADC_CLOCK_SYNC_PCLK_DIV8))
|
---|
| 572 | #define IS_ADC_SAMPLING_DELAY(DELAY) (((DELAY) == ADC_TWOSAMPLINGDELAY_5CYCLES) || \
|
---|
| 573 | ((DELAY) == ADC_TWOSAMPLINGDELAY_6CYCLES) || \
|
---|
| 574 | ((DELAY) == ADC_TWOSAMPLINGDELAY_7CYCLES) || \
|
---|
| 575 | ((DELAY) == ADC_TWOSAMPLINGDELAY_8CYCLES) || \
|
---|
| 576 | ((DELAY) == ADC_TWOSAMPLINGDELAY_9CYCLES) || \
|
---|
| 577 | ((DELAY) == ADC_TWOSAMPLINGDELAY_10CYCLES) || \
|
---|
| 578 | ((DELAY) == ADC_TWOSAMPLINGDELAY_11CYCLES) || \
|
---|
| 579 | ((DELAY) == ADC_TWOSAMPLINGDELAY_12CYCLES) || \
|
---|
| 580 | ((DELAY) == ADC_TWOSAMPLINGDELAY_13CYCLES) || \
|
---|
| 581 | ((DELAY) == ADC_TWOSAMPLINGDELAY_14CYCLES) || \
|
---|
| 582 | ((DELAY) == ADC_TWOSAMPLINGDELAY_15CYCLES) || \
|
---|
| 583 | ((DELAY) == ADC_TWOSAMPLINGDELAY_16CYCLES) || \
|
---|
| 584 | ((DELAY) == ADC_TWOSAMPLINGDELAY_17CYCLES) || \
|
---|
| 585 | ((DELAY) == ADC_TWOSAMPLINGDELAY_18CYCLES) || \
|
---|
| 586 | ((DELAY) == ADC_TWOSAMPLINGDELAY_19CYCLES) || \
|
---|
| 587 | ((DELAY) == ADC_TWOSAMPLINGDELAY_20CYCLES))
|
---|
| 588 | #define IS_ADC_RESOLUTION(RESOLUTION) (((RESOLUTION) == ADC_RESOLUTION_12B) || \
|
---|
| 589 | ((RESOLUTION) == ADC_RESOLUTION_10B) || \
|
---|
| 590 | ((RESOLUTION) == ADC_RESOLUTION_8B) || \
|
---|
| 591 | ((RESOLUTION) == ADC_RESOLUTION_6B))
|
---|
| 592 | #define IS_ADC_EXT_TRIG_EDGE(EDGE) (((EDGE) == ADC_EXTERNALTRIGCONVEDGE_NONE) || \
|
---|
| 593 | ((EDGE) == ADC_EXTERNALTRIGCONVEDGE_RISING) || \
|
---|
| 594 | ((EDGE) == ADC_EXTERNALTRIGCONVEDGE_FALLING) || \
|
---|
| 595 | ((EDGE) == ADC_EXTERNALTRIGCONVEDGE_RISINGFALLING))
|
---|
| 596 | #define IS_ADC_EXT_TRIG(REGTRIG) (((REGTRIG) == ADC_EXTERNALTRIGCONV_T1_CC1) || \
|
---|
| 597 | ((REGTRIG) == ADC_EXTERNALTRIGCONV_T1_CC2) || \
|
---|
| 598 | ((REGTRIG) == ADC_EXTERNALTRIGCONV_T1_CC3) || \
|
---|
| 599 | ((REGTRIG) == ADC_EXTERNALTRIGCONV_T2_CC2) || \
|
---|
| 600 | ((REGTRIG) == ADC_EXTERNALTRIGCONV_T2_CC3) || \
|
---|
| 601 | ((REGTRIG) == ADC_EXTERNALTRIGCONV_T2_CC4) || \
|
---|
| 602 | ((REGTRIG) == ADC_EXTERNALTRIGCONV_T2_TRGO) || \
|
---|
| 603 | ((REGTRIG) == ADC_EXTERNALTRIGCONV_T3_CC1) || \
|
---|
| 604 | ((REGTRIG) == ADC_EXTERNALTRIGCONV_T3_TRGO) || \
|
---|
| 605 | ((REGTRIG) == ADC_EXTERNALTRIGCONV_T4_CC4) || \
|
---|
| 606 | ((REGTRIG) == ADC_EXTERNALTRIGCONV_T5_CC1) || \
|
---|
| 607 | ((REGTRIG) == ADC_EXTERNALTRIGCONV_T5_CC2) || \
|
---|
| 608 | ((REGTRIG) == ADC_EXTERNALTRIGCONV_T5_CC3) || \
|
---|
| 609 | ((REGTRIG) == ADC_EXTERNALTRIGCONV_T8_CC1) || \
|
---|
| 610 | ((REGTRIG) == ADC_EXTERNALTRIGCONV_T8_TRGO) || \
|
---|
| 611 | ((REGTRIG) == ADC_EXTERNALTRIGCONV_Ext_IT11)|| \
|
---|
| 612 | ((REGTRIG) == ADC_SOFTWARE_START))
|
---|
| 613 | #define IS_ADC_DATA_ALIGN(ALIGN) (((ALIGN) == ADC_DATAALIGN_RIGHT) || \
|
---|
| 614 | ((ALIGN) == ADC_DATAALIGN_LEFT))
|
---|
| 615 | #define IS_ADC_SAMPLE_TIME(TIME) (((TIME) == ADC_SAMPLETIME_3CYCLES) || \
|
---|
| 616 | ((TIME) == ADC_SAMPLETIME_15CYCLES) || \
|
---|
| 617 | ((TIME) == ADC_SAMPLETIME_28CYCLES) || \
|
---|
| 618 | ((TIME) == ADC_SAMPLETIME_56CYCLES) || \
|
---|
| 619 | ((TIME) == ADC_SAMPLETIME_84CYCLES) || \
|
---|
| 620 | ((TIME) == ADC_SAMPLETIME_112CYCLES) || \
|
---|
| 621 | ((TIME) == ADC_SAMPLETIME_144CYCLES) || \
|
---|
| 622 | ((TIME) == ADC_SAMPLETIME_480CYCLES))
|
---|
| 623 | #define IS_ADC_EOCSelection(EOCSelection) (((EOCSelection) == ADC_EOC_SINGLE_CONV) || \
|
---|
| 624 | ((EOCSelection) == ADC_EOC_SEQ_CONV) || \
|
---|
| 625 | ((EOCSelection) == ADC_EOC_SINGLE_SEQ_CONV))
|
---|
| 626 | #define IS_ADC_EVENT_TYPE(EVENT) (((EVENT) == ADC_AWD_EVENT) || \
|
---|
| 627 | ((EVENT) == ADC_OVR_EVENT))
|
---|
| 628 | #define IS_ADC_ANALOG_WATCHDOG(WATCHDOG) (((WATCHDOG) == ADC_ANALOGWATCHDOG_SINGLE_REG) || \
|
---|
| 629 | ((WATCHDOG) == ADC_ANALOGWATCHDOG_SINGLE_INJEC) || \
|
---|
| 630 | ((WATCHDOG) == ADC_ANALOGWATCHDOG_SINGLE_REGINJEC) || \
|
---|
| 631 | ((WATCHDOG) == ADC_ANALOGWATCHDOG_ALL_REG) || \
|
---|
| 632 | ((WATCHDOG) == ADC_ANALOGWATCHDOG_ALL_INJEC) || \
|
---|
| 633 | ((WATCHDOG) == ADC_ANALOGWATCHDOG_ALL_REGINJEC) || \
|
---|
| 634 | ((WATCHDOG) == ADC_ANALOGWATCHDOG_NONE))
|
---|
| 635 | #define IS_ADC_CHANNELS_TYPE(CHANNEL_TYPE) (((CHANNEL_TYPE) == ADC_ALL_CHANNELS) || \
|
---|
| 636 | ((CHANNEL_TYPE) == ADC_REGULAR_CHANNELS) || \
|
---|
| 637 | ((CHANNEL_TYPE) == ADC_INJECTED_CHANNELS))
|
---|
| 638 | #define IS_ADC_THRESHOLD(THRESHOLD) ((THRESHOLD) <= ((uint32_t)0xFFF))
|
---|
| 639 |
|
---|
| 640 | #define IS_ADC_REGULAR_LENGTH(LENGTH) (((LENGTH) >= ((uint32_t)1)) && ((LENGTH) <= ((uint32_t)16)))
|
---|
| 641 | #define IS_ADC_REGULAR_RANK(RANK) (((RANK) >= ((uint32_t)1)) && ((RANK) <= ((uint32_t)16)))
|
---|
| 642 | #define IS_ADC_REGULAR_DISC_NUMBER(NUMBER) (((NUMBER) >= ((uint32_t)1)) && ((NUMBER) <= ((uint32_t)8)))
|
---|
| 643 | #define IS_ADC_RANGE(RESOLUTION, ADC_VALUE) \
|
---|
| 644 | ((((RESOLUTION) == ADC_RESOLUTION_12B) && ((ADC_VALUE) <= ((uint32_t)0x0FFF))) || \
|
---|
| 645 | (((RESOLUTION) == ADC_RESOLUTION_10B) && ((ADC_VALUE) <= ((uint32_t)0x03FF))) || \
|
---|
| 646 | (((RESOLUTION) == ADC_RESOLUTION_8B) && ((ADC_VALUE) <= ((uint32_t)0x00FF))) || \
|
---|
| 647 | (((RESOLUTION) == ADC_RESOLUTION_6B) && ((ADC_VALUE) <= ((uint32_t)0x003F))))
|
---|
| 648 |
|
---|
| 649 | /**
|
---|
| 650 | * @brief Set ADC Regular channel sequence length.
|
---|
| 651 | * @param _NbrOfConversion_: Regular channel sequence length.
|
---|
| 652 | * @retval None
|
---|
| 653 | */
|
---|
| 654 | #define ADC_SQR1(_NbrOfConversion_) (((_NbrOfConversion_) - (uint8_t)1) << 20)
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| 655 |
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| 656 | /**
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| 657 | * @brief Set the ADC's sample time for channel numbers between 10 and 18.
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| 658 | * @param _SAMPLETIME_: Sample time parameter.
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| 659 | * @param _CHANNELNB_: Channel number.
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| 660 | * @retval None
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| 661 | */
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| 662 | #define ADC_SMPR1(_SAMPLETIME_, _CHANNELNB_) ((_SAMPLETIME_) << (3 * (((uint32_t)((uint16_t)(_CHANNELNB_))) - 10)))
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| 663 |
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| 664 | /**
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| 665 | * @brief Set the ADC's sample time for channel numbers between 0 and 9.
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| 666 | * @param _SAMPLETIME_: Sample time parameter.
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| 667 | * @param _CHANNELNB_: Channel number.
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| 668 | * @retval None
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| 669 | */
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| 670 | #define ADC_SMPR2(_SAMPLETIME_, _CHANNELNB_) ((_SAMPLETIME_) << (3 * ((uint32_t)((uint16_t)(_CHANNELNB_)))))
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| 671 |
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| 672 | /**
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| 673 | * @brief Set the selected regular channel rank for rank between 1 and 6.
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| 674 | * @param _CHANNELNB_: Channel number.
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| 675 | * @param _RANKNB_: Rank number.
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| 676 | * @retval None
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| 677 | */
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| 678 | #define ADC_SQR3_RK(_CHANNELNB_, _RANKNB_) (((uint32_t)((uint16_t)(_CHANNELNB_))) << (5 * ((_RANKNB_) - 1)))
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| 679 |
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| 680 | /**
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| 681 | * @brief Set the selected regular channel rank for rank between 7 and 12.
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| 682 | * @param _CHANNELNB_: Channel number.
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| 683 | * @param _RANKNB_: Rank number.
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| 684 | * @retval None
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| 685 | */
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| 686 | #define ADC_SQR2_RK(_CHANNELNB_, _RANKNB_) (((uint32_t)((uint16_t)(_CHANNELNB_))) << (5 * ((_RANKNB_) - 7)))
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| 687 |
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| 688 | /**
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| 689 | * @brief Set the selected regular channel rank for rank between 13 and 16.
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| 690 | * @param _CHANNELNB_: Channel number.
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| 691 | * @param _RANKNB_: Rank number.
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| 692 | * @retval None
|
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| 693 | */
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| 694 | #define ADC_SQR1_RK(_CHANNELNB_, _RANKNB_) (((uint32_t)((uint16_t)(_CHANNELNB_))) << (5 * ((_RANKNB_) - 13)))
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| 695 |
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| 696 | /**
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| 697 | * @brief Enable ADC continuous conversion mode.
|
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| 698 | * @param _CONTINUOUS_MODE_: Continuous mode.
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| 699 | * @retval None
|
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| 700 | */
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| 701 | #define ADC_CR2_CONTINUOUS(_CONTINUOUS_MODE_) ((_CONTINUOUS_MODE_) << 1)
|
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| 702 |
|
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| 703 | /**
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| 704 | * @brief Configures the number of discontinuous conversions for the regular group channels.
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| 705 | * @param _NBR_DISCONTINUOUSCONV_: Number of discontinuous conversions.
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| 706 | * @retval None
|
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| 707 | */
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| 708 | #define ADC_CR1_DISCONTINUOUS(_NBR_DISCONTINUOUSCONV_) (((_NBR_DISCONTINUOUSCONV_) - 1) << POSITION_VAL(ADC_CR1_DISCNUM))
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| 709 |
|
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| 710 | /**
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| 711 | * @brief Enable ADC scan mode.
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| 712 | * @param _SCANCONV_MODE_: Scan conversion mode.
|
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| 713 | * @retval None
|
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| 714 | */
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| 715 | #define ADC_CR1_SCANCONV(_SCANCONV_MODE_) ((_SCANCONV_MODE_) << 8)
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| 716 |
|
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| 717 | /**
|
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| 718 | * @brief Enable the ADC end of conversion selection.
|
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| 719 | * @param _EOCSelection_MODE_: End of conversion selection mode.
|
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| 720 | * @retval None
|
---|
| 721 | */
|
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| 722 | #define ADC_CR2_EOCSelection(_EOCSelection_MODE_) ((_EOCSelection_MODE_) << 10)
|
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| 723 |
|
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| 724 | /**
|
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| 725 | * @brief Enable the ADC DMA continuous request.
|
---|
| 726 | * @param _DMAContReq_MODE_: DMA continuous request mode.
|
---|
| 727 | * @retval None
|
---|
| 728 | */
|
---|
| 729 | #define ADC_CR2_DMAContReq(_DMAContReq_MODE_) ((_DMAContReq_MODE_) << 9)
|
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| 730 |
|
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| 731 | /**
|
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| 732 | * @brief Return resolution bits in CR1 register.
|
---|
| 733 | * @param __HANDLE__: ADC handle
|
---|
| 734 | * @retval None
|
---|
| 735 | */
|
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| 736 | #define ADC_GET_RESOLUTION(__HANDLE__) (((__HANDLE__)->Instance->CR1) & ADC_CR1_RES)
|
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| 737 |
|
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| 738 | /**
|
---|
| 739 | * @}
|
---|
| 740 | */
|
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| 741 |
|
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| 742 | /* Private functions ---------------------------------------------------------*/
|
---|
| 743 | /** @defgroup ADC_Private_Functions ADC Private Functions
|
---|
| 744 | * @{
|
---|
| 745 | */
|
---|
| 746 |
|
---|
| 747 | /**
|
---|
| 748 | * @}
|
---|
| 749 | */
|
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| 750 |
|
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| 751 | /**
|
---|
| 752 | * @}
|
---|
| 753 | */
|
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| 754 |
|
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| 755 | /**
|
---|
| 756 | * @}
|
---|
| 757 | */
|
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| 758 |
|
---|
| 759 | #ifdef __cplusplus
|
---|
| 760 | }
|
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| 761 | #endif
|
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| 762 |
|
---|
| 763 | #endif /*__STM32F4xx_ADC_H */
|
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| 764 |
|
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| 765 |
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| 766 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
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