1 | /*
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2 | * TOPPERS Software
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3 | * Toyohashi Open Platform for Embedded Real-Time Systems
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4 | *
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5 | * Copyright (C) 2006-2015 by Embedded and Real-Time Systems Laboratory
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6 | * Graduate School of Information Science, Nagoya Univ., JAPAN
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7 | *
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8 | * ä¸è¨èä½æ¨©è
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9 | ã¯ï¼ä»¥ä¸ã®(1)ã(4)ã®æ¡ä»¶ãæºããå ´åã«éãï¼æ¬ã½ããã¦ã§
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10 | * ã¢ï¼æ¬ã½ããã¦ã§ã¢ãæ¹å¤ãããã®ãå«ãï¼ä»¥ä¸åãï¼ã使ç¨ã»è¤è£½ã»æ¹
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11 | * å¤ã»åé
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12 | å¸ï¼ä»¥ä¸ï¼å©ç¨ã¨å¼ã¶ï¼ãããã¨ãç¡åã§è¨±è«¾ããï¼
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13 | * (1) æ¬ã½ããã¦ã§ã¢ãã½ã¼ã¹ã³ã¼ãã®å½¢ã§å©ç¨ããå ´åã«ã¯ï¼ä¸è¨ã®èä½
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14 | * 権表示ï¼ãã®å©ç¨æ¡ä»¶ããã³ä¸è¨ã®ç¡ä¿è¨¼è¦å®ãï¼ãã®ã¾ã¾ã®å½¢ã§ã½ã¼
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15 | * ã¹ã³ã¼ãä¸ã«å«ã¾ãã¦ãããã¨ï¼
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16 | * (2) æ¬ã½ããã¦ã§ã¢ãï¼ã©ã¤ãã©ãªå½¢å¼ãªã©ï¼ä»ã®ã½ããã¦ã§ã¢éçºã«ä½¿
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17 | * ç¨ã§ããå½¢ã§åé
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18 | å¸ããå ´åã«ã¯ï¼åé
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19 | å¸ã«ä¼´ãããã¥ã¡ã³ãï¼å©ç¨
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20 | * è
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21 | ããã¥ã¢ã«ãªã©ï¼ã«ï¼ä¸è¨ã®èä½æ¨©è¡¨ç¤ºï¼ãã®å©ç¨æ¡ä»¶ããã³ä¸è¨
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22 | * ã®ç¡ä¿è¨¼è¦å®ãæ²è¼ãããã¨ï¼
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23 | * (3) æ¬ã½ããã¦ã§ã¢ãï¼æ©å¨ã«çµã¿è¾¼ããªã©ï¼ä»ã®ã½ããã¦ã§ã¢éçºã«ä½¿
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24 | * ç¨ã§ããªãå½¢ã§åé
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25 | å¸ããå ´åã«ã¯ï¼æ¬¡ã®ããããã®æ¡ä»¶ãæºããã
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26 | * ã¨ï¼
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27 | * (a) åé
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28 | å¸ã«ä¼´ãããã¥ã¡ã³ãï¼å©ç¨è
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29 | ããã¥ã¢ã«ãªã©ï¼ã«ï¼ä¸è¨ã®è
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30 | * ä½æ¨©è¡¨ç¤ºï¼ãã®å©ç¨æ¡ä»¶ããã³ä¸è¨ã®ç¡ä¿è¨¼è¦å®ãæ²è¼ãããã¨ï¼
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31 | * (b) åé
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32 | å¸ã®å½¢æ
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33 | ãï¼å¥ã«å®ããæ¹æ³ã«ãã£ã¦ï¼TOPPERSããã¸ã§ã¯ãã«
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34 | * å ±åãããã¨ï¼
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35 | * (4) æ¬ã½ããã¦ã§ã¢ã®å©ç¨ã«ããç´æ¥çã¾ãã¯éæ¥çã«çãããããªãæ
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36 | * 害ãããï¼ä¸è¨èä½æ¨©è
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37 | ããã³TOPPERSããã¸ã§ã¯ããå
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38 | 責ãããã¨ï¼
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39 | * ã¾ãï¼æ¬ã½ããã¦ã§ã¢ã®ã¦ã¼ã¶ã¾ãã¯ã¨ã³ãã¦ã¼ã¶ããã®ãããªãç
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40 | * ç±ã«åºã¥ãè«æ±ãããï¼ä¸è¨èä½æ¨©è
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41 | ããã³TOPPERSããã¸ã§ã¯ãã
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42 | * å
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43 | 責ãããã¨ï¼
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44 | *
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45 | * æ¬ã½ããã¦ã§ã¢ã¯ï¼ç¡ä¿è¨¼ã§æä¾ããã¦ãããã®ã§ããï¼ä¸è¨èä½æ¨©è
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46 | ã
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47 | * ãã³TOPPERSããã¸ã§ã¯ãã¯ï¼æ¬ã½ããã¦ã§ã¢ã«é¢ãã¦ï¼ç¹å®ã®ä½¿ç¨ç®ç
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48 | * ã«å¯¾ããé©åæ§ãå«ãã¦ï¼ãããªãä¿è¨¼ãè¡ããªãï¼ã¾ãï¼æ¬ã½ããã¦ã§
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49 | * ã¢ã®å©ç¨ã«ããç´æ¥çã¾ãã¯éæ¥çã«çãããããªãæ害ã«é¢ãã¦ãï¼ã
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50 | * ã®è²¬ä»»ãè² ããªãï¼
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51 | *
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52 | * $Id: mpcore.h 357 2015-07-25 12:05:26Z ertl-hiro $
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53 | */
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54 |
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55 | /*
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56 | * MPCoreãµãã¼ãã¢ã¸ã¥ã¼ã«
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57 | */
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58 |
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59 | #ifndef TOPPERS_MPCORE_H
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60 | #define TOPPERS_MPCORE_H
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61 |
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62 | #include <sil.h>
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63 | #include "arm.h"
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64 |
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65 | /*
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66 | * CP15ã®è£å©å¶å¾¡ã¬ã¸ã¹ã¿ï¼ACTLRï¼ã®è¨å®å¤
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67 | */
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68 | #if __TARGET_ARCH_ARM == 6
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69 | #define CP15_ACTLR_SMP UINT_C(0x00000020)
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70 | #else /* __TARGET_ARCH_ARM == 6 */
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71 | #define CP15_ACTLR_SMP UINT_C(0x00000040)
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72 | #endif /* __TARGET_ARCH_ARM == 6 */
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73 |
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74 | /*
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75 | * SCUï¼ã¹ãã¼ãå¶å¾¡ã¦ãããï¼é¢é£ã®å®ç¾©
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76 | */
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77 |
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78 | /*
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79 | * SCUã¬ã¸ã¹ã¿ã®çªå°ã®å®ç¾©
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80 | */
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81 | #define MPCORE_SCU_BASE (MPCORE_PMR_BASE + 0x0000U)
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82 | #define MPCORE_SCU_CTRL ((uint32_t *)(MPCORE_SCU_BASE + 0x00U))
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83 | #define MPCORE_SCU_CONFIG ((uint32_t *)(MPCORE_SCU_BASE + 0x04U))
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84 | #define MPCORE_SCU_CPUSTAT ((uint32_t *)(MPCORE_SCU_BASE + 0x08U))
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85 | #define MPCORE_SCU_INVALL ((uint32_t *)(MPCORE_SCU_BASE + 0x0cU))
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86 |
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87 | /*
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88 | * SCUå¶å¾¡ã¬ã¸ã¹ã¿ï¼SCU_CTRLï¼ã®è¨å®å¤
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89 | */
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90 | #define MPCORE_SCU_CTRL_ENABLE UINT_C(0x00000001)
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91 |
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92 | /*
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93 | * SCUã¤ã³ããªãã¼ããªã¼ã«ã¬ã¸ã¹ã¿ï¼SCU_INVALLï¼ã®è¨å®å¤
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94 | */
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95 | #define MPCORE_SCU_INVALL_ALLWAYS UINT_C(0x0000ffff)
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96 |
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97 | /*
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98 | * GICé¢é£ã®å®ç¾©
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99 | */
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100 |
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101 | /*
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102 | * GICã¬ã¸ã¹ã¿ã®ãã¼ã¹ã¢ãã¬ã¹ã®å®ç¾©
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103 | */
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104 | #define GICC_BASE (MPCORE_PMR_BASE + UINT_C(0x0100))
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105 | #define GICD_BASE (MPCORE_PMR_BASE + UINT_C(0x1000))
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106 |
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107 | /*
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108 | * ãã©ã¤ãã¼ãã¿ã¤ãã¨ã¦ã©ããããã°é¢é£ã®å®ç¾©
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109 | */
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110 |
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111 | /*
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112 | * ãã©ã¤ãã¼ãã¿ã¤ãã¨ã¦ã©ããããã°ã®å²è¾¼ã¿çªå·
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113 | */
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114 | #define MPCORE_IRQNO_TMR 29U /* ãã©ã¤ãã¼ãã¿ã¤ãã®å²è¾¼ã¿çªå· */
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115 | #define MPCORE_IRQNO_WDG 30U /* ã¦ã©ããããã°ã®å²è¾¼ã¿çªå· */
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116 |
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117 | /*
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118 | * ãã©ã¤ãã¼ãã¿ã¤ãã¨ã¦ã©ããããã°ã¬ã¸ã¹ã¿ã®çªå°ã®å®ç¾©
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119 | */
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120 | #define MPCORE_TMR_BASE (MPCORE_PMR_BASE + 0x0600U)
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121 | #define MPCORE_TMR_LR ((uint32_t *)(MPCORE_TMR_BASE + 0x00U))
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122 | #define MPCORE_TMR_CNT ((uint32_t *)(MPCORE_TMR_BASE + 0x04U))
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123 | #define MPCORE_TMR_CTRL ((uint32_t *)(MPCORE_TMR_BASE + 0x08U))
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124 | #define MPCORE_TMR_ISR ((uint32_t *)(MPCORE_TMR_BASE + 0x0cU))
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125 | #define MPCORE_WDG_LR ((uint32_t *)(MPCORE_TMR_BASE + 0x20U))
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126 | #define MPCORE_WDG_CNT ((uint32_t *)(MPCORE_TMR_BASE + 0x24U))
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127 | #define MPCORE_WDG_CTRL ((uint32_t *)(MPCORE_TMR_BASE + 0x28U))
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128 | #define MPCORE_WDG_ISR ((uint32_t *)(MPCORE_TMR_BASE + 0x2cU))
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129 | #define MPCORE_WDG_RST ((uint32_t *)(MPCORE_TMR_BASE + 0x30U))
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130 | #define MPCORE_WDG_DIS ((uint32_t *)(MPCORE_TMR_BASE + 0x34U))
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131 |
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132 | /*
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133 | * ãã©ã¤ãã¼ãã¿ã¤ãå¶å¾¡ã¬ã¸ã¹ã¿ï¼MPCORE_TMR_CTRLï¼ã®è¨å®å¤
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134 | */
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135 | #define MPCORE_TMR_CTRL_DISABLE 0x00U
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136 | #define MPCORE_TMR_CTRL_ENABLE 0x01U
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137 | #define MPCORE_TMR_CTRL_AUTORELOAD 0x02U
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138 | #define MPCORE_TMR_CTRL_ENAINT 0x04U
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139 | #define MPCORE_TMR_CTRL_PS_SHIFT 8
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140 |
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141 | /*
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142 | * ãã©ã¤ãã¼ãã¿ã¤ãå²è¾¼ã¿ã¹ãã¼ã¿ã¹ã¬ã¸ã¹ã¿ï¼MPCORE_TMR_ISRï¼ã®è¨å®å¤
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143 | */
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144 | #define MPCORE_TMR_ISR_EVENTFLAG 0x01U
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145 |
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146 | /*
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147 | * ã¦ã©ããããã°å¶å¾¡ã¬ã¸ã¹ã¿ï¼MPCORE_WDG_CTRLï¼ã®åç
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148 | §å¤
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149 | */
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150 | #define MPCORE_WDG_CTRL_DISABLE 0x00U
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151 | #define MPCORE_WDG_CTRL_ENABLE 0x01U
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152 | #define MPCORE_WDG_CTRL_AUTORELOAD 0x02U
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153 | #define MPCORE_WDG_CTRL_ENAINT 0x04U
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154 | #define MPCORE_WDG_CTRL_WDGMODE 0x08U
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155 | #define MPCORE_WDG_CTRL_PS_SHIFT 8
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156 |
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157 | /*
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158 | * ã¦ã©ããããã°å²è¾¼ã¿ã¹ãã¼ã¿ã¹ã¬ã¸ã¹ã¿ï¼MPCORE_WDG_ISRï¼ã®åç
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159 | §å¤
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160 | */
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161 | #define MPCORE_WDG_ISR_EVENTFLAG 0x01U
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162 |
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163 | /*
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164 | * ã°ãã¼ãã«ã¿ã¤ãé¢é£ã®å®ç¾©
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165 | */
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166 | #if __TARGET_ARCH_ARM == 7
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167 |
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168 | /*
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169 | * ã°ãã¼ãã«ã¿ã¤ãã¬ã¸ã¹ã¿ã®çªå°ã®å®ç¾©
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170 | */
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171 | #define MPCORE_GTC_BASE (MPCORE_PMR_BASE + 0x0200U)
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172 | #define MPCORE_GTC_COUNT_L ((uint32_t *)(MPCORE_GTC_BASE + 0x00U))
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173 | #define MPCORE_GTC_COUNT_U ((uint32_t *)(MPCORE_GTC_BASE + 0x04U))
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174 | #define MPCORE_GTC_CTRL ((uint32_t *)(MPCORE_GTC_BASE + 0x08U))
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175 | #define MPCORE_GTC_ISR ((uint32_t *)(MPCORE_GTC_BASE + 0x0cU))
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176 | #define MPCORE_GTC_CVR_L ((uint32_t *)(MPCORE_PMR_BASE + 0x10U))
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177 | #define MPCORE_GTC_CVR_U ((uint32_t *)(MPCORE_PMR_BASE + 0x14U))
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178 |
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179 | /*
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180 | * ã°ãã¼ãã«ã¿ã¤ãå¶å¾¡ã¬ã¸ã¹ã¿ï¼MPCORE_GTC_CTRLï¼ã®è¨å®å¤
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181 | */
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182 | #define MPCORE_GTC_CTRL_ENABLE 0x01U
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183 |
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184 | #endif /* __TARGET_ARCH_ARM == 7 */
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185 |
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186 | #ifndef TOPPERS_MACRO_ONLY
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187 |
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188 | /*
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189 | * SMPã¢ã¼ãã«è¨å®
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190 | */
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191 | Inline void
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192 | mpcore_enable_smp(void)
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193 | {
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194 | uint32_t reg;
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195 |
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196 | CP15_READ_ACTLR(reg);
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197 | reg |= CP15_ACTLR_SMP;
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198 | CP15_WRITE_ACTLR(reg);
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199 | }
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200 |
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201 | /*
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202 | * SCUï¼ã¹ãã¼ãå¶å¾¡ã¦ãããï¼ã®æä½
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203 | */
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204 |
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205 | /*
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206 | * SCUã®ã¤ãã¼ãã«
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207 | */
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208 | Inline void
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209 | mpcore_enable_scu(void)
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210 | {
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211 | uint32_t reg;
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212 |
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213 | /*
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214 | * SCUã®ãã¹ã¦ã®ã¿ã°ãç¡å¹åããï¼
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215 | */
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216 | sil_wrw_mem(MPCORE_SCU_INVALL, MPCORE_SCU_INVALL_ALLWAYS);
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217 |
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218 | /*
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219 | * SCUãæå¹ã«ããï¼
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220 | */
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221 | reg = sil_rew_mem(MPCORE_SCU_CTRL);
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222 | reg |= MPCORE_SCU_CTRL_ENABLE;
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223 | sil_wrw_mem(MPCORE_SCU_CTRL, reg);
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224 | data_sync_barrier();
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225 | }
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226 |
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227 | #endif /* TOPPERS_MACRO_ONLY */
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228 | #endif /* TOPPERS_MPCORE_H */
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