1 |
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2 | TOPPERSããã¸ã§ã¯ã è¨è¨ã¡ã¢
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3 | MPCoreããã³ãããç¨ãããããï¼ãã¼ãã«é¢ããã¡ã¢
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4 |
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5 | ä½æè
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6 | : é«ç°åºç« ï¼åå¤å±å¤§å¦ï¼
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7 | æçµæ´æ°: 2016å¹´1æ16æ¥
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8 |
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9 | âã¡ã¢ã®ä½ç½®ã¥ã
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10 |
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11 | ãã®ã¡ã¢ã¯ï¼MPCoreã¨ï¼ãããç¨ãã以ä¸ã®ãããï¼ãã¼ãã«é¢ãã¦ï¼
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12 | TOPPERSã«ã¼ãã«ããã¼ãã£ã³ã°ããã«ããã£ã¦å¿
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13 | è¦ã¨ãªãäºé
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14 | ãã¾ã¨ãããã®
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15 | ã§ããï¼
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16 |
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17 | ã»ARM11 MPCore
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18 | ã»Core Tile for ARM11 MPCoreï¼CT11MPCoreï¼
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19 | ã»RealView Platform Baseboard for ARM11 MPCore
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20 |
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21 | âç®æ¬¡
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22 |
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23 | ã»åèæç®
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24 | ã»MPCoreã¨ã¯ï¼
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25 | ã»SCUï¼Snoop Control Unitï¼
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26 | ã»ARM CT11MPcore with RealView Emulation Baseboard
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27 | - ç¨èªã®æ´ç
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28 | - ARM11 MPCoreãã¹ããããã®å²è¾¼ã¿æ©è½
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29 | - CoreTile for ARM11 MPcoreã®å²è¾¼ã¿æ©è½
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30 | - ããã¤ã¹ã¬ã¸ã¹ã¿ã®ã¢ãã¬ã¹
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31 | ã»ARM11 MPCoreå
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32 | èµã¿ã¤ã
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33 | - ã¿ã¤ã
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34 | - ã¦ã©ããããã°
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35 |
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36 | âåèæç®
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37 |
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38 | [1] ARM11 MPCore Processor Technical Reference Manual, 2008
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39 | Revision: r2p0
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40 | DDI0360F_arm11_mpcore_r2p0_trm.pdf
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41 |
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42 | [2] Cortex-A9 MPCore Technical Reference Manual, 2012
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43 | Revision: r4p1
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44 | DDI0407I_cortex_a9_mpcore_r4p1_trm
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45 |
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46 | [3] Core Tile for ARM11 MPCore User Guide
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47 | HBI-0146
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48 | DUI0318F_core_tile_for_arm11_mpcore_ug.pdf
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49 |
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50 | [4] Using a CT11MPCore with the RealView Emulation Baseboard, 2008
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51 | ARM DAI 0152E
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52 | DAI0152E_ct11mpcore_on_emulation_baseboard.pdf
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53 |
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54 | [5] RealView Platform Baseboard for ARM11 MPCore User Guide, 2011
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55 | HBI-0159, HBI-0175, HBI-0176
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56 | DUI0351E_realview_platform_baseboard_for_arm11_mpcore_ug.pdf
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57 |
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58 | âMPCoreã¨ã¯ï¼
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59 |
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60 | MPCoreã¨ã¯ï¼ARMã³ã¢ã1ã4åã¨ï¼SCUï¼Snoop Control Unitï¼ãªã©ï¼ãã«ãã³
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61 | ã¢ã·ã¹ãã ã«å¿
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62 | è¦ãªå¨è¾ºåè·¯ãå«ãããã»ããµã¢ã¼ããã¯ãã£ã®å称ã¨æãã
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63 | ãï¼
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64 |
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65 | åèæç®[1]ã«ããã¨ï¼ARM11 MPCoreã¨ã¯ï¼1ã4åã®MP11 CPUï¼ã³ã¢ï¼ãè¼ãï¼
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66 | SCUï¼DICï¼Distributed Interrupt Controllerï¼ï¼ã³ã¢æ¯ã®ãã©ã¤ãã¼ãã¿ã¤
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67 | ãã¨ãã©ã¤ãã¼ãã¦ã©ããããã°ï¼AXIã¤ã³ã¿ãã§ã¼ã¹ãªã©ãå«ãããã»ããµã®
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68 | å称ã§ããï¼MP11 CPUã¨ã¯ï¼ARM11ãæ¡å¼µããã³ã¢ã®ãã¨ã¨æãããï¼
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69 |
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70 | åèæç®[2]ã«ããã¨ï¼Cortex-A9 MPCoreã¨ã¯ï¼1ã4åã®Cortex-A9ããã»ããµ
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71 | ï¼ã³ã¢ï¼ãè¼ãï¼SCUï¼GICï¼Generic Interrupt Controllerï¼ï¼ãã©ã¤ãã¼ã
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72 | ããªãã§ã©ã«ï¼ã°ãã¼ãã«ã¿ã¤ãï¼ã³ã¢æ¯ã®ãã©ã¤ãã¼ãã¿ã¤ãã¨ã¦ã©ãããã
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73 | ã°ï¼ï¼AXIã¤ã³ã¿ãã§ã¼ã¹ï¼ãªãã·ã§ã³ï¼ãªã©ãå«ãããã»ããµã®å称ã§ããï¼
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74 |
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75 | 以ä¸ããï¼MPCoreãããä¾åé¨ã«ã¯ï¼SCUï¼GICï¼ã¾ãã¯DICï¼ï¼ãã©ã¤ãã¼ãã
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76 | ãªãã§ã©ã«ãæ±ãã³ã¼ããå«ããã®ã妥å½ã¨èããããï¼ãã ãï¼GICï¼ããã³
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77 | DICï¼ã«ã¤ãã¦ã¯ï¼å¥ã®ARMããã»ããµã«ãå
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78 | ±éã§ä½¿ãããããï¼ARMã³ã¢ä¾åé¨
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79 | ã«å«ããï¼
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80 |
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81 | âSCUï¼Snoop Control Unitï¼
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82 |
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83 | SCUã¯ï¼åã³ã¢ãæã¤L1ãã£ãã·ã¥ã®ã³ãã¼ã¬ã³ã¹ãä¿ã¤ããã®åè·¯ã§ããï¼
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84 | ARM11 MPCoreã§ã¯ï¼SCUãããã©ã¼ãã³ã¹ã¢ãã¿ã®æ©è½ãæã£ã¦ãããï¼
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85 | Cortex-Aã·ãªã¼ãºã§ã¯ï¼ããã©ã¼ãã³ã¹ã¢ãã¿ã¯ç¬ç«ããæ©è½ã¨ãã¦ç¨æãã
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86 | ã¦ããï¼SCUã¯ããã©ã¼ãã³ã¹ã¢ãã¿ã®æ©è½ãæããªãï¼
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87 |
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88 | 以ä¸ã§ã¯ï¼SCUã®å¶å¾¡ã¬ã¸ã¹ã¿ã«ã¤ãã¦ã¾ã¨ããï¼
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89 |
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90 | SCUå¶å¾¡ã¬ã¸ã¹ã¿ï¼MPCORE_SCU_CTRLï¼â¦ 32ããã
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91 | ï¼ARM11 MPCoreã¨Cortex-A9 MPCoreã§ï¼ãããé
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92 | ç½®ãç°ãªãï¼
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93 |
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94 | SCUã³ã³ãã£ã®ã¥ã¬ã¼ã·ã§ã³ã¬ã¸ã¹ã¿ï¼MPCORE_SCU_CONFIGï¼â¦ 32ããã
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95 |
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96 | SCU CPUãã¯ã¼ã¹ãã¼ã¿ã¹ã¬ã¸ã¹ã¿ï¼MPCORE_SCU_CPUSTATï¼â¦ 32ããã
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97 | ï¼ARM11 MPCoreã¨Cortex-A9 MPCoreã§ï¼ãããé
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98 | ç½®ãç°ãªãï¼
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99 |
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100 | SCUå
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101 | ¨ç¡å¹åã¬ã¸ã¹ã¿ï¼MPCORE_SCU_INVALLï¼â¦ 32ããã
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102 | - ãã®ã¬ã¸ã¹ã¿ã«æ¸ãè¾¼ããã¨ã§ï¼ã¿ã°ã¡ã¢ãªãç¡å¹åã§ããï¼
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103 |
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104 | âARM CT11MPcore with RealView Emulation Baseboard
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105 |
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106 | âç¨èªã®æ´ç
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107 |
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108 | ã»Emulation Baseboardï¼EBï¼
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109 | - ã³ã¢ãå«ã¾ãªããã¼ã¹ãã¼ã
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110 | - ã¡ã¢ãªãå種ã®ããªãã§ã©ã«ãæè¼ãã
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111 |
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112 | ã»Platform Baseboardï¼PBï¼
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113 | - ã³ã¢ãæè¼ãããã¼ã¹ãã¼ã
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114 | - ã¡ã¢ãªãå種ã®ããªãã§ã©ã«ãæè¼ãã
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115 |
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116 | ã»CoreTileï¼CTï¼
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117 | - Emulation Baseboardï¼EBï¼ã«è¼ããããã®ã³ã¢ãæè¼ããå°åãã¼ã
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118 |
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119 | ã»Core Tile for ARM11 MPCoreï¼CT11MPCoreï¼
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120 | - ARM11 MPCoreã®ãã¹ãããããæè¼ããCoreTile
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121 | + 4ããã»ããµæ§æã®ARM11 MPCore
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122 | + L220 ã¬ãã«2 ãã£ãã·ã¥ã³ã³ããã¼ã©
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123 |
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124 | ã»HDRXï¼HDRYï¼HDRZï¼ä½ã®ç¥ãä¸æï¼
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125 | - Baseboardã¨CoreTileãæ¥ç¶ãã3ã¤ã®ã³ãã¯ã¿ã®å称
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126 |
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127 | ã»DCCï¼Debug Communications Controllerï¼
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128 |
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129 | âARM11 MPCoreãã¹ããããã®å²è¾¼ã¿æ©è½ï¼[3] 4.3.2ç¯ï¼
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130 |
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131 | ã»æè¼ããã¦ããå²è¾¼ã¿ã³ã³ããã¼ã©
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132 | - DICï¼Distributed Interrupt Controllerï¼
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133 | - GICã®å身ã¨ãªãä»æ§ï¼GICv0ã«ç¸å½ï¼
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134 |
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135 | ã»ãããå¤ããã®å²è¾¼ã¿è¦æ±ã©ã¤ã³
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136 | - nIRQ[3:0] ⦠DICã®å²è¾¼ã¿ID31ã«
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137 | - nFIQ[3:0] ⦠åããã»ããµã®FIQã«ç´çµ
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138 | - INT[15:0] ⦠DICã®å²è¾¼ã¿ID32ã47ã«
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139 |
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140 | ã»CPSRä¸ã®Fããããç¡å¹ã«ãã¦ï¼FIQãNMIæ±ãã§ãã
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141 | - ãã¹ããããå²è¾¼ã¿å¶å¾¡ã¬ã¸ã¹ã¿ã§è¨å®
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142 | PERIPHBASEï¼0x3004U
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143 |
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144 | ã»DICã¯32æ¬ã®å²è¾¼ã¿è¦æ±ã©ã¤ã³ãæã¤
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145 | - ãã¼ãã¦ã§ã¢å²è¾¼ã¿ï¼GICã®SPIã«ç¸å½ï¼ã®æ¬æ°ã®ãã¨ã¨æããã
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146 |
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147 | ã»ãã¹ããããã®INT[31:16]ã¯ï¼ãããå
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148 | ã«éãã¦ä½¿ç¨
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149 | - INT[31:29]ï¼L220ããã®å²è¾¼ã¿ï¼3æ¬ï¼
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150 | - INT[17:28]ï¼åããã»ããµããã³SCUããã®å²è¾¼ã¿ï¼12æ¬ï¼PMUIRQ[0:11]
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151 | - INT[16]ï¼æªä½¿ç¨ï¼1æ¬ï¼
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152 |
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153 | âCoreTile for ARM11 MPcoreã®å²è¾¼ã¿æ©è½ï¼[3] 3.4.2ç¯ï¼
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154 |
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155 | ã»3ã¤ã®å²è¾¼ã¿ã¢ã¼ãããµãã¼ã
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156 | - Legacy mode
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157 | - Normal mode with DCC interrupt routing
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158 | - Normal mode without DCC interrupt routing ⦠ããã§ä½¿ã£ã¦ãã
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159 | - EBã·ã¹ãã FPGAã®SYS_PLD_CTL1ã¬ã¸ã¹ã¿ã®INTMODE[2:0]ã§è¨å®ãã
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160 |
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161 | ã»Normal mode without DCC
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162 | - Emulation Baseboardããã®16æ¬ã«å²è¾¼ã¿è¦æ±ã©ã¤ã³ãï¼ãã®ã¾ã¾
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163 | INT[15:0]ã«æ¥ç¶ï¼nIRQ[3:0]ã¨nFIQ[3:0]ã¯ä½¿ããªã
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164 | - å²è¾¼ã¿çªå·ã®ã¢ãµã¤ã³
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165 | INT[0]ï¼ACCI
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166 | INT[1]ï¼EB_TIMER0/1
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167 | INT[2]ï¼EB_TIMER2/3
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168 | INT[3]ï¼USB
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169 | INT[4]ï¼EB_UART0
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170 | INT[5]ï¼EB_UART1
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171 | â¦
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172 | INT[10]ï¼EB_GIC1_nIRQ
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173 | INT[11]ï¼EB_GIC2_nIRQ
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174 | INT[12]ï¼EB_GIC1_nFIQ
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175 | INT[13]ï¼EB_GIC2_nFIQ
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176 | â¦
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177 |
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178 | âããã¤ã¹ã¬ã¸ã¹ã¿ã®ã¢ãã¬ã¹
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179 |
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180 | ã»ããªãã§ã©ã«ãã¼ã¹ã¢ãã¬ã¹ï¼PERIPHBASEï¼ï¼[3] 3.10.1ç¯ï¼
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181 | - 以ä¸ã®ã¬ã¸ã¹ã¿ã®ã¢ãã¬ã¹ã決ãã
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182 | + ARM11 MPCoreã®ã¬ã¸ã¹ã¿
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183 | SCUã®å¶å¾¡ã¬ã¸ã¹ã¿
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184 | + L220ãã£ãã·ã¥ã³ã³ããã¼ã©ã®ã¬ã¸ã¹ã¿
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185 | + ARM11 MPCoreãã¹ããããã®ã¬ã¸ã¹ã¿
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186 | Test chip PLL control register
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187 | Test chip interrupt control register
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188 | Test chip cluster ID register
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189 | Test chip power status register
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190 | Test chip way map register
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191 | Test chip clock divider register
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192 | - CT11MPCoreã§ã¯ï¼CoreTileä¸ã®ã¸ã£ã³ãã¹ã¤ããã§è¨å®å¯è½
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193 | + ããã©ã«ãã¯ï¼0x1F000000
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194 | - QEMUã§ã¯ï¼0x10100000ã«è¨å®ããã¦ããï¼qemu-2.1.0/hw/arm/realview.cï¼
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195 |
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196 | ã»Emulation Baseboardä¸ã®ãªã½ã¼ã¹ã®ã¢ãã¬ã¹ï¼[4] 5.2ç¯ï¼[5] 4ç« ï¼
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197 | - ãã¼ã¹ã¢ãã¬ã¹ã¯ï¼0x10000000
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198 | - ã¬ã¸ã¹ã¿ãã¢ã³ããã¯ããæ¹æ³
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199 | + base+0x20ã«ï¼0xA05Fãæ¸ãè¾¼ã
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200 | - ã¡ã¢ãªããã
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201 | 0x10000000ã0x10000fff ã·ã¹ãã ã¬ã¸ã¹ã¿
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202 | 0x10001000ã0x10001fff ã·ã¹ãã ã³ã³ããã¼ã©ï¼SP810ï¼
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203 | â¦ä¸ç¥â¦
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204 | 0x10009000ã0x10009fff UART0 ⦠ARM UART PL011 r1p3
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205 | 0x1000a000ã0x1000afff UART1 ⦠ARM UART PL011 r1p3
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206 | 0x1000b000ã0x1000bfff UART2 ⦠ARM UART PL011 r1p3
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207 | 0x1000c000ã0x1000cfff UART3 ⦠ARM UART PL011 r1p3
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208 | â¦ä¸ç¥â¦
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209 | 0x10010000ã0x10010fff Watchdog ⦠ARM WDOG SP805 r2p0
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210 | 0x10011000ã0x10011fff Timer 0&1 ⦠ARM Dual-Timer SP804 r1p2
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211 | 0x10012000ã0x10012fff Timer 2&3 ⦠ARM Dual-Timer SP804 r1p2
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212 | â¦ä¸ç¥â¦
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213 |
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214 | âARM11 MPCoreå
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215 | èµã¿ã¤ãï¼[1] 9.2ç¯ï¼
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216 |
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217 | ARM11 MPCoreã¯ï¼ã³ã¢æ¯ã«ï¼ãã©ã¤ãã¼ãã¿ã¤ãã¨ãã©ã¤ãã¼ãã¦ã©ãããã
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218 | ã°ãæã¤ï¼ã¦ã©ããããã°ã¯ï¼ã¿ã¤ãã¨ãã¦ä½¿ç¨ãããã¨ãã§ããï¼
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219 |
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220 | âã¿ã¤ã
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221 |
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222 | ã¿ã¤ããã¼ãã¬ã¸ã¹ã¿ï¼MPCORE_TMR_LRï¼â¦ 32ããã
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223 | - ã«ã¦ã³ãã¬ã¸ã¹ã¿ã0ã«ãªã£ãæã«ãªãã¼ãããå¤ãä¿æããã¬ã¸ã¹ã¿ï¼
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224 | - ãã®ã¬ã¸ã¹ã¿ã«æ¸ãè¾¼ãã¨ï¼ã«ã¦ã³ãã¬ã¸ã¹ã¿ã«ãæ¸ãè¾¼ã¾ããï¼
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225 |
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226 | ã¿ã¤ãã«ã¦ã³ãã¬ã¸ã¹ã¿ï¼MPCORE_TMR_CNTï¼â¦ 32ããã
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227 | - ãã¦ã³ã«ã¦ã³ã¿ï¼
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228 | - 0ã«ãªã£ããï¼å²è¾¼ã¿ãè¦æ±ããï¼
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229 | - ãªã¼ããªãã¼ãã¢ã¼ãã§ã¯ï¼0ã«ãªã£ããï¼ãã¼ãã¬ã¸ã¹ã¿ã®å¤ã«æ»ãï¼
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230 | - ãã¼ãã¬ã¸ã¹ã¿ãã«ã¦ã³ã¿ã¬ã¸ã¹ã¿ã«æ¸ãè¾¼ãã¨ï¼æ°ããå¤ããã«ã¦ã³ãï¼
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231 |
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232 | ã¿ã¤ãå¶å¾¡ã¬ã¸ã¹ã¿ï¼MPCORE_TMR_CTRLï¼â¦ 32ããã
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233 | [31:16] äºç´ï¼SBZ/RAZï¼
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234 | [15:8] ããªã¹ã±ã¼ã©
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235 | [7:3] äºç´ï¼SBZ/RAZï¼
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236 | [2] å²è¾¼ã¿ã¤ãã¼ãã«
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237 | [1] ãªã¼ããªãã¼ã
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238 | [0] ã¿ã¤ãã¤ãã¼ãã«
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239 |
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240 | ã¿ã¤ãå²è¾¼ã¿ç¶æ
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241 | ã¬ã¸ã¹ã¿ï¼MPCORE_TMR_ISRï¼â¦ 32ããã
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242 | [31:1] äºç´
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243 | [0] ã¤ãã³ããã©ã°
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244 | - ã«ã¦ã³ã¿ã¬ã¸ã¹ã¿ã0ã«ãªã£ãæã«ã»ãããããï¼
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245 | - 1ãæ¸ãè¾¼ãã¨ã¯ãªã¢ãããï¼
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246 |
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247 | âã¦ã©ããããã°
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248 |
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249 | ã¦ã©ããããã°ãã¼ãã¬ã¸ã¹ã¿ï¼MPCORE_WDG_LRï¼â¦ 32ããã
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250 | - ã«ã¦ã³ãã¬ã¸ã¹ã¿ã0ã«ãªã£ãæã«ãªãã¼ãããå¤ãä¿æããã¬ã¸ã¹ã¿ï¼
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251 | - ãã®ã¬ã¸ã¹ã¿ã«æ¸ãè¾¼ãã¨ï¼ã«ã¦ã³ãã¬ã¸ã¹ã¿ã«ãæ¸ãè¾¼ã¾ããï¼
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252 |
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253 | ã¦ã©ããããã°ã«ã¦ã³ãã¬ã¸ã¹ã¿ï¼MPCORE_WDG_CNTï¼â¦ 32ããã
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254 | - ãã¦ã³ã«ã¦ã³ã¿ï¼
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255 | ã+ ã¿ã¤ãã¢ã¼ã
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256 | - 0ã«ãªã£ããï¼å²è¾¼ã¿ãè¦æ±ããï¼
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257 | - ãªã¼ããªãã¼ãã¢ã¼ãã§ã¯ï¼0ã«ãªã£ããï¼ãã¼ãã¬ã¸ã¹ã¿ã®å¤ã«æ»ãï¼
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258 | - ãã¼ãã¬ã¸ã¹ã¿ãã«ã¦ã³ã¿ã¬ã¸ã¹ã¿ã«æ¸ãè¾¼ãã¨ï¼æ°ããå¤ããã«ã¦ã³ãï¼
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259 | ã+ ã¦ã©ããããã°ã¢ã¼ã
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260 | - 0ã«ãªã£ããï¼ãªã»ãããè¦æ±ããï¼
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261 | - ãã®ã¬ã¸ã¹ã¿ã¸ã¯æ¸ãè¾¼ããªãï¼
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262 |
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263 | ã¦ã©ããããã°å¶å¾¡ã¬ã¸ã¹ã¿ï¼MPCORE_WDG_CTRLï¼â¦ 32ããã
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264 | [31:16] äºç´ï¼SBZ/RAZï¼
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265 | [15:8] ããªã¹ã±ã¼ã©
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266 | [7:4] äºç´ï¼SBZ/RAZï¼
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267 | [3] ã¦ã©ããããã°ã¢ã¼ãï¼ããã«0ãæ¸ãã¦ãå¤æ´ã§ããªãï¼
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268 | [2] å²è¾¼ã¿ã¤ãã¼ãã«
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269 | [1] ãªã¼ããªãã¼ã
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270 | [0] ã¦ã©ããããã°ã¤ãã¼ãã«
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271 |
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272 | ã¦ã©ããããã°å²è¾¼ã¿ç¶æ
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273 | ã¬ã¸ã¹ã¿ï¼MPCORE_WDG_ISRï¼â¦ 32ããã
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274 | [31:1] äºç´
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275 | [0] ã¤ãã³ããã©ã°
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276 | - ã¿ã¤ãã¢ã¼ãã§ï¼ã«ã¦ã³ã¿ã¬ã¸ã¹ã¿ã0ã«ãªã£ãæã«ã»ããï¼
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277 | - 1ãæ¸ãè¾¼ãã¨ã¯ãªã¢ï¼
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