1 | #if !__ARMEB__ && !__thumb__
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2 |
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3 | /*
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4 | * Copyright (C) 2008 The Android Open Source Project
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5 | * All rights reserved.
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6 | *
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7 | * Redistribution and use in source and binary forms, with or without
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8 | * modification, are permitted provided that the following conditions
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9 | * are met:
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10 | * * Redistributions of source code must retain the above copyright
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11 | * notice, this list of conditions and the following disclaimer.
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12 | * * Redistributions in binary form must reproduce the above copyright
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13 | * notice, this list of conditions and the following disclaimer in
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14 | * the documentation and/or other materials provided with the
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15 | * distribution.
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16 | *
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17 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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18 | * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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19 | * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
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20 | * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
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21 | * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
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22 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
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23 | * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
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24 | * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
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25 | * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
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26 | * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
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27 | * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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28 | * SUCH DAMAGE.
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29 | */
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30 |
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31 |
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32 | /*
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33 | * Optimized memcpy() for ARM.
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34 | *
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35 | * note that memcpy() always returns the destination pointer,
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36 | * so we have to preserve R0.
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37 | */
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38 |
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39 | /*
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40 | * This file has been modified from the original for use in musl libc.
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41 | * The main changes are: addition of .type memcpy,%function to make the
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42 | * code safely callable from thumb mode, adjusting the return
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43 | * instructions to be compatible with pre-thumb ARM cpus, and removal
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44 | * of prefetch code that is not compatible with older cpus.
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45 | */
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46 |
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47 | .syntax unified
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48 |
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49 | .global memcpy
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50 | .type memcpy,%function
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51 | memcpy:
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52 | /* The stack must always be 64-bits aligned to be compliant with the
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53 | * ARM ABI. Since we have to save R0, we might as well save R4
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54 | * which we can use for better pipelining of the reads below
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55 | */
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56 | .fnstart
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57 | .save {r0, r4, lr}
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58 | stmfd sp!, {r0, r4, lr}
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59 | /* Making room for r5-r11 which will be spilled later */
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60 | .pad #28
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61 | sub sp, sp, #28
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62 |
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63 | /* it simplifies things to take care of len<4 early */
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64 | cmp r2, #4
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65 | blo copy_last_3_and_return
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66 |
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67 | /* compute the offset to align the source
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68 | * offset = (4-(src&3))&3 = -src & 3
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69 | */
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70 | rsb r3, r1, #0
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71 | ands r3, r3, #3
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72 | beq src_aligned
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73 |
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74 | /* align source to 32 bits. We need to insert 2 instructions between
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75 | * a ldr[b|h] and str[b|h] because byte and half-word instructions
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76 | * stall 2 cycles.
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77 | */
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78 | movs r12, r3, lsl #31
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79 | sub r2, r2, r3 /* we know that r3 <= r2 because r2 >= 4 */
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80 | ldrbmi r3, [r1], #1
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81 | ldrbcs r4, [r1], #1
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82 | ldrbcs r12,[r1], #1
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83 | strbmi r3, [r0], #1
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84 | strbcs r4, [r0], #1
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85 | strbcs r12,[r0], #1
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86 |
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87 | src_aligned:
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88 |
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89 | /* see if src and dst are aligned together (congruent) */
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90 | eor r12, r0, r1
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91 | tst r12, #3
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92 | bne non_congruent
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93 |
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94 | /* Use post-incriment mode for stm to spill r5-r11 to reserved stack
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95 | * frame. Don't update sp.
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96 | */
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97 | stmea sp, {r5-r11}
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98 |
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99 | /* align the destination to a cache-line */
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100 | rsb r3, r0, #0
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101 | ands r3, r3, #0x1C
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102 | beq congruent_aligned32
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103 | cmp r3, r2
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104 | andhi r3, r2, #0x1C
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105 |
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106 | /* conditionnaly copies 0 to 7 words (length in r3) */
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107 | movs r12, r3, lsl #28
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108 | ldmcs r1!, {r4, r5, r6, r7} /* 16 bytes */
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109 | ldmmi r1!, {r8, r9} /* 8 bytes */
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110 | stmcs r0!, {r4, r5, r6, r7}
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111 | stmmi r0!, {r8, r9}
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112 | tst r3, #0x4
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113 | ldrne r10,[r1], #4 /* 4 bytes */
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114 | strne r10,[r0], #4
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115 | sub r2, r2, r3
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116 |
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117 | congruent_aligned32:
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118 | /*
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119 | * here source is aligned to 32 bytes.
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120 | */
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121 |
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122 | cached_aligned32:
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123 | subs r2, r2, #32
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124 | blo less_than_32_left
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125 |
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126 | /*
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127 | * We preload a cache-line up to 64 bytes ahead. On the 926, this will
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128 | * stall only until the requested world is fetched, but the linefill
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129 | * continues in the the background.
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130 | * While the linefill is going, we write our previous cache-line
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131 | * into the write-buffer (which should have some free space).
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132 | * When the linefill is done, the writebuffer will
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133 | * start dumping its content into memory
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134 | *
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135 | * While all this is going, we then load a full cache line into
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136 | * 8 registers, this cache line should be in the cache by now
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137 | * (or partly in the cache).
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138 | *
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139 | * This code should work well regardless of the source/dest alignment.
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140 | *
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141 | */
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142 |
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143 | /* Align the preload register to a cache-line because the cpu does
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144 | * "critical word first" (the first word requested is loaded first).
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145 | */
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146 | @ bic r12, r1, #0x1F
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147 | @ add r12, r12, #64
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148 |
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149 | 1: ldmia r1!, { r4-r11 }
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150 | subs r2, r2, #32
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151 |
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152 | /*
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153 | * NOTE: if r12 is more than 64 ahead of r1, the following ldrhi
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154 | * for ARM9 preload will not be safely guarded by the preceding subs.
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155 | * When it is safely guarded the only possibility to have SIGSEGV here
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156 | * is because the caller overstates the length.
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157 | */
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158 | @ ldrhi r3, [r12], #32 /* cheap ARM9 preload */
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159 | stmia r0!, { r4-r11 }
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160 | bhs 1b
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161 |
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162 | add r2, r2, #32
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163 |
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164 | less_than_32_left:
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165 | /*
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166 | * less than 32 bytes left at this point (length in r2)
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167 | */
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168 |
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169 | /* skip all this if there is nothing to do, which should
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170 | * be a common case (if not executed the code below takes
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171 | * about 16 cycles)
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172 | */
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173 | tst r2, #0x1F
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174 | beq 1f
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175 |
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176 | /* conditionnaly copies 0 to 31 bytes */
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177 | movs r12, r2, lsl #28
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178 | ldmcs r1!, {r4, r5, r6, r7} /* 16 bytes */
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179 | ldmmi r1!, {r8, r9} /* 8 bytes */
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180 | stmcs r0!, {r4, r5, r6, r7}
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181 | stmmi r0!, {r8, r9}
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182 | movs r12, r2, lsl #30
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183 | ldrcs r3, [r1], #4 /* 4 bytes */
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184 | ldrhmi r4, [r1], #2 /* 2 bytes */
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185 | strcs r3, [r0], #4
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186 | strhmi r4, [r0], #2
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187 | tst r2, #0x1
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188 | ldrbne r3, [r1] /* last byte */
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189 | strbne r3, [r0]
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190 |
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191 | /* we're done! restore everything and return */
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192 | 1: ldmfd sp!, {r5-r11}
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193 | ldmfd sp!, {r0, r4, lr}
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194 | bx lr
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195 |
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196 | /********************************************************************/
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197 |
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198 | non_congruent:
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199 | /*
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200 | * here source is aligned to 4 bytes
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201 | * but destination is not.
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202 | *
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203 | * in the code below r2 is the number of bytes read
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204 | * (the number of bytes written is always smaller, because we have
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205 | * partial words in the shift queue)
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206 | */
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207 | cmp r2, #4
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208 | blo copy_last_3_and_return
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209 |
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210 | /* Use post-incriment mode for stm to spill r5-r11 to reserved stack
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211 | * frame. Don't update sp.
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212 | */
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213 | stmea sp, {r5-r11}
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214 |
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215 | /* compute shifts needed to align src to dest */
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216 | rsb r5, r0, #0
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217 | and r5, r5, #3 /* r5 = # bytes in partial words */
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218 | mov r12, r5, lsl #3 /* r12 = right */
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219 | rsb lr, r12, #32 /* lr = left */
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220 |
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221 | /* read the first word */
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222 | ldr r3, [r1], #4
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223 | sub r2, r2, #4
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224 |
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225 | /* write a partial word (0 to 3 bytes), such that destination
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226 | * becomes aligned to 32 bits (r5 = nb of words to copy for alignment)
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227 | */
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228 | movs r5, r5, lsl #31
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229 | strbmi r3, [r0], #1
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230 | movmi r3, r3, lsr #8
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231 | strbcs r3, [r0], #1
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232 | movcs r3, r3, lsr #8
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233 | strbcs r3, [r0], #1
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234 | movcs r3, r3, lsr #8
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235 |
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236 | cmp r2, #4
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237 | blo partial_word_tail
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238 |
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239 | /* Align destination to 32 bytes (cache line boundary) */
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240 | 1: tst r0, #0x1c
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241 | beq 2f
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242 | ldr r5, [r1], #4
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243 | sub r2, r2, #4
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244 | orr r4, r3, r5, lsl lr
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245 | mov r3, r5, lsr r12
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246 | str r4, [r0], #4
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247 | cmp r2, #4
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248 | bhs 1b
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249 | blo partial_word_tail
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250 |
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251 | /* copy 32 bytes at a time */
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252 | 2: subs r2, r2, #32
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253 | blo less_than_thirtytwo
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254 |
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255 | /* Use immediate mode for the shifts, because there is an extra cycle
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256 | * for register shifts, which could account for up to 50% of
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257 | * performance hit.
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258 | */
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259 |
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260 | cmp r12, #24
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261 | beq loop24
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262 | cmp r12, #8
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263 | beq loop8
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264 |
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265 | loop16:
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266 | ldr r12, [r1], #4
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267 | 1: mov r4, r12
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268 | ldmia r1!, { r5,r6,r7, r8,r9,r10,r11}
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269 | subs r2, r2, #32
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270 | ldrhs r12, [r1], #4
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271 | orr r3, r3, r4, lsl #16
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272 | mov r4, r4, lsr #16
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273 | orr r4, r4, r5, lsl #16
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274 | mov r5, r5, lsr #16
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275 | orr r5, r5, r6, lsl #16
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276 | mov r6, r6, lsr #16
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277 | orr r6, r6, r7, lsl #16
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278 | mov r7, r7, lsr #16
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279 | orr r7, r7, r8, lsl #16
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280 | mov r8, r8, lsr #16
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281 | orr r8, r8, r9, lsl #16
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282 | mov r9, r9, lsr #16
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283 | orr r9, r9, r10, lsl #16
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284 | mov r10, r10, lsr #16
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285 | orr r10, r10, r11, lsl #16
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286 | stmia r0!, {r3,r4,r5,r6, r7,r8,r9,r10}
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287 | mov r3, r11, lsr #16
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288 | bhs 1b
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289 | b less_than_thirtytwo
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290 |
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291 | loop8:
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292 | ldr r12, [r1], #4
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293 | 1: mov r4, r12
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294 | ldmia r1!, { r5,r6,r7, r8,r9,r10,r11}
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295 | subs r2, r2, #32
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296 | ldrhs r12, [r1], #4
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297 | orr r3, r3, r4, lsl #24
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298 | mov r4, r4, lsr #8
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299 | orr r4, r4, r5, lsl #24
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300 | mov r5, r5, lsr #8
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301 | orr r5, r5, r6, lsl #24
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302 | mov r6, r6, lsr #8
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303 | orr r6, r6, r7, lsl #24
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304 | mov r7, r7, lsr #8
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305 | orr r7, r7, r8, lsl #24
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306 | mov r8, r8, lsr #8
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307 | orr r8, r8, r9, lsl #24
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308 | mov r9, r9, lsr #8
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309 | orr r9, r9, r10, lsl #24
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310 | mov r10, r10, lsr #8
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311 | orr r10, r10, r11, lsl #24
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312 | stmia r0!, {r3,r4,r5,r6, r7,r8,r9,r10}
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313 | mov r3, r11, lsr #8
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314 | bhs 1b
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315 | b less_than_thirtytwo
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316 |
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317 | loop24:
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318 | ldr r12, [r1], #4
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319 | 1: mov r4, r12
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320 | ldmia r1!, { r5,r6,r7, r8,r9,r10,r11}
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321 | subs r2, r2, #32
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322 | ldrhs r12, [r1], #4
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323 | orr r3, r3, r4, lsl #8
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324 | mov r4, r4, lsr #24
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325 | orr r4, r4, r5, lsl #8
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326 | mov r5, r5, lsr #24
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327 | orr r5, r5, r6, lsl #8
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328 | mov r6, r6, lsr #24
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329 | orr r6, r6, r7, lsl #8
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330 | mov r7, r7, lsr #24
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331 | orr r7, r7, r8, lsl #8
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332 | mov r8, r8, lsr #24
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333 | orr r8, r8, r9, lsl #8
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334 | mov r9, r9, lsr #24
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335 | orr r9, r9, r10, lsl #8
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336 | mov r10, r10, lsr #24
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337 | orr r10, r10, r11, lsl #8
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338 | stmia r0!, {r3,r4,r5,r6, r7,r8,r9,r10}
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339 | mov r3, r11, lsr #24
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340 | bhs 1b
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341 |
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342 | less_than_thirtytwo:
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343 | /* copy the last 0 to 31 bytes of the source */
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344 | rsb r12, lr, #32 /* we corrupted r12, recompute it */
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345 | add r2, r2, #32
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346 | cmp r2, #4
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347 | blo partial_word_tail
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348 |
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349 | 1: ldr r5, [r1], #4
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350 | sub r2, r2, #4
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351 | orr r4, r3, r5, lsl lr
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352 | mov r3, r5, lsr r12
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353 | str r4, [r0], #4
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354 | cmp r2, #4
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355 | bhs 1b
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356 |
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357 | partial_word_tail:
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358 | /* we have a partial word in the input buffer */
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359 | movs r5, lr, lsl #(31-3)
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360 | strbmi r3, [r0], #1
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361 | movmi r3, r3, lsr #8
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362 | strbcs r3, [r0], #1
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363 | movcs r3, r3, lsr #8
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364 | strbcs r3, [r0], #1
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365 |
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366 | /* Refill spilled registers from the stack. Don't update sp. */
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367 | ldmfd sp, {r5-r11}
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368 |
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369 | copy_last_3_and_return:
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370 | movs r2, r2, lsl #31 /* copy remaining 0, 1, 2 or 3 bytes */
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371 | ldrbmi r2, [r1], #1
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372 | ldrbcs r3, [r1], #1
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373 | ldrbcs r12,[r1]
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374 | strbmi r2, [r0], #1
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375 | strbcs r3, [r0], #1
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376 | strbcs r12,[r0]
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377 |
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378 | /* we're done! restore sp and spilled registers and return */
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379 | add sp, sp, #28
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380 | ldmfd sp!, {r0, r4, lr}
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381 | bx lr
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382 |
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383 | #endif
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