1 | /* mbed Microcontroller Library
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2 | * Copyright (c) 2006-2013 ARM Limited
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3 | *
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4 | * Licensed under the Apache License, Version 2.0 (the "License");
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5 | * you may not use this file except in compliance with the License.
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6 | * You may obtain a copy of the License at
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7 | *
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8 | * http://www.apache.org/licenses/LICENSE-2.0
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9 | *
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10 | * Unless required by applicable law or agreed to in writing, software
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11 | * distributed under the License is distributed on an "AS IS" BASIS,
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12 | * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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13 | * See the License for the specific language governing permissions and
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14 | * limitations under the License.
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15 | */
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16 | #include "mbed_assert.h"
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17 | #include <math.h>
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18 |
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19 | #include "spi_api.h"
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20 | #include "cmsis.h"
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21 | #include "pinmap.h"
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22 | #include "mbed_error.h"
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23 | #include "RZ_A1_Init.h"
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24 |
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25 | static const PinMap PinMap_SPI_SCLK[] = {
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26 | {P10_12, SPI_0, 4},
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27 | {P4_4 , SPI_1, 2},
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28 | {P6_4 , SPI_1, 7},
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29 | {P11_12, SPI_1, 2},
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30 | {P8_3 , SPI_2, 3},
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31 | {P5_0 , SPI_3, 8},
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32 | {NC , NC , 0}
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33 | };
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34 |
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35 | static const PinMap PinMap_SPI_SSEL[] = {
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36 | {P10_13, SPI_0, 4},
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37 | {P4_5 , SPI_1, 2},
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38 | {P6_5 , SPI_1, 7},
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39 | {P11_13, SPI_1, 2},
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40 | {P8_4 , SPI_2, 3},
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41 | {P5_1 , SPI_3, 8},
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42 | {NC , NC , 0}
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43 | };
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44 |
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45 | static const PinMap PinMap_SPI_MOSI[] = {
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46 | {P10_14, SPI_0, 4},
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47 | {P4_6 , SPI_1, 2},
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48 | {P6_6 , SPI_1, 7},
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49 | {P11_14, SPI_1, 2},
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50 | {P8_5 , SPI_2, 3},
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51 | {P5_2 , SPI_3, 8},
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52 | {NC , NC , 0}
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53 | };
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54 |
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55 | static const PinMap PinMap_SPI_MISO[] = {
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56 | {P10_15, SPI_0, 4},
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57 | {P4_7 , SPI_1, 2},
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58 | {P6_7 , SPI_1, 7},
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59 | {P11_15, SPI_1, 2},
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60 | {P8_6 , SPI_2, 3},
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61 | {P5_3 , SPI_3, 8},
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62 | {NC , NC , 0}
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63 | };
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64 |
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65 | static const struct st_rspi *RSPI[] = RSPI_ADDRESS_LIST;
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66 |
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67 | static inline void spi_disable(spi_t *obj);
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68 | static inline void spi_enable(spi_t *obj);
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69 | static inline int spi_readable(spi_t *obj);
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70 | static inline void spi_write(spi_t *obj, int value);
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71 | static inline int spi_read(spi_t *obj);
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72 |
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73 | void spi_init(spi_t *obj, PinName mosi, PinName miso, PinName sclk, PinName ssel) {
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74 | // determine the SPI to use
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75 | volatile uint8_t dummy;
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76 | uint32_t spi_mosi = pinmap_peripheral(mosi, PinMap_SPI_MOSI);
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77 | uint32_t spi_miso = pinmap_peripheral(miso, PinMap_SPI_MISO);
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78 | uint32_t spi_sclk = pinmap_peripheral(sclk, PinMap_SPI_SCLK);
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79 | uint32_t spi_ssel = pinmap_peripheral(ssel, PinMap_SPI_SSEL);
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80 | uint32_t spi_data = pinmap_merge(spi_mosi, spi_miso);
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81 | uint32_t spi_cntl = pinmap_merge(spi_sclk, spi_ssel);
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82 | uint32_t spi = pinmap_merge(spi_data, spi_cntl);
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83 |
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84 | MBED_ASSERT((int)spi != NC);
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85 |
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86 | obj->spi.spi = (struct st_rspi *)RSPI[spi];
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87 | obj->spi.index = spi;
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88 |
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89 | // enable power and clocking
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90 | switch (spi) {
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91 | case SPI_0: CPGSTBCR10 &= ~(0x80); break;
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92 | case SPI_1: CPGSTBCR10 &= ~(0x40); break;
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93 | case SPI_2: CPGSTBCR10 &= ~(0x20); break;
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94 | case SPI_3: CPGSTBCR10 &= ~(0x10); break;
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95 | }
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96 | dummy = CPGSTBCR10;
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97 |
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98 | obj->spi.spi->SPCR = 0x00; // CTRL to 0
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99 | obj->spi.spi->SPSCR = 0x00; // no sequential operation
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100 | obj->spi.spi->SSLP = 0x00; // SSL 'L' active
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101 | obj->spi.spi->SPDCR = 0x20; // byte access
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102 | obj->spi.spi->SPCKD = 0x00; // SSL -> enable CLK delay : 1RSPCK
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103 | obj->spi.spi->SSLND = 0x00; // CLK end -> SSL neg delay : 1RSPCK
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104 | obj->spi.spi->SPND = 0x00; // delay between CMD : 1RSPCK + 2P1CLK
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105 | obj->spi.spi->SPPCR = 0x20; // MOSI Idle fixed value equals 0
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106 | obj->spi.spi->SPBFCR = 0xf0; // and set trigger count: read 1, write 1
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107 | obj->spi.spi->SPBFCR = 0x30; // and reset buffer
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108 |
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109 | // pin out the spi pins
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110 | pinmap_pinout(mosi, PinMap_SPI_MOSI);
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111 | pinmap_pinout(miso, PinMap_SPI_MISO);
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112 | pinmap_pinout(sclk, PinMap_SPI_SCLK);
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113 | if ((int)ssel != NC) {
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114 | pinmap_pinout(ssel, PinMap_SPI_SSEL);
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115 | }
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116 | }
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117 |
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118 | void spi_free(spi_t *obj) {}
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119 |
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120 | void spi_format(spi_t *obj, int bits, int mode, int slave) {
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121 | int DSS; // DSS (data select size)
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122 | int polarity = (mode & 0x2) ? 1 : 0;
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123 | int phase = (mode & 0x1) ? 1 : 0;
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124 | uint16_t tmp = 0;
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125 | uint16_t mask = 0xf03;
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126 | uint16_t wk_spcmd0;
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127 | uint8_t splw;
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128 |
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129 | switch (mode) {
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130 | case 0:
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131 | case 1:
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132 | case 2:
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133 | case 3:
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134 | // Do Nothing
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135 | break;
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136 | default:
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137 | error("SPI format error");
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138 | return;
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139 | }
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140 |
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141 | switch (bits) {
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142 | case 8:
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143 | DSS = 0x7;
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144 | splw = 0x20;
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145 | break;
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146 | case 16:
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147 | DSS = 0xf;
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148 | splw = 0x40;
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149 | break;
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150 | case 32:
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151 | DSS = 0x2;
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152 | splw = 0x60;
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153 | break;
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154 | default:
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155 | error("SPI module don't support other than 8/16/32bits");
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156 | return;
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157 | }
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158 | tmp |= phase;
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159 | tmp |= (polarity << 1);
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160 | tmp |= (DSS << 8);
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161 | obj->spi.bits = bits;
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162 |
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163 | spi_disable(obj);
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164 | wk_spcmd0 = obj->spi.spi->SPCMD0;
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165 | wk_spcmd0 &= ~mask;
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166 | wk_spcmd0 |= (mask & tmp);
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167 | obj->spi.spi->SPCMD0 = wk_spcmd0;
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168 | obj->spi.spi->SPDCR = splw;
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169 | if (slave) {
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170 | obj->spi.spi->SPCR &=~(1 << 3); // MSTR to 0
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171 | } else {
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172 | obj->spi.spi->SPCR |= (1 << 3); // MSTR to 1
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173 | }
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174 | spi_enable(obj);
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175 | }
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176 |
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177 | void spi_frequency(spi_t *obj, int hz) {
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178 | uint32_t pclk_base;
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179 | uint32_t div;
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180 | uint32_t brdv = 0;
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181 | uint32_t hz_max;
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182 | uint32_t hz_min;
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183 | uint16_t mask = 0x000c;
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184 | uint16_t wk_spcmd0;
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185 |
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186 | /* set PCLK */
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187 | if (RZ_A1_IsClockMode0() == false) {
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188 | pclk_base = CM1_RENESAS_RZ_A1_P1_CLK;
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189 | } else {
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190 | pclk_base = CM0_RENESAS_RZ_A1_P1_CLK;
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191 | }
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192 |
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193 | hz_min = pclk_base / 2 / 256 / 8;
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194 | hz_max = pclk_base / 2;
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195 | if ((hz < hz_min) || (hz > hz_max)) {
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196 | error("Couldn't setup requested SPI frequency");
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197 | return;
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198 | }
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199 |
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200 | div = (pclk_base / hz / 2);
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201 | while (div > 256) {
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202 | div >>= 1;
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203 | brdv++;
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204 | }
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205 | div -= 1;
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206 | brdv = (brdv << 2);
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207 |
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208 | spi_disable(obj);
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209 | obj->spi.spi->SPBR = div;
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210 | wk_spcmd0 = obj->spi.spi->SPCMD0;
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211 | wk_spcmd0 &= ~mask;
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212 | wk_spcmd0 |= (mask & brdv);
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213 | obj->spi.spi->SPCMD0 = wk_spcmd0;
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214 | spi_enable(obj);
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215 | }
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216 |
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217 | static inline void spi_disable(spi_t *obj) {
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218 | obj->spi.spi->SPCR &= ~(1 << 6); // SPE to 0
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219 | }
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220 |
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221 | static inline void spi_enable(spi_t *obj) {
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222 | obj->spi.spi->SPCR |= (1 << 6); // SPE to 1
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223 | }
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224 |
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225 | static inline int spi_readable(spi_t *obj) {
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226 | return obj->spi.spi->SPSR & (1 << 7); // SPRF
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227 | }
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228 |
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229 | static inline int spi_tend(spi_t *obj) {
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230 | return obj->spi.spi->SPSR & (1 << 6); // TEND
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231 | }
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232 |
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233 | static inline void spi_write(spi_t *obj, int value) {
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234 | if (obj->spi.bits == 8) {
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235 | obj->spi.spi->SPDR.UINT8[0] = (uint8_t)value;
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236 | } else if (obj->spi.bits == 16) {
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237 | obj->spi.spi->SPDR.UINT16[0] = (uint16_t)value;
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238 | } else {
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239 | obj->spi.spi->SPDR.UINT32 = (uint32_t)value;
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240 | }
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241 | }
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242 |
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243 | static inline int spi_read(spi_t *obj) {
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244 | int read_data;
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245 |
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246 | if (obj->spi.bits == 8) {
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247 | read_data = obj->spi.spi->SPDR.UINT8[0];
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248 | } else if (obj->spi.bits == 16) {
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249 | read_data = obj->spi.spi->SPDR.UINT16[0];
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250 | } else {
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251 | read_data = obj->spi.spi->SPDR.UINT32;
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252 | }
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253 |
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254 | return read_data;
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255 | }
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256 |
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257 | int spi_master_write(spi_t *obj, int value) {
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258 | spi_write(obj, value);
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259 | while(!spi_tend(obj));
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260 | return spi_read(obj);
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261 | }
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262 |
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263 | int spi_slave_receive(spi_t *obj) {
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264 | return (spi_readable(obj) && !spi_busy(obj)) ? (1) : (0);
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265 | }
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266 |
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267 | int spi_slave_read(spi_t *obj) {
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268 | return spi_read(obj);
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269 | }
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270 |
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271 | void spi_slave_write(spi_t *obj, int value) {
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272 | spi_write(obj, value);
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273 | }
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274 |
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275 | int spi_busy(spi_t *obj) {
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276 | return 0;
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277 | }
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278 |
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279 | #if DEVICE_SPI_ASYNCH
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280 |
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281 | #define IRQ_NUM 2
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282 |
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283 | static void spi_irqs_set(spi_t *obj, uint32_t enable);
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284 | static void spi_async_write(spi_t *obj);
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285 | static void spi_async_read(spi_t *obj);
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286 |
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287 | static void spi0_rx_irq(void);
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288 | static void spi1_rx_irq(void);
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289 | static void spi2_rx_irq(void);
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290 | static void spi3_rx_irq(void);
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291 | static void spi4_rx_irq(void);
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292 | static void spi0_er_irq(void);
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293 | static void spi1_er_irq(void);
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294 | static void spi2_er_irq(void);
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295 | static void spi3_er_irq(void);
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296 | static void spi4_er_irq(void);
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297 |
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298 | static const IRQn_Type irq_set_tbl[RSPI_COUNT][IRQ_NUM] = {
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299 | {RSPISPRI0_IRQn, RSPISPEI0_IRQn},
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300 | {RSPISPRI1_IRQn, RSPISPEI1_IRQn},
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301 | {RSPISPRI2_IRQn, RSPISPEI2_IRQn},
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302 | {RSPISPRI3_IRQn, RSPISPEI3_IRQn},
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303 | {RSPISPRI4_IRQn, RSPISPEI4_IRQn}
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304 | };
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305 |
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306 | static const IRQHandler hander_set_tbl[RSPI_COUNT][IRQ_NUM] = {
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307 | {spi0_rx_irq, spi0_er_irq},
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308 | {spi1_rx_irq, spi1_er_irq},
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309 | {spi2_rx_irq, spi2_er_irq},
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310 | {spi3_rx_irq, spi3_er_irq},
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311 | {spi4_rx_irq, spi4_er_irq}
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312 | };
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313 |
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314 | struct spi_global_data_s {
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315 | spi_t *async_obj;
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316 | uint32_t async_callback, event, wanted_events;
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317 | };
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318 |
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319 | static struct spi_global_data_s spi_data[RSPI_COUNT];
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320 |
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321 | static void spi_rx_irq(IRQn_Type irq_num, uint32_t index)
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322 | {
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323 | spi_t *obj = spi_data[index].async_obj;
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324 | if (obj->rx_buff.buffer && obj->rx_buff.pos < obj->rx_buff.length) {
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325 | spi_async_read(obj);
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326 | } else {
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327 | if (obj->rx_buff.buffer && obj->tx_buff.buffer && obj->tx_buff.pos < obj->tx_buff.length) {
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328 | spi_data[obj->spi.index].event = SPI_EVENT_INTERNAL_TRANSFER_COMPLETE;
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329 | if (spi_data[obj->spi.index].wanted_events & SPI_EVENT_COMPLETE) {
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330 | spi_data[obj->spi.index].event |= SPI_EVENT_COMPLETE;
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331 | }
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332 | spi_irqs_set(obj, 0);
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333 | spi_data[obj->spi.index].async_obj = NULL;
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334 | ((void (*)())spi_data[obj->spi.index].async_callback)();
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335 | return;
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336 | }
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337 | spi_read(obj);
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338 | }
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339 | if (obj->tx_buff.buffer) {
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340 | if (obj->tx_buff.pos == obj->tx_buff.length) {
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341 | spi_data[obj->spi.index].event = SPI_EVENT_INTERNAL_TRANSFER_COMPLETE;
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342 | if (spi_data[obj->spi.index].wanted_events & SPI_EVENT_COMPLETE) {
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343 | spi_data[obj->spi.index].event |= SPI_EVENT_COMPLETE;
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344 | }
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345 | spi_irqs_set(obj, 0);
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346 | spi_data[obj->spi.index].async_obj = NULL;
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347 | ((void (*)())spi_data[obj->spi.index].async_callback)();
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348 | } else {
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349 | spi_async_write(obj);
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350 | }
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351 | } else {
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352 | if (obj->rx_buff.pos == obj->rx_buff.length) {
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353 | spi_data[obj->spi.index].event = SPI_EVENT_INTERNAL_TRANSFER_COMPLETE;
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354 | if (spi_data[obj->spi.index].wanted_events & SPI_EVENT_COMPLETE) {
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355 | spi_data[obj->spi.index].event |= SPI_EVENT_COMPLETE;
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356 | }
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357 | spi_irqs_set(obj, 0);
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358 | spi_data[obj->spi.index].async_obj = NULL;
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359 | ((void (*)())spi_data[obj->spi.index].async_callback)();
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360 | } else {
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361 | spi_async_write(obj);
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362 | }
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363 | }
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364 | }
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365 |
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366 | static void spi_err_irq(IRQn_Type irq_num, uint32_t index)
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367 | {
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368 | spi_t *obj = spi_data[index].async_obj;
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369 | spi_abort_asynch(obj);
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370 | spi_data[index].event = SPI_EVENT_ERROR;
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371 | if (spi_data[index].wanted_events & SPI_EVENT_ERROR) {
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372 | ((void (*)())spi_data[index].async_callback)();
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373 | }
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374 | }
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375 |
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376 | static void spi0_rx_irq(void)
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377 | {
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378 | spi_rx_irq(RSPISPRI0_IRQn, 0);
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379 | }
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380 |
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381 | static void spi1_rx_irq(void)
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382 | {
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383 | spi_rx_irq(RSPISPRI1_IRQn, 1);
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384 | }
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385 |
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386 | static void spi2_rx_irq(void)
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387 | {
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388 | spi_rx_irq(RSPISPRI2_IRQn, 2);
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389 | }
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390 |
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391 | static void spi3_rx_irq(void)
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392 | {
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393 | spi_rx_irq(RSPISPRI3_IRQn, 3);
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394 | }
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395 |
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396 | static void spi4_rx_irq(void)
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397 | {
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398 | spi_rx_irq(RSPISPRI4_IRQn, 4);
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399 | }
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400 |
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401 | static void spi0_er_irq(void)
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402 | {
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403 | spi_err_irq(RSPISPEI0_IRQn, 0);
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404 | }
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405 |
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406 | static void spi1_er_irq(void)
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407 | {
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408 | spi_err_irq(RSPISPEI1_IRQn, 1);
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409 | }
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410 |
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411 | static void spi2_er_irq(void)
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412 | {
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413 | spi_err_irq(RSPISPEI2_IRQn, 2);
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414 | }
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415 |
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416 | static void spi3_er_irq(void)
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417 | {
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418 | spi_err_irq(RSPISPEI3_IRQn, 3);
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419 | }
|
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420 |
|
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421 | static void spi4_er_irq(void)
|
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422 | {
|
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423 | spi_err_irq(RSPISPEI4_IRQn, 4);
|
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424 | }
|
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425 |
|
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426 | static void spi_irqs_set(spi_t *obj, uint32_t enable)
|
---|
427 | {
|
---|
428 | int i;
|
---|
429 | const IRQn_Type *irqTable = irq_set_tbl[obj->spi.index];
|
---|
430 | const IRQHandler *handlerTable = hander_set_tbl[obj->spi.index];
|
---|
431 | for (i = 0; i < IRQ_NUM; ++i) {
|
---|
432 | if (enable) {
|
---|
433 | InterruptHandlerRegister(irqTable[i], handlerTable[i]);
|
---|
434 | GIC_SetPriority(irqTable[i], 5);
|
---|
435 | GIC_EnableIRQ(irqTable[i]);
|
---|
436 | } else {
|
---|
437 | GIC_DisableIRQ(irqTable[i]);
|
---|
438 | }
|
---|
439 | }
|
---|
440 | if (enable) {
|
---|
441 | obj->spi.spi->SPCR |= (1 << 4) | (1 << 7);
|
---|
442 | } else {
|
---|
443 | obj->spi.spi->SPCR &= ~((1 << 4) | (1 << 7));
|
---|
444 | }
|
---|
445 | }
|
---|
446 |
|
---|
447 | static void spi_async_write(spi_t *obj)
|
---|
448 | {
|
---|
449 | uint8_t **width8;
|
---|
450 | uint16_t **width16;
|
---|
451 | uint32_t **width32;
|
---|
452 |
|
---|
453 | if (obj->tx_buff.buffer) {
|
---|
454 | switch (obj->tx_buff.width) {
|
---|
455 | case 8:
|
---|
456 | width8 = (uint8_t **)&obj->tx_buff.buffer;
|
---|
457 | spi_write(obj, **width8);
|
---|
458 | ++*width8;
|
---|
459 | obj->tx_buff.pos += sizeof(uint8_t);
|
---|
460 | break;
|
---|
461 |
|
---|
462 | case 16:
|
---|
463 | width16 = (uint16_t **)&obj->tx_buff.buffer;
|
---|
464 | spi_write(obj, **width16);
|
---|
465 | ++*width16;
|
---|
466 | obj->tx_buff.pos += sizeof(uint16_t);
|
---|
467 | break;
|
---|
468 |
|
---|
469 | case 32:
|
---|
470 | width32 = (uint32_t **)&obj->tx_buff.buffer;
|
---|
471 | spi_write(obj, **width32);
|
---|
472 | ++*width32;
|
---|
473 | obj->tx_buff.pos += sizeof(uint32_t);
|
---|
474 | break;
|
---|
475 |
|
---|
476 | default:
|
---|
477 | MBED_ASSERT(0);
|
---|
478 | break;
|
---|
479 | }
|
---|
480 | } else {
|
---|
481 | spi_write(obj, SPI_FILL_WORD);
|
---|
482 | }
|
---|
483 | }
|
---|
484 |
|
---|
485 | static void spi_async_read(spi_t *obj)
|
---|
486 | {
|
---|
487 | uint8_t **width8;
|
---|
488 | uint16_t **width16;
|
---|
489 | uint32_t **width32;
|
---|
490 |
|
---|
491 | switch (obj->rx_buff.width) {
|
---|
492 | case 8:
|
---|
493 | width8 = (uint8_t **)&obj->rx_buff.buffer;
|
---|
494 | **width8 = spi_read(obj);
|
---|
495 | ++*width8;
|
---|
496 | obj->rx_buff.pos += sizeof(uint8_t);
|
---|
497 | break;
|
---|
498 |
|
---|
499 | case 16:
|
---|
500 | width16 = (uint16_t **)&obj->rx_buff.buffer;
|
---|
501 | **width16 = spi_read(obj);
|
---|
502 | ++*width16;
|
---|
503 | obj->rx_buff.pos += sizeof(uint16_t);
|
---|
504 | break;
|
---|
505 |
|
---|
506 | case 32:
|
---|
507 | width32 = (uint32_t **)&obj->rx_buff.buffer;
|
---|
508 | **width32 = spi_read(obj);
|
---|
509 | ++*width32;
|
---|
510 | obj->rx_buff.pos += sizeof(uint32_t);
|
---|
511 | break;
|
---|
512 |
|
---|
513 | default:
|
---|
514 | MBED_ASSERT(0);
|
---|
515 | break;
|
---|
516 | }
|
---|
517 | }
|
---|
518 |
|
---|
519 | /******************************************************************************
|
---|
520 | * ASYNCHRONOUS HAL
|
---|
521 | ******************************************************************************/
|
---|
522 |
|
---|
523 | void spi_master_transfer(spi_t *obj, const void *tx, size_t tx_length, void *rx, size_t rx_length, uint8_t bit_width, uint32_t handler, uint32_t event, DMAUsage hint)
|
---|
524 | {
|
---|
525 | int i;
|
---|
526 | MBED_ASSERT(obj);
|
---|
527 | MBED_ASSERT(tx || rx);
|
---|
528 | MBED_ASSERT(tx && ! rx ? tx_length : 1);
|
---|
529 | MBED_ASSERT(rx && ! tx ? rx_length : 1);
|
---|
530 | MBED_ASSERT(obj->spi.spi->SPCR & (1 << 3)); /* Slave mode */
|
---|
531 | MBED_ASSERT(bit_width == 8 || bit_width == 16 || bit_width == 32);
|
---|
532 |
|
---|
533 | if (tx_length) {
|
---|
534 | obj->tx_buff.buffer = (void *)tx;
|
---|
535 | } else {
|
---|
536 | obj->tx_buff.buffer = NULL;
|
---|
537 | }
|
---|
538 | obj->tx_buff.length = tx_length * bit_width / 8;
|
---|
539 | obj->tx_buff.pos = 0;
|
---|
540 | obj->tx_buff.width = bit_width;
|
---|
541 | if (rx_length) {
|
---|
542 | obj->rx_buff.buffer = rx;
|
---|
543 | } else {
|
---|
544 | obj->rx_buff.buffer = NULL;
|
---|
545 | }
|
---|
546 | obj->rx_buff.length = rx_length * bit_width / 8;
|
---|
547 | obj->rx_buff.pos = 0;
|
---|
548 | obj->rx_buff.width = bit_width;
|
---|
549 | for (i = 0; i < obj->rx_buff.length; i++) {
|
---|
550 | ((uint8_t *)obj->rx_buff.buffer)[i] = SPI_FILL_WORD;
|
---|
551 | }
|
---|
552 |
|
---|
553 | spi_data[obj->spi.index].async_callback = handler;
|
---|
554 | spi_data[obj->spi.index].async_obj = obj;
|
---|
555 | spi_data[obj->spi.index].event = 0;
|
---|
556 | spi_data[obj->spi.index].wanted_events = event;
|
---|
557 |
|
---|
558 | spi_irqs_set(obj, 1);
|
---|
559 |
|
---|
560 | spi_async_write(obj);
|
---|
561 | }
|
---|
562 |
|
---|
563 | uint32_t spi_irq_handler_asynch(spi_t *obj)
|
---|
564 | {
|
---|
565 | return spi_data[obj->spi.index].event;
|
---|
566 | }
|
---|
567 |
|
---|
568 | uint8_t spi_active(spi_t *obj)
|
---|
569 | {
|
---|
570 | return spi_data[obj->spi.index].async_obj != NULL;
|
---|
571 | }
|
---|
572 |
|
---|
573 | void spi_abort_asynch(spi_t *obj)
|
---|
574 | {
|
---|
575 | spi_disable(obj);
|
---|
576 | spi_irqs_set(obj, 0);
|
---|
577 | spi_data[obj->spi.index].async_obj = NULL;
|
---|
578 | spi_enable(obj);
|
---|
579 | }
|
---|
580 |
|
---|
581 | #endif
|
---|