[352] | 1 | /* mbed Microcontroller Library
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| 2 | * Copyright (c) 2006-2013 ARM Limited
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| 3 | *
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| 4 | * Licensed under the Apache License, Version 2.0 (the "License");
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| 5 | * you may not use this file except in compliance with the License.
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| 6 | * You may obtain a copy of the License at
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| 7 | *
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| 8 | * http://www.apache.org/licenses/LICENSE-2.0
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| 9 | *
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| 10 | * Unless required by applicable law or agreed to in writing, software
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| 11 | * distributed under the License is distributed on an "AS IS" BASIS,
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| 12 | * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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| 13 | * See the License for the specific language governing permissions and
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| 14 | * limitations under the License.
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| 15 | */
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| 16 | #include "mbed_assert.h"
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| 17 | #include <math.h>
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| 18 |
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| 19 | #include "spi_api.h"
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| 20 | #include "cmsis.h"
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| 21 | #include "pinmap.h"
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| 22 | #include "mbed_error.h"
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| 23 | #include "RZ_A1_Init.h"
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| 24 |
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| 25 | static const PinMap PinMap_SPI_SCLK[] = {
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| 26 | {P10_12, SPI_0, 4},
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| 27 | {P4_4 , SPI_1, 2},
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| 28 | {P6_4 , SPI_1, 7},
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| 29 | {P11_12, SPI_1, 2},
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| 30 | {P8_3 , SPI_2, 3},
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| 31 | {P5_0 , SPI_3, 8},
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| 32 | {NC , NC , 0}
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| 33 | };
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| 34 |
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| 35 | static const PinMap PinMap_SPI_SSEL[] = {
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| 36 | {P10_13, SPI_0, 4},
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| 37 | {P4_5 , SPI_1, 2},
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| 38 | {P6_5 , SPI_1, 7},
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| 39 | {P11_13, SPI_1, 2},
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| 40 | {P8_4 , SPI_2, 3},
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| 41 | {P5_1 , SPI_3, 8},
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| 42 | {NC , NC , 0}
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| 43 | };
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| 44 |
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| 45 | static const PinMap PinMap_SPI_MOSI[] = {
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| 46 | {P10_14, SPI_0, 4},
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| 47 | {P4_6 , SPI_1, 2},
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| 48 | {P6_6 , SPI_1, 7},
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| 49 | {P11_14, SPI_1, 2},
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| 50 | {P8_5 , SPI_2, 3},
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| 51 | {P5_2 , SPI_3, 8},
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| 52 | {NC , NC , 0}
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| 53 | };
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| 54 |
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| 55 | static const PinMap PinMap_SPI_MISO[] = {
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| 56 | {P10_15, SPI_0, 4},
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| 57 | {P4_7 , SPI_1, 2},
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| 58 | {P6_7 , SPI_1, 7},
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| 59 | {P11_15, SPI_1, 2},
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| 60 | {P8_6 , SPI_2, 3},
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| 61 | {P5_3 , SPI_3, 8},
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| 62 | {NC , NC , 0}
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| 63 | };
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| 64 |
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| 65 | static const struct st_rspi *RSPI[] = RSPI_ADDRESS_LIST;
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| 66 |
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| 67 | static inline void spi_disable(spi_t *obj);
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| 68 | static inline void spi_enable(spi_t *obj);
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| 69 | static inline int spi_readable(spi_t *obj);
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| 70 | static inline void spi_write(spi_t *obj, int value);
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| 71 | static inline int spi_read(spi_t *obj);
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| 72 |
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| 73 | void spi_init(spi_t *obj, PinName mosi, PinName miso, PinName sclk, PinName ssel) {
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| 74 | // determine the SPI to use
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| 75 | volatile uint8_t dummy;
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| 76 | uint32_t spi_mosi = pinmap_peripheral(mosi, PinMap_SPI_MOSI);
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| 77 | uint32_t spi_miso = pinmap_peripheral(miso, PinMap_SPI_MISO);
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| 78 | uint32_t spi_sclk = pinmap_peripheral(sclk, PinMap_SPI_SCLK);
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| 79 | uint32_t spi_ssel = pinmap_peripheral(ssel, PinMap_SPI_SSEL);
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| 80 | uint32_t spi_data = pinmap_merge(spi_mosi, spi_miso);
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| 81 | uint32_t spi_cntl = pinmap_merge(spi_sclk, spi_ssel);
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| 82 | uint32_t spi = pinmap_merge(spi_data, spi_cntl);
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| 83 |
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| 84 | MBED_ASSERT((int)spi != NC);
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| 85 |
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| 86 | obj->spi.spi = (struct st_rspi *)RSPI[spi];
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| 87 | obj->spi.index = spi;
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| 88 |
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| 89 | // enable power and clocking
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| 90 | switch (spi) {
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| 91 | case SPI_0: CPGSTBCR10 &= ~(0x80); break;
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| 92 | case SPI_1: CPGSTBCR10 &= ~(0x40); break;
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| 93 | case SPI_2: CPGSTBCR10 &= ~(0x20); break;
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| 94 | case SPI_3: CPGSTBCR10 &= ~(0x10); break;
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| 95 | }
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| 96 | dummy = CPGSTBCR10;
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| 97 |
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| 98 | obj->spi.spi->SPCR = 0x00; // CTRL to 0
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| 99 | obj->spi.spi->SPSCR = 0x00; // no sequential operation
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| 100 | obj->spi.spi->SSLP = 0x00; // SSL 'L' active
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| 101 | obj->spi.spi->SPDCR = 0x20; // byte access
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| 102 | obj->spi.spi->SPCKD = 0x00; // SSL -> enable CLK delay : 1RSPCK
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| 103 | obj->spi.spi->SSLND = 0x00; // CLK end -> SSL neg delay : 1RSPCK
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| 104 | obj->spi.spi->SPND = 0x00; // delay between CMD : 1RSPCK + 2P1CLK
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| 105 | obj->spi.spi->SPPCR = 0x20; // MOSI Idle fixed value equals 0
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| 106 | obj->spi.spi->SPBFCR = 0xf0; // and set trigger count: read 1, write 1
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| 107 | obj->spi.spi->SPBFCR = 0x30; // and reset buffer
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| 108 |
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| 109 | // pin out the spi pins
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| 110 | pinmap_pinout(mosi, PinMap_SPI_MOSI);
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| 111 | pinmap_pinout(miso, PinMap_SPI_MISO);
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| 112 | pinmap_pinout(sclk, PinMap_SPI_SCLK);
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| 113 | if ((int)ssel != NC) {
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| 114 | pinmap_pinout(ssel, PinMap_SPI_SSEL);
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| 115 | }
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| 116 | }
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| 117 |
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| 118 | void spi_free(spi_t *obj) {}
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| 119 |
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| 120 | void spi_format(spi_t *obj, int bits, int mode, int slave) {
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| 121 | int DSS; // DSS (data select size)
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| 122 | int polarity = (mode & 0x2) ? 1 : 0;
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| 123 | int phase = (mode & 0x1) ? 1 : 0;
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| 124 | uint16_t tmp = 0;
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| 125 | uint16_t mask = 0xf03;
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| 126 | uint16_t wk_spcmd0;
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| 127 | uint8_t splw;
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| 128 |
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| 129 | switch (mode) {
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| 130 | case 0:
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| 131 | case 1:
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| 132 | case 2:
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| 133 | case 3:
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| 134 | // Do Nothing
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| 135 | break;
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| 136 | default:
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| 137 | error("SPI format error");
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| 138 | return;
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| 139 | }
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| 140 |
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| 141 | switch (bits) {
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| 142 | case 8:
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| 143 | DSS = 0x7;
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| 144 | splw = 0x20;
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| 145 | break;
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| 146 | case 16:
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| 147 | DSS = 0xf;
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| 148 | splw = 0x40;
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| 149 | break;
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| 150 | case 32:
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| 151 | DSS = 0x2;
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| 152 | splw = 0x60;
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| 153 | break;
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| 154 | default:
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| 155 | error("SPI module don't support other than 8/16/32bits");
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| 156 | return;
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| 157 | }
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| 158 | tmp |= phase;
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| 159 | tmp |= (polarity << 1);
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| 160 | tmp |= (DSS << 8);
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| 161 | obj->spi.bits = bits;
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| 162 |
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| 163 | spi_disable(obj);
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| 164 | wk_spcmd0 = obj->spi.spi->SPCMD0;
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| 165 | wk_spcmd0 &= ~mask;
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| 166 | wk_spcmd0 |= (mask & tmp);
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| 167 | obj->spi.spi->SPCMD0 = wk_spcmd0;
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| 168 | obj->spi.spi->SPDCR = splw;
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| 169 | if (slave) {
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| 170 | obj->spi.spi->SPCR &=~(1 << 3); // MSTR to 0
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| 171 | } else {
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| 172 | obj->spi.spi->SPCR |= (1 << 3); // MSTR to 1
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| 173 | }
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| 174 | spi_enable(obj);
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| 175 | }
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| 176 |
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| 177 | void spi_frequency(spi_t *obj, int hz) {
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| 178 | uint32_t pclk_base;
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| 179 | uint32_t div;
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| 180 | uint32_t brdv = 0;
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| 181 | uint32_t hz_max;
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| 182 | uint32_t hz_min;
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| 183 | uint16_t mask = 0x000c;
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| 184 | uint16_t wk_spcmd0;
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| 185 |
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| 186 | /* set PCLK */
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| 187 | if (RZ_A1_IsClockMode0() == false) {
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| 188 | pclk_base = CM1_RENESAS_RZ_A1_P1_CLK;
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| 189 | } else {
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| 190 | pclk_base = CM0_RENESAS_RZ_A1_P1_CLK;
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| 191 | }
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| 192 |
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| 193 | hz_min = pclk_base / 2 / 256 / 8;
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| 194 | hz_max = pclk_base / 2;
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| 195 | if ((hz < hz_min) || (hz > hz_max)) {
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| 196 | error("Couldn't setup requested SPI frequency");
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| 197 | return;
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| 198 | }
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| 199 |
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| 200 | div = (pclk_base / hz / 2);
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| 201 | while (div > 256) {
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| 202 | div >>= 1;
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| 203 | brdv++;
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| 204 | }
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| 205 | div -= 1;
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| 206 | brdv = (brdv << 2);
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| 207 |
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| 208 | spi_disable(obj);
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| 209 | obj->spi.spi->SPBR = div;
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| 210 | wk_spcmd0 = obj->spi.spi->SPCMD0;
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| 211 | wk_spcmd0 &= ~mask;
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| 212 | wk_spcmd0 |= (mask & brdv);
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| 213 | obj->spi.spi->SPCMD0 = wk_spcmd0;
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| 214 | spi_enable(obj);
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| 215 | }
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| 216 |
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| 217 | static inline void spi_disable(spi_t *obj) {
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| 218 | obj->spi.spi->SPCR &= ~(1 << 6); // SPE to 0
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| 219 | }
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| 220 |
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| 221 | static inline void spi_enable(spi_t *obj) {
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| 222 | obj->spi.spi->SPCR |= (1 << 6); // SPE to 1
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| 223 | }
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| 224 |
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| 225 | static inline int spi_readable(spi_t *obj) {
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| 226 | return obj->spi.spi->SPSR & (1 << 7); // SPRF
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| 227 | }
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| 228 |
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| 229 | static inline int spi_tend(spi_t *obj) {
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| 230 | return obj->spi.spi->SPSR & (1 << 6); // TEND
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| 231 | }
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| 232 |
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| 233 | static inline void spi_write(spi_t *obj, int value) {
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| 234 | if (obj->spi.bits == 8) {
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| 235 | obj->spi.spi->SPDR.UINT8[0] = (uint8_t)value;
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| 236 | } else if (obj->spi.bits == 16) {
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| 237 | obj->spi.spi->SPDR.UINT16[0] = (uint16_t)value;
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| 238 | } else {
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| 239 | obj->spi.spi->SPDR.UINT32 = (uint32_t)value;
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| 240 | }
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| 241 | }
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| 242 |
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| 243 | static inline int spi_read(spi_t *obj) {
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| 244 | int read_data;
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| 245 |
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| 246 | if (obj->spi.bits == 8) {
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| 247 | read_data = obj->spi.spi->SPDR.UINT8[0];
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| 248 | } else if (obj->spi.bits == 16) {
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| 249 | read_data = obj->spi.spi->SPDR.UINT16[0];
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| 250 | } else {
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| 251 | read_data = obj->spi.spi->SPDR.UINT32;
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| 252 | }
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| 253 |
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| 254 | return read_data;
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| 255 | }
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| 256 |
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| 257 | int spi_master_write(spi_t *obj, int value) {
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| 258 | spi_write(obj, value);
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| 259 | while(!spi_tend(obj));
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| 260 | return spi_read(obj);
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| 261 | }
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| 262 |
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[364] | 263 | int spi_master_block_write(spi_t *obj, const char *tx_buffer, int tx_length,
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| 264 | char *rx_buffer, int rx_length, char write_fill) {
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| 265 | int total = (tx_length > rx_length) ? tx_length : rx_length;
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| 266 |
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| 267 | for (int i = 0; i < total; i++) {
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| 268 | char out = (i < tx_length) ? tx_buffer[i] : write_fill;
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| 269 | char in = spi_master_write(obj, out);
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| 270 | if (i < rx_length) {
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| 271 | rx_buffer[i] = in;
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| 272 | }
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| 273 | }
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| 274 |
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| 275 | return total;
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| 276 | }
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| 277 |
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[352] | 278 | int spi_slave_receive(spi_t *obj) {
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| 279 | return (spi_readable(obj) && !spi_busy(obj)) ? (1) : (0);
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| 280 | }
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| 281 |
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| 282 | int spi_slave_read(spi_t *obj) {
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| 283 | return spi_read(obj);
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| 284 | }
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| 285 |
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| 286 | void spi_slave_write(spi_t *obj, int value) {
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| 287 | spi_write(obj, value);
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| 288 | }
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| 289 |
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| 290 | int spi_busy(spi_t *obj) {
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| 291 | return 0;
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| 292 | }
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| 293 |
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| 294 | #if DEVICE_SPI_ASYNCH
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| 295 |
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| 296 | #define IRQ_NUM 2
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| 297 |
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| 298 | static void spi_irqs_set(spi_t *obj, uint32_t enable);
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| 299 | static void spi_async_write(spi_t *obj);
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| 300 | static void spi_async_read(spi_t *obj);
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| 301 |
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| 302 | static void spi0_rx_irq(void);
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| 303 | static void spi1_rx_irq(void);
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| 304 | static void spi2_rx_irq(void);
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| 305 | static void spi3_rx_irq(void);
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| 306 | static void spi4_rx_irq(void);
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| 307 | static void spi0_er_irq(void);
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| 308 | static void spi1_er_irq(void);
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| 309 | static void spi2_er_irq(void);
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| 310 | static void spi3_er_irq(void);
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| 311 | static void spi4_er_irq(void);
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| 312 |
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| 313 | static const IRQn_Type irq_set_tbl[RSPI_COUNT][IRQ_NUM] = {
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| 314 | {RSPISPRI0_IRQn, RSPISPEI0_IRQn},
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| 315 | {RSPISPRI1_IRQn, RSPISPEI1_IRQn},
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| 316 | {RSPISPRI2_IRQn, RSPISPEI2_IRQn},
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| 317 | {RSPISPRI3_IRQn, RSPISPEI3_IRQn},
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| 318 | {RSPISPRI4_IRQn, RSPISPEI4_IRQn}
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| 319 | };
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| 320 |
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| 321 | static const IRQHandler hander_set_tbl[RSPI_COUNT][IRQ_NUM] = {
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| 322 | {spi0_rx_irq, spi0_er_irq},
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| 323 | {spi1_rx_irq, spi1_er_irq},
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| 324 | {spi2_rx_irq, spi2_er_irq},
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| 325 | {spi3_rx_irq, spi3_er_irq},
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| 326 | {spi4_rx_irq, spi4_er_irq}
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| 327 | };
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| 328 |
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| 329 | struct spi_global_data_s {
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| 330 | spi_t *async_obj;
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| 331 | uint32_t async_callback, event, wanted_events;
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| 332 | };
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| 333 |
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| 334 | static struct spi_global_data_s spi_data[RSPI_COUNT];
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| 335 |
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| 336 | static void spi_rx_irq(IRQn_Type irq_num, uint32_t index)
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| 337 | {
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| 338 | spi_t *obj = spi_data[index].async_obj;
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| 339 | if (obj->rx_buff.buffer && obj->rx_buff.pos < obj->rx_buff.length) {
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| 340 | spi_async_read(obj);
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| 341 | } else {
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| 342 | if (obj->rx_buff.buffer && obj->tx_buff.buffer && obj->tx_buff.pos < obj->tx_buff.length) {
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| 343 | spi_data[obj->spi.index].event = SPI_EVENT_INTERNAL_TRANSFER_COMPLETE;
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| 344 | if (spi_data[obj->spi.index].wanted_events & SPI_EVENT_COMPLETE) {
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| 345 | spi_data[obj->spi.index].event |= SPI_EVENT_COMPLETE;
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| 346 | }
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| 347 | spi_irqs_set(obj, 0);
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| 348 | spi_data[obj->spi.index].async_obj = NULL;
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| 349 | ((void (*)())spi_data[obj->spi.index].async_callback)();
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| 350 | return;
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| 351 | }
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| 352 | spi_read(obj);
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| 353 | }
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| 354 | if (obj->tx_buff.buffer) {
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| 355 | if (obj->tx_buff.pos == obj->tx_buff.length) {
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| 356 | spi_data[obj->spi.index].event = SPI_EVENT_INTERNAL_TRANSFER_COMPLETE;
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| 357 | if (spi_data[obj->spi.index].wanted_events & SPI_EVENT_COMPLETE) {
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| 358 | spi_data[obj->spi.index].event |= SPI_EVENT_COMPLETE;
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| 359 | }
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| 360 | spi_irqs_set(obj, 0);
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| 361 | spi_data[obj->spi.index].async_obj = NULL;
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| 362 | ((void (*)())spi_data[obj->spi.index].async_callback)();
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| 363 | } else {
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| 364 | spi_async_write(obj);
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| 365 | }
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| 366 | } else {
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| 367 | if (obj->rx_buff.pos == obj->rx_buff.length) {
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| 368 | spi_data[obj->spi.index].event = SPI_EVENT_INTERNAL_TRANSFER_COMPLETE;
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| 369 | if (spi_data[obj->spi.index].wanted_events & SPI_EVENT_COMPLETE) {
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| 370 | spi_data[obj->spi.index].event |= SPI_EVENT_COMPLETE;
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| 371 | }
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| 372 | spi_irqs_set(obj, 0);
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| 373 | spi_data[obj->spi.index].async_obj = NULL;
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| 374 | ((void (*)())spi_data[obj->spi.index].async_callback)();
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| 375 | } else {
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| 376 | spi_async_write(obj);
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| 377 | }
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| 378 | }
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| 379 | }
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| 380 |
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| 381 | static void spi_err_irq(IRQn_Type irq_num, uint32_t index)
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| 382 | {
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| 383 | spi_t *obj = spi_data[index].async_obj;
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| 384 | spi_abort_asynch(obj);
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| 385 | spi_data[index].event = SPI_EVENT_ERROR;
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| 386 | if (spi_data[index].wanted_events & SPI_EVENT_ERROR) {
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| 387 | ((void (*)())spi_data[index].async_callback)();
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| 388 | }
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| 389 | }
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| 390 |
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| 391 | static void spi0_rx_irq(void)
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| 392 | {
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| 393 | spi_rx_irq(RSPISPRI0_IRQn, 0);
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| 394 | }
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| 395 |
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| 396 | static void spi1_rx_irq(void)
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| 397 | {
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| 398 | spi_rx_irq(RSPISPRI1_IRQn, 1);
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| 399 | }
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| 400 |
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| 401 | static void spi2_rx_irq(void)
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| 402 | {
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| 403 | spi_rx_irq(RSPISPRI2_IRQn, 2);
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| 404 | }
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| 405 |
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| 406 | static void spi3_rx_irq(void)
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| 407 | {
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| 408 | spi_rx_irq(RSPISPRI3_IRQn, 3);
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| 409 | }
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| 410 |
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| 411 | static void spi4_rx_irq(void)
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| 412 | {
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| 413 | spi_rx_irq(RSPISPRI4_IRQn, 4);
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| 414 | }
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| 415 |
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| 416 | static void spi0_er_irq(void)
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| 417 | {
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| 418 | spi_err_irq(RSPISPEI0_IRQn, 0);
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| 419 | }
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| 420 |
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| 421 | static void spi1_er_irq(void)
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| 422 | {
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| 423 | spi_err_irq(RSPISPEI1_IRQn, 1);
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| 424 | }
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| 425 |
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| 426 | static void spi2_er_irq(void)
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| 427 | {
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| 428 | spi_err_irq(RSPISPEI2_IRQn, 2);
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| 429 | }
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| 430 |
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| 431 | static void spi3_er_irq(void)
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| 432 | {
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| 433 | spi_err_irq(RSPISPEI3_IRQn, 3);
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| 434 | }
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| 435 |
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| 436 | static void spi4_er_irq(void)
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| 437 | {
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| 438 | spi_err_irq(RSPISPEI4_IRQn, 4);
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| 439 | }
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| 440 |
|
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| 441 | static void spi_irqs_set(spi_t *obj, uint32_t enable)
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| 442 | {
|
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| 443 | int i;
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| 444 | const IRQn_Type *irqTable = irq_set_tbl[obj->spi.index];
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| 445 | const IRQHandler *handlerTable = hander_set_tbl[obj->spi.index];
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| 446 | for (i = 0; i < IRQ_NUM; ++i) {
|
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| 447 | if (enable) {
|
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| 448 | InterruptHandlerRegister(irqTable[i], handlerTable[i]);
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| 449 | GIC_SetPriority(irqTable[i], 5);
|
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| 450 | GIC_EnableIRQ(irqTable[i]);
|
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| 451 | } else {
|
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| 452 | GIC_DisableIRQ(irqTable[i]);
|
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| 453 | }
|
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| 454 | }
|
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| 455 | if (enable) {
|
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| 456 | obj->spi.spi->SPCR |= (1 << 4) | (1 << 7);
|
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| 457 | } else {
|
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| 458 | obj->spi.spi->SPCR &= ~((1 << 4) | (1 << 7));
|
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| 459 | }
|
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| 460 | }
|
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| 461 |
|
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| 462 | static void spi_async_write(spi_t *obj)
|
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| 463 | {
|
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| 464 | uint8_t **width8;
|
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| 465 | uint16_t **width16;
|
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| 466 | uint32_t **width32;
|
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| 467 |
|
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| 468 | if (obj->tx_buff.buffer) {
|
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| 469 | switch (obj->tx_buff.width) {
|
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| 470 | case 8:
|
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| 471 | width8 = (uint8_t **)&obj->tx_buff.buffer;
|
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| 472 | spi_write(obj, **width8);
|
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| 473 | ++*width8;
|
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| 474 | obj->tx_buff.pos += sizeof(uint8_t);
|
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| 475 | break;
|
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| 476 |
|
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| 477 | case 16:
|
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| 478 | width16 = (uint16_t **)&obj->tx_buff.buffer;
|
---|
| 479 | spi_write(obj, **width16);
|
---|
| 480 | ++*width16;
|
---|
| 481 | obj->tx_buff.pos += sizeof(uint16_t);
|
---|
| 482 | break;
|
---|
| 483 |
|
---|
| 484 | case 32:
|
---|
| 485 | width32 = (uint32_t **)&obj->tx_buff.buffer;
|
---|
| 486 | spi_write(obj, **width32);
|
---|
| 487 | ++*width32;
|
---|
| 488 | obj->tx_buff.pos += sizeof(uint32_t);
|
---|
| 489 | break;
|
---|
| 490 |
|
---|
| 491 | default:
|
---|
| 492 | MBED_ASSERT(0);
|
---|
| 493 | break;
|
---|
| 494 | }
|
---|
| 495 | } else {
|
---|
| 496 | spi_write(obj, SPI_FILL_WORD);
|
---|
| 497 | }
|
---|
| 498 | }
|
---|
| 499 |
|
---|
| 500 | static void spi_async_read(spi_t *obj)
|
---|
| 501 | {
|
---|
| 502 | uint8_t **width8;
|
---|
| 503 | uint16_t **width16;
|
---|
| 504 | uint32_t **width32;
|
---|
| 505 |
|
---|
| 506 | switch (obj->rx_buff.width) {
|
---|
| 507 | case 8:
|
---|
| 508 | width8 = (uint8_t **)&obj->rx_buff.buffer;
|
---|
| 509 | **width8 = spi_read(obj);
|
---|
| 510 | ++*width8;
|
---|
| 511 | obj->rx_buff.pos += sizeof(uint8_t);
|
---|
| 512 | break;
|
---|
| 513 |
|
---|
| 514 | case 16:
|
---|
| 515 | width16 = (uint16_t **)&obj->rx_buff.buffer;
|
---|
| 516 | **width16 = spi_read(obj);
|
---|
| 517 | ++*width16;
|
---|
| 518 | obj->rx_buff.pos += sizeof(uint16_t);
|
---|
| 519 | break;
|
---|
| 520 |
|
---|
| 521 | case 32:
|
---|
| 522 | width32 = (uint32_t **)&obj->rx_buff.buffer;
|
---|
| 523 | **width32 = spi_read(obj);
|
---|
| 524 | ++*width32;
|
---|
| 525 | obj->rx_buff.pos += sizeof(uint32_t);
|
---|
| 526 | break;
|
---|
| 527 |
|
---|
| 528 | default:
|
---|
| 529 | MBED_ASSERT(0);
|
---|
| 530 | break;
|
---|
| 531 | }
|
---|
| 532 | }
|
---|
| 533 |
|
---|
| 534 | /******************************************************************************
|
---|
| 535 | * ASYNCHRONOUS HAL
|
---|
| 536 | ******************************************************************************/
|
---|
| 537 |
|
---|
| 538 | void spi_master_transfer(spi_t *obj, const void *tx, size_t tx_length, void *rx, size_t rx_length, uint8_t bit_width, uint32_t handler, uint32_t event, DMAUsage hint)
|
---|
| 539 | {
|
---|
| 540 | int i;
|
---|
| 541 | MBED_ASSERT(obj);
|
---|
| 542 | MBED_ASSERT(tx || rx);
|
---|
| 543 | MBED_ASSERT(tx && ! rx ? tx_length : 1);
|
---|
| 544 | MBED_ASSERT(rx && ! tx ? rx_length : 1);
|
---|
| 545 | MBED_ASSERT(obj->spi.spi->SPCR & (1 << 3)); /* Slave mode */
|
---|
| 546 | MBED_ASSERT(bit_width == 8 || bit_width == 16 || bit_width == 32);
|
---|
| 547 |
|
---|
| 548 | if (tx_length) {
|
---|
| 549 | obj->tx_buff.buffer = (void *)tx;
|
---|
| 550 | } else {
|
---|
| 551 | obj->tx_buff.buffer = NULL;
|
---|
| 552 | }
|
---|
| 553 | obj->tx_buff.length = tx_length * bit_width / 8;
|
---|
| 554 | obj->tx_buff.pos = 0;
|
---|
| 555 | obj->tx_buff.width = bit_width;
|
---|
| 556 | if (rx_length) {
|
---|
| 557 | obj->rx_buff.buffer = rx;
|
---|
| 558 | } else {
|
---|
| 559 | obj->rx_buff.buffer = NULL;
|
---|
| 560 | }
|
---|
| 561 | obj->rx_buff.length = rx_length * bit_width / 8;
|
---|
| 562 | obj->rx_buff.pos = 0;
|
---|
| 563 | obj->rx_buff.width = bit_width;
|
---|
| 564 | for (i = 0; i < obj->rx_buff.length; i++) {
|
---|
| 565 | ((uint8_t *)obj->rx_buff.buffer)[i] = SPI_FILL_WORD;
|
---|
| 566 | }
|
---|
| 567 |
|
---|
| 568 | spi_data[obj->spi.index].async_callback = handler;
|
---|
| 569 | spi_data[obj->spi.index].async_obj = obj;
|
---|
| 570 | spi_data[obj->spi.index].event = 0;
|
---|
| 571 | spi_data[obj->spi.index].wanted_events = event;
|
---|
| 572 |
|
---|
| 573 | spi_irqs_set(obj, 1);
|
---|
| 574 |
|
---|
| 575 | spi_async_write(obj);
|
---|
| 576 | }
|
---|
| 577 |
|
---|
| 578 | uint32_t spi_irq_handler_asynch(spi_t *obj)
|
---|
| 579 | {
|
---|
| 580 | return spi_data[obj->spi.index].event;
|
---|
| 581 | }
|
---|
| 582 |
|
---|
| 583 | uint8_t spi_active(spi_t *obj)
|
---|
| 584 | {
|
---|
| 585 | return spi_data[obj->spi.index].async_obj != NULL;
|
---|
| 586 | }
|
---|
| 587 |
|
---|
| 588 | void spi_abort_asynch(spi_t *obj)
|
---|
| 589 | {
|
---|
| 590 | spi_disable(obj);
|
---|
| 591 | spi_irqs_set(obj, 0);
|
---|
| 592 | spi_data[obj->spi.index].async_obj = NULL;
|
---|
| 593 | spi_enable(obj);
|
---|
| 594 | }
|
---|
| 595 |
|
---|
| 596 | #endif
|
---|