source: asp3_tinet_ecnl_arm/trunk/asp3_dcre/mbed/targets/TARGET_RENESAS/TARGET_RZ_A1H/pwmout_api.c@ 352

Last change on this file since 352 was 352, checked in by coas-nagasima, 6 years ago

arm向けASP3版ECNLを追加
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1/* mbed Microcontroller Library
2 * Copyright (c) 2006-2013 ARM Limited
3 *
4 * Licensed under the Apache License, Version 2.0 (the "License");
5 * you may not use this file except in compliance with the License.
6 * You may obtain a copy of the License at
7 *
8 * http://www.apache.org/licenses/LICENSE-2.0
9 *
10 * Unless required by applicable law or agreed to in writing, software
11 * distributed under the License is distributed on an "AS IS" BASIS,
12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
13 * See the License for the specific language governing permissions and
14 * limitations under the License.
15 */
16#include "mbed_assert.h"
17#include "pwmout_api.h"
18#include "cmsis.h"
19#include "pinmap.h"
20#include "RZ_A1_Init.h"
21#include "cpg_iodefine.h"
22#include "pwm_iodefine.h"
23#include "gpio_addrdefine.h"
24
25#define MTU2_PWM_NUM 22
26#define MTU2_PWM_SIGNAL 2
27#define MTU2_PWM_OFFSET 0x20
28
29// PORT ID, PWM ID, Pin function
30static const PinMap PinMap_PWM[] = {
31 {P2_1 , MTU2_PWM0_PIN , 6},
32 {P2_11 , MTU2_PWM1_PIN , 5},
33 {P3_8 , MTU2_PWM2_PIN , 6},
34 {P3_10 , MTU2_PWM3_PIN , 6},
35 {P4_0 , MTU2_PWM4_PIN , 2},
36 {P4_4 , MTU2_PWM5_PIN , 3},
37 {P4_6 , MTU2_PWM6_PIN , 3},
38 {P5_0 , MTU2_PWM7_PIN , 6},
39 {P5_3 , MTU2_PWM8_PIN , 6},
40 {P5_5 , MTU2_PWM9_PIN , 6},
41 {P7_2 , MTU2_PWM10_PIN , 7},
42 {P7_4 , MTU2_PWM11_PIN , 7},
43 {P7_6 , MTU2_PWM12_PIN , 7},
44 {P7_10 , MTU2_PWM13_PIN , 7},
45 {P7_12 , MTU2_PWM14_PIN , 7},
46 {P7_14 , MTU2_PWM15_PIN , 7},
47 {P8_8 , MTU2_PWM16_PIN , 5},
48 {P8_10 , MTU2_PWM17_PIN , 4},
49 {P8_12 , MTU2_PWM18_PIN , 4},
50 {P8_14 , MTU2_PWM19_PIN , 4},
51 {P11_0 , MTU2_PWM20_PIN , 2},
52 {P11_2 , MTU2_PWM21_PIN , 2},
53 {P4_4 , PWM0_PIN , 4},
54 {P3_2 , PWM1_PIN , 7},
55 {P4_6 , PWM2_PIN , 4},
56 {P4_7 , PWM3_PIN , 4},
57 {P8_14 , PWM4_PIN , 6},
58 {P8_15 , PWM5_PIN , 6},
59 {P8_13 , PWM6_PIN , 6},
60 {P8_11 , PWM7_PIN , 6},
61 {P8_8 , PWM8_PIN , 6},
62 {P10_0 , PWM9_PIN , 3},
63 {P8_12 , PWM10_PIN , 6},
64 {P8_9 , PWM11_PIN , 6},
65 {P8_10 , PWM12_PIN , 6},
66 {P4_5 , PWM13_PIN , 4},
67 {NC , NC , 0}
68};
69
70static const PWMType PORT[] = {
71 PWM2E, // PWM0_PIN
72 PWM2C, // PWM1_PIN
73 PWM2G, // PWM2_PIN
74 PWM2H, // PWM3_PIN
75 PWM1G, // PWM4_PIN
76 PWM1H, // PWM5_PIN
77 PWM1F, // PWM6_PIN
78 PWM1D, // PWM7_PIN
79 PWM1A, // PWM8_PIN
80 PWM2A, // PWM9_PIN
81 PWM1E, // PWM10_PIN
82 PWM1B, // PWM11_PIN
83 PWM1C, // PWM12_PIN
84 PWM2F, // PWM13_PIN
85};
86
87static const MTU2_PWMType MTU2_PORT[] = {
88 TIOC2A, // MTU2_PWM0_PIN
89 TIOC1A, // MTU2_PWM1_PIN
90 TIOC4A, // MTU2_PWM2_PIN
91 TIOC4C, // MTU2_PWM3_PIN
92 TIOC0A, // MTU2_PWM4_PIN
93 TIOC4A, // MTU2_PWM5_PIN
94 TIOC4C, // MTU2_PWM6_PIN
95 TIOC0A, // MTU2_PWM7_PIN
96 TIOC3C, // MTU2_PWM8_PIN
97 TIOC0C, // MTU2_PWM9_PIN
98 TIOC0C, // MTU2_PWM10_PIN
99 TIOC1A, // MTU2_PWM11_PIN
100 TIOC2A, // MTU2_PWM12_PIN
101 TIOC3C, // MTU2_PWM13_PIN
102 TIOC4A, // MTU2_PWM14_PIN
103 TIOC4C, // MTU2_PWM15_PIN
104 TIOC1A, // MTU2_PWM16_PIN
105 TIOC3A, // MTU2_PWM17_PIN
106 TIOC3C, // MTU2_PWM18_PIN
107 TIOC2A, // MTU2_PWM19_PIN
108 TIOC4A, // MTU2_PWM20_PIN
109 TIOC4C, // MTU2_PWM21_PIN
110};
111
112static __IO uint16_t *PWM_MATCH[] = {
113 &PWMPWBFR_2E, // PWM0_PIN
114 &PWMPWBFR_2C, // PWM1_PIN
115 &PWMPWBFR_2G, // PWM2_PIN
116 &PWMPWBFR_2G, // PWM3_PIN
117 &PWMPWBFR_1G, // PWM4_PIN
118 &PWMPWBFR_1G, // PWM5_PIN
119 &PWMPWBFR_1E, // PWM6_PIN
120 &PWMPWBFR_1C, // PWM7_PIN
121 &PWMPWBFR_1A, // PWM8_PIN
122 &PWMPWBFR_2A, // PWM9_PIN
123 &PWMPWBFR_1E, // PWM10_PIN
124 &PWMPWBFR_1A, // PWM11_PIN
125 &PWMPWBFR_1C, // PWM12_PIN
126 &PWMPWBFR_2E, // PWM13_PIN
127};
128
129static __IO uint16_t *MTU2_PWM_MATCH[MTU2_PWM_NUM][MTU2_PWM_SIGNAL] = {
130 { &MTU2TGRA_2, &MTU2TGRB_2 }, // MTU2_PWM0_PIN
131 { &MTU2TGRA_1, &MTU2TGRB_1 }, // MTU2_PWM1_PIN
132 { &MTU2TGRA_4, &MTU2TGRB_4 }, // MTU2_PWM2_PIN
133 { &MTU2TGRC_4, &MTU2TGRD_4 }, // MTU2_PWM3_PIN
134 { &MTU2TGRA_0, &MTU2TGRB_0 }, // MTU2_PWM4_PIN
135 { &MTU2TGRA_4, &MTU2TGRB_4 }, // MTU2_PWM5_PIN
136 { &MTU2TGRC_4, &MTU2TGRD_4 }, // MTU2_PWM6_PIN
137 { &MTU2TGRA_0, &MTU2TGRB_0 }, // MTU2_PWM7_PIN
138 { &MTU2TGRC_3, &MTU2TGRD_3 }, // MTU2_PWM8_PIN
139 { &MTU2TGRC_0, &MTU2TGRD_0 }, // MTU2_PWM9_PIN
140 { &MTU2TGRC_0, &MTU2TGRD_0 }, // MTU2_PWM10_PIN
141 { &MTU2TGRA_1, &MTU2TGRB_1 }, // MTU2_PWM11_PIN
142 { &MTU2TGRA_2, &MTU2TGRB_2 }, // MTU2_PWM12_PIN
143 { &MTU2TGRC_3, &MTU2TGRD_3 }, // MTU2_PWM13_PIN
144 { &MTU2TGRA_4, &MTU2TGRB_4 }, // MTU2_PWM14_PIN
145 { &MTU2TGRC_4, &MTU2TGRD_4 }, // MTU2_PWM15_PIN
146 { &MTU2TGRA_1, &MTU2TGRB_1 }, // MTU2_PWM16_PIN
147 { &MTU2TGRA_3, &MTU2TGRB_3 }, // MTU2_PWM17_PIN
148 { &MTU2TGRC_3, &MTU2TGRD_3 }, // MTU2_PWM18_PIN
149 { &MTU2TGRA_2, &MTU2TGRB_2 }, // MTU2_PWM19_PIN
150 { &MTU2TGRA_4, &MTU2TGRB_4 }, // MTU2_PWM20_PIN
151 { &MTU2TGRC_4, &MTU2TGRD_4 } // MTU2_PWM21_PIN
152};
153
154static __IO uint8_t *TCR_MATCH[] = {
155 &MTU2TCR_0,
156 &MTU2TCR_1,
157 &MTU2TCR_2,
158 &MTU2TCR_3,
159 &MTU2TCR_4,
160};
161
162static __IO uint8_t *TIORH_MATCH[] = {
163 &MTU2TIORH_0,
164 &MTU2TIOR_1,
165 &MTU2TIOR_2,
166 &MTU2TIORH_3,
167 &MTU2TIORH_4,
168};
169
170static __IO uint8_t *TIORL_MATCH[] = {
171 &MTU2TIORL_0,
172 NULL,
173 NULL,
174 &MTU2TIORL_3,
175 &MTU2TIORL_4,
176};
177
178static __IO uint16_t *TGRA_MATCH[] = {
179 &MTU2TGRA_0,
180 &MTU2TGRA_1,
181 &MTU2TGRA_2,
182 &MTU2TGRA_3,
183 &MTU2TGRA_4,
184};
185
186static __IO uint16_t *TGRC_MATCH[] = {
187 &MTU2TGRC_0,
188 NULL,
189 NULL,
190 &MTU2TGRC_3,
191 &MTU2TGRC_4,
192};
193
194static __IO uint8_t *TMDR_MATCH[] = {
195 &MTU2TMDR_0,
196 &MTU2TMDR_1,
197 &MTU2TMDR_2,
198 &MTU2TMDR_3,
199 &MTU2TMDR_4,
200};
201
202static int MAX_PERIOD[] = {
203 125000,
204 503000,
205 2000000,
206 2000000,
207 2000000,
208};
209
210typedef enum {
211 MTU2_PULSE = 0,
212 MTU2_PERIOD
213} MTU2Signal;
214
215static uint16_t init_period_ch1 = 0;
216static uint16_t init_period_ch2 = 0;
217static uint16_t init_mtu2_period_ch[5] = {0};
218static int32_t period_ch1 = 1;
219static int32_t period_ch2 = 1;
220static int32_t mtu2_period_ch[5] = {1, 1, 1, 1, 1};
221
222void pwmout_init(pwmout_t* obj, PinName pin) {
223 // determine the channel
224 PWMName pwm = (PWMName)pinmap_peripheral(pin, PinMap_PWM);
225 MBED_ASSERT(pwm != (PWMName)NC);
226
227 if (pwm >= MTU2_PWM_OFFSET) {
228 /* PWM by MTU2 */
229 int tmp_pwm;
230
231 // power on
232 CPGSTBCR3 &= ~(CPG_STBCR3_BIT_MSTP33);
233
234 obj->pwm = pwm;
235 tmp_pwm = (int)(obj->pwm - MTU2_PWM_OFFSET);
236 if (((uint32_t)MTU2_PORT[tmp_pwm] & 0x00000040) == 0x00000040) {
237 obj->ch = 4;
238 MTU2TOER |= 0x36;
239 } else if (((uint32_t)MTU2_PORT[tmp_pwm] & 0x00000030) == 0x00000030) {
240 obj->ch = 3;
241 MTU2TOER |= 0x09;
242 } else if (((uint32_t)MTU2_PORT[tmp_pwm] & 0x00000020) == 0x00000020) {
243 obj->ch = 2;
244 } else if (((uint32_t)MTU2_PORT[tmp_pwm] & 0x00000010) == 0x00000010) {
245 obj->ch = 1;
246 } else {
247 obj->ch = 0;
248 }
249 // Wire pinout
250 pinmap_pinout(pin, PinMap_PWM);
251
252 int bitmask = 1 << (pin & 0xf);
253
254 *PMSR(PINGROUP(pin)) = (bitmask << 16) | 0;
255
256 // default duty 0.0f
257 pwmout_write(obj, 0);
258 if (init_mtu2_period_ch[obj->ch] == 0) {
259 // default period 1ms
260 pwmout_period_us(obj, 1000);
261 init_mtu2_period_ch[obj->ch] = 1;
262 }
263 } else {
264 /* PWM */
265 // power on
266 CPGSTBCR3 &= ~(CPG_STBCR3_BIT_MSTP30);
267
268 obj->pwm = pwm;
269 if (((uint32_t)PORT[obj->pwm] & 0x00000010) == 0x00000010) {
270 obj->ch = 2;
271 PWMPWPR_2_BYTE_L = 0x00;
272 } else {
273 obj->ch = 1;
274 PWMPWPR_1_BYTE_L = 0x00;
275 }
276
277 // Wire pinout
278 pinmap_pinout(pin, PinMap_PWM);
279
280 // default to 491us: standard for servos, and fine for e.g. brightness control
281 pwmout_write(obj, 0);
282 if ((obj->ch == 2) && (init_period_ch2 == 0)) {
283 pwmout_period_us(obj, 491);
284 init_period_ch2 = 1;
285 }
286 if ((obj->ch == 1) && (init_period_ch1 == 0)) {
287 pwmout_period_us(obj, 491);
288 init_period_ch1 = 1;
289 }
290 }
291}
292
293void pwmout_free(pwmout_t* obj) {
294 pwmout_write(obj, 0);
295}
296
297void pwmout_write(pwmout_t* obj, float value) {
298 uint32_t wk_cycle;
299 uint16_t v;
300
301 if (obj->pwm >= MTU2_PWM_OFFSET) {
302 /* PWM by MTU2 */
303 int tmp_pwm;
304
305 if (value < 0.0f) {
306 value = 0.0f;
307 } else if (value > 1.0f) {
308 value = 1.0f;
309 } else {
310 // Do Nothing
311 }
312 tmp_pwm = (int)(obj->pwm - MTU2_PWM_OFFSET);
313 wk_cycle = *MTU2_PWM_MATCH[tmp_pwm][MTU2_PERIOD] & 0xffff;
314 // set channel match to percentage
315 *MTU2_PWM_MATCH[tmp_pwm][MTU2_PULSE] = (uint16_t)((float)wk_cycle * value);
316 } else {
317 /* PWM */
318 if (value < 0.0f) {
319 value = 0.0f;
320 } else if (value > 1.0f) {
321 value = 1.0f;
322 } else {
323 // Do Nothing
324 }
325
326 if (obj->ch == 2) {
327 wk_cycle = PWMPWCYR_2 & 0x03ff;
328 } else {
329 wk_cycle = PWMPWCYR_1 & 0x03ff;
330 }
331
332 // set channel match to percentage
333 v = (uint16_t)((float)wk_cycle * value);
334 *PWM_MATCH[obj->pwm] = (v | ((PORT[obj->pwm] & 1) << 12));
335 }
336}
337
338float pwmout_read(pwmout_t* obj) {
339 uint32_t wk_cycle;
340 float value;
341
342 if (obj->pwm >= MTU2_PWM_OFFSET) {
343 /* PWM by MTU2 */
344 uint32_t wk_pulse;
345 int tmp_pwm;
346
347 tmp_pwm = (int)(obj->pwm - MTU2_PWM_OFFSET);
348 wk_cycle = *MTU2_PWM_MATCH[tmp_pwm][MTU2_PERIOD] & 0xffff;
349 wk_pulse = *MTU2_PWM_MATCH[tmp_pwm][MTU2_PULSE] & 0xffff;
350 value = ((float)wk_pulse / (float)wk_cycle);
351 } else {
352 /* PWM */
353 if (obj->ch == 2) {
354 wk_cycle = PWMPWCYR_2 & 0x03ff;
355 } else {
356 wk_cycle = PWMPWCYR_1 & 0x03ff;
357 }
358 value = ((float)(*PWM_MATCH[obj->pwm] & 0x03ff) / (float)wk_cycle);
359 }
360
361 return (value > 1.0f) ? (1.0f) : (value);
362}
363
364void pwmout_period(pwmout_t* obj, float seconds) {
365 pwmout_period_us(obj, seconds * 1000000.0f);
366}
367
368void pwmout_period_ms(pwmout_t* obj, int ms) {
369 pwmout_period_us(obj, ms * 1000);
370}
371
372static void set_duty_again(__IO uint16_t *p_pwmpbfr, uint16_t last_cycle, uint16_t new_cycle){
373 uint16_t wk_pwmpbfr;
374 float value;
375 uint16_t v;
376
377 wk_pwmpbfr = *p_pwmpbfr;
378 value = ((float)(wk_pwmpbfr & 0x03ff) / (float)last_cycle);
379 v = (uint16_t)((float)new_cycle * value);
380 *p_pwmpbfr = (v | (wk_pwmpbfr & 0x1000));
381}
382
383static void set_mtu2_duty_again(__IO uint16_t *p_pwmpbfr, uint16_t last_cycle, uint16_t new_cycle){
384 uint16_t wk_pwmpbfr;
385 float value;
386
387 wk_pwmpbfr = *p_pwmpbfr;
388 value = ((float)(wk_pwmpbfr & 0xffff) / (float)last_cycle);
389 *p_pwmpbfr = (uint16_t)((float)new_cycle * value);
390}
391
392// Set the PWM period, keeping the duty cycle the same.
393void pwmout_period_us(pwmout_t* obj, int us) {
394 uint64_t wk_cycle_mtu2;
395 uint32_t pclk_base;
396 uint32_t wk_cycle;
397 uint32_t wk_cks = 0;
398 uint16_t wk_last_cycle;
399 int max_us = 0;
400
401 if (obj->pwm >= MTU2_PWM_OFFSET) {
402 /* PWM by MTU2 */
403 int tmp_pwm;
404 uint8_t tmp_tcr_up;
405 uint8_t tmp_tstr_sp;
406 uint8_t tmp_tstr_st;
407
408 max_us = MAX_PERIOD[obj->ch];
409 if (us > max_us) {
410 us = max_us;
411 } else if (us < 1) {
412 us = 1;
413 } else {
414 // Do Nothing
415 }
416
417 if (RZ_A1_IsClockMode0() == false) {
418 pclk_base = (uint32_t)CM1_RENESAS_RZ_A1_P0_CLK;
419 } else {
420 pclk_base = (uint32_t)CM0_RENESAS_RZ_A1_P0_CLK;
421 }
422
423 wk_cycle_mtu2 = (uint64_t)pclk_base * us;
424 while (wk_cycle_mtu2 >= 65535000000) {
425 if ((obj->ch == 1) && (wk_cks == 3)) {
426 wk_cks+=2;
427 } else if ((obj->ch == 2) && (wk_cks == 3)) {
428 wk_cycle_mtu2 >>= 2;
429 wk_cks+=3;
430 }
431 wk_cycle_mtu2 >>= 2;
432 wk_cks++;
433 }
434 wk_cycle = (uint32_t)(wk_cycle_mtu2 / 1000000);
435
436 tmp_pwm = (int)(obj->pwm - MTU2_PWM_OFFSET);
437 if (((uint8_t)MTU2_PORT[tmp_pwm] & 0x02) == 0x02) {
438 tmp_tcr_up = 0xC0;
439 } else {
440 tmp_tcr_up = 0x40;
441 }
442 if ((obj->ch == 4) || (obj->ch == 3)) {
443 tmp_tstr_sp = ~(0x38 | (1 << (obj->ch + 3)));
444 tmp_tstr_st = (1 << (obj->ch + 3));
445 } else {
446 tmp_tstr_sp = ~(0x38 | (1 << obj->ch));
447 tmp_tstr_st = (1 << obj->ch);
448 }
449 // Counter Stop
450 MTU2TSTR &= tmp_tstr_sp;
451 wk_last_cycle = *MTU2_PWM_MATCH[tmp_pwm][MTU2_PERIOD] & 0xffff;
452 *TCR_MATCH[obj->ch] = tmp_tcr_up | wk_cks;
453 *TIORH_MATCH[obj->ch] = 0x21;
454 if ((obj->ch == 0) || (obj->ch == 3) || (obj->ch == 4)) {
455 *TIORL_MATCH[obj->ch] = 0x21;
456 }
457 *MTU2_PWM_MATCH[tmp_pwm][MTU2_PERIOD] = (uint16_t)wk_cycle; // Set period
458
459 // Set duty again(TGRA)
460 set_mtu2_duty_again(TGRA_MATCH[obj->ch], wk_last_cycle, wk_cycle);
461 if ((obj->ch == 0) || (obj->ch == 3) || (obj->ch == 4)) {
462 // Set duty again(TGRC)
463 set_mtu2_duty_again(TGRC_MATCH[obj->ch], wk_last_cycle, wk_cycle);
464 }
465 *TMDR_MATCH[obj->ch] = 0x02; // PWM mode 1
466
467 // Counter Start
468 MTU2TSTR |= tmp_tstr_st;
469 // Save for future use
470 mtu2_period_ch[obj->ch] = us;
471 } else {
472 /* PWM */
473 if (us > 491) {
474 us = 491;
475 } else if (us < 1) {
476 us = 1;
477 } else {
478 // Do Nothing
479 }
480
481 if (RZ_A1_IsClockMode0() == false) {
482 pclk_base = (uint32_t)CM1_RENESAS_RZ_A1_P0_CLK / 10000;
483 } else {
484 pclk_base = (uint32_t)CM0_RENESAS_RZ_A1_P0_CLK / 10000;
485 }
486
487 wk_cycle = pclk_base * us;
488 while (wk_cycle >= 102350) {
489 wk_cycle >>= 1;
490 wk_cks++;
491 }
492 wk_cycle = (wk_cycle + 50) / 100;
493
494 if (obj->ch == 2) {
495 wk_last_cycle = PWMPWCYR_2 & 0x03ff;
496 PWMPWCR_2_BYTE_L = 0xc0 | wk_cks;
497 PWMPWCYR_2 = (uint16_t)wk_cycle;
498
499 // Set duty again
500 set_duty_again(&PWMPWBFR_2A, wk_last_cycle, wk_cycle);
501 set_duty_again(&PWMPWBFR_2C, wk_last_cycle, wk_cycle);
502 set_duty_again(&PWMPWBFR_2E, wk_last_cycle, wk_cycle);
503 set_duty_again(&PWMPWBFR_2G, wk_last_cycle, wk_cycle);
504
505 // Counter Start
506 PWMPWCR_2_BYTE_L |= 0x08;
507
508 // Save for future use
509 period_ch2 = us;
510 } else {
511 wk_last_cycle = PWMPWCYR_1 & 0x03ff;
512 PWMPWCR_1_BYTE_L = 0xc0 | wk_cks;
513 PWMPWCYR_1 = (uint16_t)wk_cycle;
514
515 // Set duty again
516 set_duty_again(&PWMPWBFR_1A, wk_last_cycle, wk_cycle);
517 set_duty_again(&PWMPWBFR_1C, wk_last_cycle, wk_cycle);
518 set_duty_again(&PWMPWBFR_1E, wk_last_cycle, wk_cycle);
519 set_duty_again(&PWMPWBFR_1G, wk_last_cycle, wk_cycle);
520
521 // Counter Start
522 PWMPWCR_1_BYTE_L |= 0x08;
523
524 // Save for future use
525 period_ch1 = us;
526 }
527 }
528}
529
530void pwmout_pulsewidth(pwmout_t* obj, float seconds) {
531 pwmout_pulsewidth_us(obj, seconds * 1000000.0f);
532}
533
534void pwmout_pulsewidth_ms(pwmout_t* obj, int ms) {
535 pwmout_pulsewidth_us(obj, ms * 1000);
536}
537
538void pwmout_pulsewidth_us(pwmout_t* obj, int us) {
539 float value = 0;
540
541 if (obj->pwm >= MTU2_PWM_OFFSET) {
542 /* PWM by MTU2 */
543 if (mtu2_period_ch[obj->ch] != 0) {
544 value = (float)us / (float)mtu2_period_ch[obj->ch];
545 }
546 } else {
547 /* PWM */
548 if (obj->ch == 2) {
549 if (period_ch2 != 0) {
550 value = (float)us / (float)period_ch2;
551 }
552 } else {
553 if (period_ch1 != 0) {
554 value = (float)us / (float)period_ch1;
555 }
556 }
557 }
558 pwmout_write(obj, value);
559}
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