source: asp3_tinet_ecnl_arm/trunk/asp3_dcre/mbed/targets/TARGET_RENESAS/TARGET_RZ_A1H/i2c_api.c@ 352

Last change on this file since 352 was 352, checked in by coas-nagasima, 6 years ago

arm向けASP3版ECNLを追加
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1/* mbed Microcontroller Library
2 * Copyright (c) 2006-2013 ARM Limited
3 *
4 * Licensed under the Apache License, Version 2.0 (the "License");
5 * you may not use this file except in compliance with the License.
6 * You may obtain a copy of the License at
7 *
8 * http://www.apache.org/licenses/LICENSE-2.0
9 *
10 * Unless required by applicable law or agreed to in writing, software
11 * distributed under the License is distributed on an "AS IS" BASIS,
12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
13 * See the License for the specific language governing permissions and
14 * limitations under the License.
15 */
16#include "mbed_assert.h"
17#include "dma_api.h"
18#include "i2c_api.h"
19#include "cmsis.h"
20#include "pinmap.h"
21#include "r_typedefs.h"
22
23#include "riic_iodefine.h"
24#include "RZ_A1_Init.h"
25#include "MBRZA1H.h"
26
27volatile struct st_riic *RIIC[] = RIIC_ADDRESS_LIST;
28
29#define REG(N) \
30 RIIC[obj->i2c.i2c]->RIICn##N
31
32/* RIICnCR1 */
33#define CR1_RST (1 << 6)
34#define CR1_ICE (1 << 7)
35
36/* RIICnCR2 */
37#define CR2_ST (1 << 1)
38#define CR2_RS (1 << 2)
39#define CR2_SP (1 << 3)
40#define CR2_TRS (1 << 5)
41#define CR2_BBSY (1 << 7)
42
43/* RIICnMR3 */
44#define MR3_ACKBT (1 << 3)
45#define MR3_ACKWP (1 << 4)
46#define MR3_WAIT (1 << 6)
47
48/* RIICnSER */
49#define SER_SAR0E (1 << 0)
50
51/* RIICnSR1 */
52#define SR1_AAS0 (1 << 0)
53
54/* RIICnSR2 */
55#define SR2_START (1 << 2)
56#define SR2_STOP (1 << 3)
57#define SR2_NACKF (1 << 4)
58#define SR2_RDRF (1 << 5)
59#define SR2_TEND (1 << 6)
60#define SR2_TDRE (1 << 7)
61
62#define WAIT_TIMEOUT (3600000) /* Loop counter : Time-out is about 1s. By 3600000 loops, measured value is 969ms. */
63
64static const PinMap PinMap_I2C_SDA[] = {
65 {P1_1 , I2C_0, 1},
66 {P1_3 , I2C_1, 1},
67 {P1_7 , I2C_3, 1},
68 {NC , NC , 0}
69};
70
71static const PinMap PinMap_I2C_SCL[] = {
72 {P1_0 , I2C_0, 1},
73 {P1_2 , I2C_1, 1},
74 {P1_6 , I2C_3, 1},
75 {NC , NC, 0}
76};
77
78static inline int i2c_status(i2c_t *obj) {
79 return REG(SR2.UINT8[0]);
80}
81
82static void i2c_reg_reset(i2c_t *obj) {
83 /* full reset */
84 REG(CR1.UINT8[0]) &= ~CR1_ICE; // CR1.ICE off
85 REG(CR1.UINT8[0]) |= CR1_RST; // CR1.IICRST on
86 REG(CR1.UINT8[0]) |= CR1_ICE; // CR1.ICE on
87
88 REG(MR1.UINT8[0]) = 0x08; // P_phi /x 9bit (including Ack)
89 REG(SER.UINT8[0]) = 0x00; // no slave addr enabled
90
91 /* set frequency */
92 REG(MR1.UINT8[0]) |= obj->i2c.pclk_bit;
93 REG(BRL.UINT8[0]) = obj->i2c.width_low;
94 REG(BRH.UINT8[0]) = obj->i2c.width_hi;
95
96 REG(MR2.UINT8[0]) = 0x07;
97 REG(MR3.UINT8[0]) = 0x00;
98
99 REG(FER.UINT8[0]) = 0x72; // SCLE, NFE enabled, TMOT
100 REG(IER.UINT8[0]) = 0x00; // no interrupt
101
102 REG(CR1.UINT32) &= ~CR1_RST; // CR1.IICRST negate reset
103}
104
105static inline int i2c_wait_RDRF(i2c_t *obj) {
106 int timeout = 0;
107
108 /* There is no timeout, but the upper limit value is set to avoid an infinite loop. */
109 while ((i2c_status(obj) & SR2_RDRF) == 0) {
110 timeout ++;
111 if (timeout >= WAIT_TIMEOUT) {
112 return -1;
113 }
114 }
115
116 return 0;
117}
118
119static int i2c_wait_TDRE(i2c_t *obj) {
120 int timeout = 0;
121
122 /* There is no timeout, but the upper limit value is set to avoid an infinite loop. */
123 while ((i2c_status(obj) & SR2_TDRE) == 0) {
124 timeout ++;
125 if (timeout >= WAIT_TIMEOUT) {
126 return -1;
127 }
128 }
129
130 return 0;
131}
132
133static int i2c_wait_TEND(i2c_t *obj) {
134 int timeout = 0;
135
136 /* There is no timeout, but the upper limit value is set to avoid an infinite loop. */
137 while ((i2c_status(obj) & SR2_TEND) == 0) {
138 timeout ++;
139 if (timeout >= WAIT_TIMEOUT) {
140 return -1;
141 }
142 }
143
144 return 0;
145}
146
147
148static int i2c_wait_START(i2c_t *obj) {
149 int timeout = 0;
150
151 /* There is no timeout, but the upper limit value is set to avoid an infinite loop. */
152 while ((i2c_status(obj) & SR2_START) == 0) {
153 timeout ++;
154 if (timeout >= WAIT_TIMEOUT) {
155 return -1;
156 }
157 }
158
159 return 0;
160}
161
162static int i2c_wait_STOP(i2c_t *obj) {
163 int timeout = 0;
164
165 /* There is no timeout, but the upper limit value is set to avoid an infinite loop. */
166 while ((i2c_status(obj) & SR2_STOP) == 0) {
167 timeout ++;
168 if (timeout >= WAIT_TIMEOUT) {
169 return -1;
170 }
171 }
172
173 return 0;
174}
175
176static int i2c_set_STOP(i2c_t *obj) {
177 /* SR2.STOP = 0 */
178 REG(SR2.UINT32) &= ~SR2_STOP;
179 /* Stop condition */
180 REG(CR2.UINT32) |= CR2_SP;
181
182 return 0;
183}
184
185static void i2c_set_SR2_NACKF_STOP(i2c_t *obj) {
186 /* SR2.NACKF = 0 */
187 REG(SR2.UINT32) &= ~SR2_NACKF;
188 /* SR2.STOP = 0 */
189 REG(SR2.UINT32) &= ~SR2_STOP;
190}
191
192static void i2c_set_MR3_NACK(i2c_t *obj) {
193 /* send a NOT ACK */
194 REG(MR3.UINT32) |= MR3_ACKWP;
195 REG(MR3.UINT32) |= MR3_ACKBT;
196 REG(MR3.UINT32) &= ~MR3_ACKWP;
197}
198
199static void i2c_set_MR3_ACK(i2c_t *obj) {
200 /* send a ACK */
201 REG(MR3.UINT32) |= MR3_ACKWP;
202 REG(MR3.UINT32) &= ~MR3_ACKBT;
203 REG(MR3.UINT32) &= ~MR3_ACKWP;
204}
205
206static inline void i2c_power_enable(i2c_t *obj) {
207 volatile uint8_t dummy;
208 switch ((int)obj->i2c.i2c) {
209 case I2C_0:
210 CPGSTBCR9 &= ~(0x80);
211 break;
212 case I2C_1:
213 CPGSTBCR9 &= ~(0x40);
214 break;
215 case I2C_2:
216 CPGSTBCR9 &= ~(0x20);
217 break;
218 case I2C_3:
219 CPGSTBCR9 &= ~(0x10);
220 break;
221 }
222 dummy = CPGSTBCR9;
223}
224
225void i2c_init(i2c_t *obj, PinName sda, PinName scl) {
226 /* determine the I2C to use */
227 I2CName i2c_sda = (I2CName)pinmap_peripheral(sda, PinMap_I2C_SDA);
228 I2CName i2c_scl = (I2CName)pinmap_peripheral(scl, PinMap_I2C_SCL);
229 obj->i2c.i2c = pinmap_merge(i2c_sda, i2c_scl);
230 MBED_ASSERT((int)obj->i2c.i2c != NC);
231
232 /* enable power */
233 i2c_power_enable(obj);
234
235 /* set default frequency at 100k */
236 i2c_frequency(obj, 100000);
237
238 pinmap_pinout(sda, PinMap_I2C_SDA);
239 pinmap_pinout(scl, PinMap_I2C_SCL);
240
241 obj->i2c.last_stop_flag = 1;
242}
243
244inline int i2c_start(i2c_t *obj) {
245 int timeout = 0;
246
247 while ((REG(CR2.UINT32) & CR2_BBSY) != 0) {
248 timeout ++;
249 if (timeout >= obj->i2c.bbsy_wait_cnt) {
250 break;
251 }
252 }
253 /* Start Condition */
254 REG(CR2.UINT8[0]) |= CR2_ST;
255
256 return 0;
257}
258
259static inline int i2c_restart(i2c_t *obj) {
260 /* SR2.START = 0 */
261 REG(SR2.UINT32) &= ~SR2_START;
262 /* ReStart condition */
263 REG(CR2.UINT32) |= CR2_RS;
264
265 return 0;
266}
267
268inline int i2c_stop(i2c_t *obj) {
269 (void)i2c_set_STOP(obj);
270 (void)i2c_wait_STOP(obj);
271 i2c_set_SR2_NACKF_STOP(obj);
272
273 return 0;
274}
275
276static void i2c_set_err_noslave(i2c_t *obj) {
277 (void)i2c_set_STOP(obj);
278 (void)i2c_wait_STOP(obj);
279 i2c_set_SR2_NACKF_STOP(obj);
280 obj->i2c.last_stop_flag = 1;
281}
282
283static inline int i2c_do_write(i2c_t *obj, int value) {
284 int timeout = 0;
285
286 /* There is no timeout, but the upper limit value is set to avoid an infinite loop. */
287 while ((i2c_status(obj) & SR2_TDRE) == 0) {
288 timeout ++;
289 if (timeout >= WAIT_TIMEOUT) {
290 return -1;
291 }
292 }
293 /* write the data */
294 REG(DRT.UINT32) = value;
295
296 return 0;
297}
298
299static inline int i2c_read_address_write(i2c_t *obj, int value) {
300 int status;
301
302 status = i2c_wait_TDRE(obj);
303 if (status == 0) {
304 /* write the data */
305 REG(DRT.UINT32) = value;
306 }
307
308 return status;
309
310}
311
312static inline int i2c_do_read(i2c_t *obj, int last) {
313 if (last == 2) {
314 /* this time is befor last byte read */
315 /* Set MR3 WAIT bit is 1 */;
316 REG(MR3.UINT32) |= MR3_WAIT;
317 } else if (last == 1) {
318 i2c_set_MR3_NACK(obj);
319 } else {
320 i2c_set_MR3_ACK(obj);
321 }
322
323 /* return the data */
324 return (REG(DRR.UINT32) & 0xFF);
325}
326
327void i2c_frequency(i2c_t *obj, int hz) {
328 float64_t pclk_val;
329 float64_t wait_utime;
330 volatile float64_t bps;
331 volatile float64_t L_time; /* H Width period */
332 volatile float64_t H_time; /* L Width period */
333 uint32_t tmp_L_width;
334 uint32_t tmp_H_width;
335 uint32_t remainder;
336 uint32_t wk_cks = 0;
337
338 /* set PCLK */
339 if (false == RZ_A1_IsClockMode0()) {
340 pclk_val = (float64_t)CM1_RENESAS_RZ_A1_P0_CLK;
341 } else {
342 pclk_val = (float64_t)CM0_RENESAS_RZ_A1_P0_CLK;
343 }
344
345 /* Min 10kHz, Max 400kHz */
346 if (hz < 10000) {
347 bps = 10000;
348 } else if (hz > 400000) {
349 bps = 400000;
350 } else {
351 bps = (float64_t)hz;
352 }
353
354 /* Calculation L width time */
355 L_time = (1 / (2 * bps)); /* Harf period of frequency */
356 H_time = L_time;
357
358 /* Check I2C mode of Speed */
359 if (bps > 100000) {
360 /* Fast-mode */
361 L_time -= 102E-9; /* Falling time of SCL clock. */
362 H_time -= 138E-9; /* Rising time of SCL clock. */
363 /* Check L wideth */
364 if (L_time < 1.3E-6) {
365 /* Wnen L width less than 1.3us */
366 /* Subtract Rise up and down time for SCL from H/L width */
367 L_time = 1.3E-6;
368 H_time = (1 / bps) - L_time - 138E-9 - 102E-9;
369 }
370 }
371
372 tmp_L_width = (uint32_t)(L_time * pclk_val * 10);
373 tmp_L_width >>= 1;
374 wk_cks++;
375 while (tmp_L_width >= 341) {
376 tmp_L_width >>= 1;
377 wk_cks++;
378 }
379 remainder = tmp_L_width % 10;
380 tmp_L_width = ((tmp_L_width + 9) / 10) - 3; /* carry */
381
382 tmp_H_width = (uint32_t)(H_time * pclk_val * 10);
383 tmp_H_width >>= wk_cks;
384 if (remainder == 0) {
385 tmp_H_width = ((tmp_H_width + 9) / 10) - 3; /* carry */
386 } else {
387 remainder += tmp_H_width % 10;
388 tmp_H_width = (tmp_H_width / 10) - 3;
389 if (remainder > 10) {
390 tmp_H_width += 1; /* fine adjustment */
391 }
392 }
393 /* timeout of BBSY bit is minimum low width by frequency */
394 /* so timeout calculates "(low width) * 2" by frequency */
395 wait_utime = (L_time * 2) * 1000000;
396 /* 1 wait of BBSY bit is about 0.3us. if it's below 0.3us, wait count is set as 1. */
397 if (wait_utime <= 0.3) {
398 obj->i2c.bbsy_wait_cnt = 1;
399 } else {
400 obj->i2c.bbsy_wait_cnt = (int)(wait_utime / 0.3);
401 }
402
403
404 /* I2C Rate */
405 obj->i2c.pclk_bit = (uint8_t)(0x10 * wk_cks); /* P_phi / xx */
406 obj->i2c.width_low = (uint8_t)(tmp_L_width | 0x000000E0);
407 obj->i2c.width_hi = (uint8_t)(tmp_H_width | 0x000000E0);
408
409 /* full reset */
410 i2c_reg_reset(obj);
411}
412
413int i2c_read(i2c_t *obj, int address, char *data, int length, int stop) {
414 int count = 0;
415 int status;
416 int value;
417 volatile uint32_t work_reg = 0;
418
419 i2c_set_MR3_ACK(obj);
420 /* There is a STOP condition for last processing */
421 if (obj->i2c.last_stop_flag != 0) {
422 status = i2c_start(obj);
423 if (status != 0) {
424 i2c_set_err_noslave(obj);
425 return I2C_ERROR_BUS_BUSY;
426 }
427 }
428 obj->i2c.last_stop_flag = stop;
429 /* Send Slave address */
430 status = i2c_read_address_write(obj, (address | 0x01));
431 if (status != 0) {
432 i2c_set_err_noslave(obj);
433 return I2C_ERROR_NO_SLAVE;
434 }
435 /* wait RDRF */
436 status = i2c_wait_RDRF(obj);
437 /* check ACK/NACK */
438 if ((status != 0) || ((REG(SR2.UINT32) & SR2_NACKF) != 0)) {
439 /* Slave sends NACK */
440 (void)i2c_set_STOP(obj);
441 /* dummy read */
442 value = REG(DRR.UINT32);
443 (void)i2c_wait_STOP(obj);
444 i2c_set_SR2_NACKF_STOP(obj);
445 obj->i2c.last_stop_flag = 1;
446 return I2C_ERROR_NO_SLAVE;
447 }
448 if (length != 0) {
449 /* Read in all except last byte */
450 if (length > 2) {
451 /* dummy read */
452 value = REG(DRR.UINT32);
453 for (count = 0; count < (length - 1); count++) {
454 /* wait for it to arrive */
455 status = i2c_wait_RDRF(obj);
456 if (status != 0) {
457 i2c_set_err_noslave(obj);
458 return I2C_ERROR_NO_SLAVE;
459 }
460 /* Recieve the data */
461 if (count == (length - 2)) {
462 value = i2c_do_read(obj, 1);
463 } else if ((length >= 3) && (count == (length - 3))) {
464 value = i2c_do_read(obj, 2);
465 } else {
466 value = i2c_do_read(obj, 0);
467 }
468 data[count] = (char)value;
469 }
470 } else if (length == 2) {
471 /* Set MR3 WAIT bit is 1 */
472 REG(MR3.UINT32) |= MR3_WAIT;
473 /* dummy read */
474 value = REG(DRR.UINT32);
475 /* wait for it to arrive */
476 status = i2c_wait_RDRF(obj);
477 if (status != 0) {
478 i2c_set_err_noslave(obj);
479 return I2C_ERROR_NO_SLAVE;
480 }
481 i2c_set_MR3_NACK(obj);
482 data[count] = (char)REG(DRR.UINT32);
483 count++;
484 } else {
485 /* length == 1 */
486 /* Set MR3 WAIT bit is 1 */;
487 REG(MR3.UINT32) |= MR3_WAIT;
488 i2c_set_MR3_NACK(obj);
489 /* dummy read */
490 value = REG(DRR.UINT32);
491 }
492 /* wait for it to arrive */
493 status = i2c_wait_RDRF(obj);
494 if (status != 0) {
495 i2c_set_err_noslave(obj);
496 return I2C_ERROR_NO_SLAVE;
497 }
498
499 /* If not repeated start, send stop. */
500 if (stop) {
501 (void)i2c_set_STOP(obj);
502 /* RIICnDRR read */
503 value = (REG(DRR.UINT32) & 0xFF);
504 data[count] = (char)value;
505 /* RIICnMR3.WAIT = 0 */
506 REG(MR3.UINT32) &= ~MR3_WAIT;
507 (void)i2c_wait_STOP(obj);
508 i2c_set_SR2_NACKF_STOP(obj);
509 } else {
510 (void)i2c_restart(obj);
511 /* RIICnDRR read */
512 value = (REG(DRR.UINT32) & 0xFF);
513 data[count] = (char)value;
514 /* RIICnMR3.WAIT = 0 */
515 REG(MR3.UINT32) &= ~MR3_WAIT;
516 (void)i2c_wait_START(obj);
517 /* SR2.START = 0 */
518 REG(SR2.UINT32) &= ~SR2_START;
519 }
520 } else {
521 /* If not repeated start, send stop. */
522 if (stop) {
523 (void)i2c_set_STOP(obj);
524 (void)i2c_wait_STOP(obj);
525 i2c_set_SR2_NACKF_STOP(obj);
526 } else {
527 (void)i2c_restart(obj);
528 (void)i2c_wait_START(obj);
529 /* SR2.START = 0 */
530 REG(SR2.UINT32) &= ~SR2_START;
531 }
532 }
533
534 return length;
535}
536
537int i2c_write(i2c_t *obj, int address, const char *data, int length, int stop) {
538 int cnt;
539 int status;
540
541 /* There is a STOP condition for last processing */
542 if (obj->i2c.last_stop_flag != 0) {
543 status = i2c_start(obj);
544 if (status != 0) {
545 i2c_set_err_noslave(obj);
546 return I2C_ERROR_BUS_BUSY;
547 }
548 }
549 obj->i2c.last_stop_flag = stop;
550 /* Send Slave address */
551 status = i2c_do_write(obj, address);
552 if (status != 0) {
553 i2c_set_err_noslave(obj);
554 return I2C_ERROR_NO_SLAVE;
555 }
556 /* Wait send end */
557 status = i2c_wait_TEND(obj);
558 if ((status != 0) || ((REG(SR2.UINT32) & SR2_NACKF) != 0)) {
559 /* Slave sends NACK */
560 i2c_set_err_noslave(obj);
561 return I2C_ERROR_NO_SLAVE;
562 }
563 /* Send Write data */
564 for (cnt=0; cnt<length; cnt++) {
565 status = i2c_do_write(obj, data[cnt]);
566 if(status != 0) {
567 i2c_set_err_noslave(obj);
568 return cnt;
569 } else {
570 /* Wait send end */
571 status = i2c_wait_TEND(obj);
572 if ((status != 0) || ((REG(SR2.UINT32) & SR2_NACKF) != 0)) {
573 /* Slave sends NACK */
574 i2c_set_err_noslave(obj);
575 return I2C_ERROR_NO_SLAVE;
576 }
577 }
578 }
579 /* If not repeated start, send stop. */
580 if (stop) {
581 (void)i2c_set_STOP(obj);
582 (void)i2c_wait_STOP(obj);
583 i2c_set_SR2_NACKF_STOP(obj);
584 } else {
585 (void)i2c_restart(obj);
586 (void)i2c_wait_START(obj);
587 /* SR2.START = 0 */
588 REG(SR2.UINT32) &= ~SR2_START;
589
590 }
591
592 return length;
593}
594
595void i2c_reset(i2c_t *obj) {
596 (void)i2c_set_STOP(obj);
597 (void)i2c_wait_STOP(obj);
598 i2c_set_SR2_NACKF_STOP(obj);
599}
600
601int i2c_byte_read(i2c_t *obj, int last) {
602 int status;
603 int data;
604
605 data = i2c_do_read(obj, last);
606 /* wait for it to arrive */
607 status = i2c_wait_RDRF(obj);
608 if (status != 0) {
609 i2c_set_SR2_NACKF_STOP(obj);
610 return I2C_ERROR_NO_SLAVE;
611 }
612
613 return data;
614}
615
616int i2c_byte_write(i2c_t *obj, int data) {
617 int ack = 0;
618 int status;
619 int timeout = 0;
620
621 status = i2c_do_write(obj, (data & 0xFF));
622 if (status != 0) {
623 i2c_set_SR2_NACKF_STOP(obj);
624 } else {
625 while (((i2c_status(obj) & SR2_RDRF) == 0) && ((i2c_status(obj) & SR2_TEND) == 0)) {
626 timeout++;
627 if (timeout >= WAIT_TIMEOUT) {
628 return ack;
629 }
630 }
631 /* check ACK/NACK */
632 if ((REG(SR2.UINT32) & SR2_NACKF) != 0) {
633 /* NACK */
634 i2c_set_SR2_NACKF_STOP(obj);
635 } else {
636 ack = 1;
637 }
638 }
639
640 return ack;
641}
642
643void i2c_slave_mode(i2c_t *obj, int enable_slave) {
644 if (enable_slave != 0) {
645 REG(SER.UINT32) |= SER_SAR0E; // only slave addr 0 is enabled
646 } else {
647 REG(SER.UINT32) &= ~SER_SAR0E; // no slave addr enabled
648 }
649}
650
651int i2c_slave_receive(i2c_t *obj) {
652 int status;
653 int retval;
654
655 status = (REG(SR1.UINT8[0]) & SR1_AAS0);
656 status |= (REG(CR2.UINT8[0]) & CR2_TRS) >> 4;
657
658 switch(status) {
659 case 0x01:
660 /* the master is writing to this slave */
661 retval = 3;
662 break;
663 case 0x02:
664 /* the master is writing to all slave */
665 retval = 2;
666 break;
667 case 0x03:
668 /* the master has requested a read from this slave */
669 retval = 1;
670 break;
671 default :
672 /* no data */
673 retval = 0;
674 break;
675 }
676
677 return retval;
678}
679
680int i2c_slave_read(i2c_t *obj, char *data, int length) {
681 int timeout = 0;
682 int count;
683 int break_flg = 0;
684
685 if(length <= 0) {
686 return 0;
687 }
688 for (count = 0; ((count < (length + 1)) && (break_flg == 0)); count++) {
689 /* There is no timeout, but the upper limit value is set to avoid an infinite loop. */
690 while (((i2c_status(obj) & SR2_STOP) != 0) || ((i2c_status(obj) & SR2_RDRF) == 0)) {
691 if ((i2c_status(obj) & SR2_STOP) != 0) {
692 break_flg = 1;
693 break;
694 }
695 timeout ++;
696 if (timeout >= WAIT_TIMEOUT) {
697 return -1;
698 }
699 }
700 if (break_flg == 0) {
701 if (count == 0) {
702 /* dummy read */
703 (void)REG(DRR.UINT32);
704 } else {
705 data[count - 1] = (char)(REG(DRR.UINT32) & 0xFF);
706 }
707 }
708 }
709 if (break_flg == 0) {
710 (void)i2c_wait_STOP(obj);
711 } else {
712 if ((i2c_status(obj) & SR2_RDRF) != 0) {
713 if (count <= 1) {
714 /* fail safe */
715 /* dummy read */
716 (void)REG(DRR.UINT32);
717 } else {
718 data[count - 2] = (char)(REG(DRR.UINT32) & 0xFF);
719 }
720 }
721 }
722 /* SR2.STOP = 0 */
723 REG(SR2.UINT32) &= ~SR2_STOP;
724
725 return (count - 1);
726}
727
728int i2c_slave_write(i2c_t *obj, const char *data, int length) {
729 int count = 0;
730 int status = 0;
731
732 if(length <= 0) {
733 return 0;
734 }
735
736 while ((count < length) && (status == 0)) {
737 status = i2c_do_write(obj, data[count]);
738 if(status == 0) {
739 /* Wait send end */
740 status = i2c_wait_TEND(obj);
741 if ((status != 0) || ((count < (length - 1)) && ((REG(SR2.UINT32) & SR2_NACKF) != 0))) {
742 /* NACK */
743 break;
744 }
745 }
746 count++;
747 }
748 /* dummy read */
749 (void)REG(DRR.UINT32);
750 (void)i2c_wait_STOP(obj);
751 i2c_set_SR2_NACKF_STOP(obj);
752
753 return count;
754}
755
756void i2c_slave_address(i2c_t *obj, int idx, uint32_t address, uint32_t mask) {
757 REG(SAR0.UINT32) = (address & 0xfffffffe);
758}
759
760#if DEVICE_I2C_ASYNCH
761
762#define IRQ_NUM 4
763#define IRQ_TX 0
764#define IRQ_RX 1
765#define IRQ_ERR1 2
766#define IRQ_ERR2 3
767
768static void i2c_irqs_set(i2c_t *obj, uint32_t enable);
769
770static void i2c0_tx_irq(void);
771static void i2c1_tx_irq(void);
772static void i2c2_tx_irq(void);
773static void i2c3_tx_irq(void);
774static void i2c0_rx_irq(void);
775static void i2c1_rx_irq(void);
776static void i2c2_rx_irq(void);
777static void i2c3_rx_irq(void);
778static void i2c0_al_irq(void);
779static void i2c1_al_irq(void);
780static void i2c2_al_irq(void);
781static void i2c3_al_irq(void);
782static void i2c0_to_irq(void);
783static void i2c1_to_irq(void);
784static void i2c2_to_irq(void);
785static void i2c3_to_irq(void);
786
787static const IRQn_Type irq_set_tbl[RIIC_COUNT][IRQ_NUM] = {
788 {INTIICTEI0_IRQn, INTIICRI0_IRQn, INTIICALI0_IRQn, INTIICTMOI0_IRQn},
789 {INTIICTEI1_IRQn, INTIICRI1_IRQn, INTIICALI1_IRQn, INTIICTMOI1_IRQn},
790 {INTIICTEI2_IRQn, INTIICRI2_IRQn, INTIICALI2_IRQn, INTIICTMOI2_IRQn},
791 {INTIICTEI3_IRQn, INTIICRI3_IRQn, INTIICALI3_IRQn, INTIICTMOI3_IRQn},
792};
793
794static const IRQHandler hander_set_tbl[RIIC_COUNT][IRQ_NUM] = {
795 {i2c0_tx_irq, i2c0_rx_irq, i2c0_al_irq, i2c0_to_irq},
796 {i2c1_tx_irq, i2c1_rx_irq, i2c1_al_irq, i2c1_to_irq},
797 {i2c2_tx_irq, i2c2_rx_irq, i2c2_al_irq, i2c2_to_irq},
798 {i2c3_tx_irq, i2c3_rx_irq, i2c3_al_irq, i2c3_to_irq},
799};
800
801struct i2c_global_data_s {
802 i2c_t *async_obj;
803 uint32_t async_callback, event, shouldStop, address;
804};
805
806static struct i2c_global_data_s i2c_data[RIIC_COUNT];
807
808static void i2c_transfer_finished(i2c_t *obj)
809{
810 i2c_irqs_set(obj, 0);
811 uint32_t index = obj->i2c.i2c;
812 i2c_data[index].event = I2C_EVENT_TRANSFER_COMPLETE;
813 i2c_data[index].async_obj = NULL;
814 ((void (*)())i2c_data[index].async_callback)();
815}
816
817static void i2c_tx_irq(IRQn_Type irq_num, uint32_t index)
818{
819 i2c_t *obj = i2c_data[index].async_obj;
820 if ((REG(SR2.UINT32) & SR2_NACKF)) {
821 /* Slave sends NACK */
822 i2c_set_err_noslave(obj);
823 i2c_data[index].event = I2C_EVENT_ERROR | I2C_EVENT_TRANSFER_EARLY_NACK;
824 i2c_abort_asynch(obj);
825 ((void (*)())i2c_data[index].async_callback)();
826 return;
827 }
828 if (obj->tx_buff.pos == obj->tx_buff.length) {
829 /* All datas have tranferred */
830
831 /* Clear TEND */
832 REG(SR2.UINT32) &= ~(SR2_TEND);
833
834 /* If not repeated start, send stop. */
835 if (i2c_data[index].shouldStop && obj->rx_buff.length == 0) {
836 (void)i2c_set_STOP(obj);
837 (void)i2c_wait_STOP(obj);
838 i2c_set_SR2_NACKF_STOP(obj);
839 i2c_transfer_finished(obj);
840 } else {
841 (void)i2c_restart(obj);
842 (void)i2c_wait_START(obj);
843 /* SR2.START = 0 */
844 REG(SR2.UINT32) &= ~SR2_START;
845 if (obj->rx_buff.length) {
846 /* Ready to read */
847 i2c_set_MR3_ACK(obj);
848
849 /* Disable INTRIICTEI */
850 REG(IER.UINT8[0]) &= ~(1 << 6);
851
852 /* Send Slave address */
853 if (i2c_read_address_write(obj, (i2c_data[index].address | 0x01)) != 0) {
854 i2c_set_err_noslave(obj);
855 i2c_data[index].event = I2C_EVENT_ERROR | I2C_EVENT_ERROR_NO_SLAVE;
856 i2c_abort_asynch(obj);
857 ((void (*)())i2c_data[index].async_callback)();
858 return;
859 }
860 } else {
861 i2c_transfer_finished(obj);
862 }
863 }
864 } else {
865 /* Send next 1 byte */
866 if (i2c_do_write(obj, *(uint8_t *)obj->tx_buff.buffer) != 0) {
867 i2c_set_err_noslave(obj);
868 i2c_data[index].event = I2C_EVENT_ERROR | I2C_EVENT_ERROR_NO_SLAVE;
869 i2c_abort_asynch(obj);
870 ((void (*)())i2c_data[index].async_callback)();
871 return;
872 }
873 obj->tx_buff.buffer = (uint8_t *)obj->tx_buff.buffer + 1;
874 ++obj->tx_buff.pos;
875 }
876}
877
878static void i2c_rx_irq(IRQn_Type irq_num, uint32_t index)
879{
880 i2c_t *obj = i2c_data[index].async_obj;
881 if (obj->rx_buff.pos == SIZE_MAX) {
882 if ((REG(SR2.UINT32) & SR2_NACKF) != 0) {
883 /* Slave sends NACK */
884 (void)i2c_set_STOP(obj);
885 /* dummy read */
886 if (REG(DRR.UINT32)) {}
887 (void)i2c_wait_STOP(obj);
888 i2c_set_SR2_NACKF_STOP(obj);
889 obj->i2c.last_stop_flag = 1;
890
891 i2c_data[index].event = I2C_EVENT_ERROR | I2C_EVENT_TRANSFER_EARLY_NACK;
892 i2c_abort_asynch(obj);
893 ((void (*)())i2c_data[index].async_callback)();
894 return;
895 }
896 if (obj->rx_buff.length == 1) {
897 /* length == 1 */
898 /* Set MR3 WAIT bit is 1 */;
899 REG(MR3.UINT32) |= MR3_WAIT;
900 i2c_set_MR3_NACK(obj);
901 } else if (obj->rx_buff.length == 2) {
902 /* Set MR3 WAIT bit is 1 */
903 REG(MR3.UINT32) |= MR3_WAIT;
904 }
905 /* dummy read */
906 if (REG(DRR.UINT32)) {}
907 obj->rx_buff.pos = 0;
908 return;
909 }
910 if ((REG(SR2.UINT32) & SR2_NACKF) != 0) {
911 /* Slave sends NACK */
912 i2c_set_err_noslave(obj);
913 i2c_data[index].event = I2C_EVENT_ERROR | I2C_EVENT_TRANSFER_EARLY_NACK;
914 i2c_abort_asynch(obj);
915 ((void (*)())i2c_data[index].async_callback)();
916 return;
917 } else {
918 switch (obj->rx_buff.length - obj->rx_buff.pos) {
919 case 1:
920 /* Finished */
921 /* If not repeated start, send stop. */
922 if (i2c_data[index].shouldStop) {
923 (void)i2c_set_STOP(obj);
924 /* RIICnDRR read */
925 *(uint8_t *)obj->rx_buff.buffer = REG(DRR.UINT32) & 0xFF;
926 /* RIICnMR3.WAIT = 0 */
927 REG(MR3.UINT32) &= ~MR3_WAIT;
928 (void)i2c_wait_STOP(obj);
929 i2c_set_SR2_NACKF_STOP(obj);
930 } else {
931 (void)i2c_restart(obj);
932 /* RIICnDRR read */
933 *(uint8_t *)obj->rx_buff.buffer = REG(DRR.UINT32) & 0xFF;
934 /* RIICnMR3.WAIT = 0 */
935 REG(MR3.UINT32) &= ~MR3_WAIT;
936 (void)i2c_wait_START(obj);
937 /* SR2.START = 0 */
938 REG(SR2.UINT32) &= ~SR2_START;
939 }
940
941 i2c_transfer_finished(obj);
942 return;
943
944 case 2:
945 i2c_set_MR3_NACK(obj);
946 break;
947
948 case 3:
949 /* this time is befor last byte read */
950 /* Set MR3 WAIT bit is 1 */
951 REG(MR3.UINT32) |= MR3_WAIT;
952 break;
953
954 default:
955 i2c_set_MR3_ACK(obj);
956 break;
957 }
958 *(uint8_t *)obj->rx_buff.buffer = REG(DRR.UINT32) & 0xFF;
959 obj->rx_buff.buffer = (uint8_t *)obj->rx_buff.buffer + 1;
960 ++obj->rx_buff.pos;
961 }
962}
963
964static void i2c_err_irq(IRQn_Type irq_num, uint32_t index)
965{
966 i2c_t *obj = i2c_data[index].async_obj;
967 i2c_abort_asynch(obj);
968 i2c_data[index].event = I2C_EVENT_ERROR;
969 ((void (*)())i2c_data[index].async_callback)();
970}
971
972/* TX handler */
973static void i2c0_tx_irq(void)
974{
975 i2c_tx_irq(INTIICTEI0_IRQn, 0);
976}
977
978static void i2c1_tx_irq(void)
979{
980 i2c_tx_irq(INTIICTEI1_IRQn, 1);
981}
982
983static void i2c2_tx_irq(void)
984{
985 i2c_tx_irq(INTIICTEI2_IRQn, 2);
986}
987
988static void i2c3_tx_irq(void)
989{
990 i2c_tx_irq(INTIICTEI3_IRQn, 3);
991}
992
993/* RX handler */
994static void i2c0_rx_irq(void)
995{
996 i2c_rx_irq(INTIICRI0_IRQn, 0);
997}
998
999static void i2c1_rx_irq(void)
1000{
1001 i2c_rx_irq(INTIICRI1_IRQn, 1);
1002}
1003
1004static void i2c2_rx_irq(void)
1005{
1006 i2c_rx_irq(INTIICRI2_IRQn, 2);
1007}
1008
1009static void i2c3_rx_irq(void)
1010{
1011 i2c_rx_irq(INTIICRI3_IRQn, 3);
1012}
1013
1014/* Arbitration Lost handler */
1015static void i2c0_al_irq(void)
1016{
1017 i2c_err_irq(INTIICALI0_IRQn, 0);
1018}
1019
1020static void i2c1_al_irq(void)
1021{
1022 i2c_err_irq(INTIICALI1_IRQn, 1);
1023}
1024
1025static void i2c2_al_irq(void)
1026{
1027 i2c_err_irq(INTIICALI2_IRQn, 2);
1028}
1029
1030static void i2c3_al_irq(void)
1031{
1032 i2c_err_irq(INTIICALI3_IRQn, 3);
1033}
1034
1035/* Timeout handler */
1036static void i2c0_to_irq(void)
1037{
1038 i2c_err_irq(INTIICTMOI0_IRQn, 0);
1039}
1040
1041static void i2c1_to_irq(void)
1042{
1043 i2c_err_irq(INTIICTMOI1_IRQn, 1);
1044}
1045
1046static void i2c2_to_irq(void)
1047{
1048 i2c_err_irq(INTIICTMOI2_IRQn, 2);
1049}
1050
1051static void i2c3_to_irq(void)
1052{
1053 i2c_err_irq(INTIICTMOI3_IRQn, 3);
1054}
1055
1056static void i2c_irqs_set(i2c_t *obj, uint32_t enable)
1057{
1058 int i;
1059 const IRQn_Type *irqTable = irq_set_tbl[obj->i2c.i2c];
1060 const IRQHandler *handlerTable = hander_set_tbl[obj->i2c.i2c];
1061 for (i = 0; i < IRQ_NUM; ++i) {
1062 if (enable) {
1063 InterruptHandlerRegister(irqTable[i], handlerTable[i]);
1064 GIC_SetPriority(irqTable[i], 5);
1065 GIC_EnableIRQ(irqTable[i]);
1066 } else {
1067 GIC_DisableIRQ(irqTable[i]);
1068 }
1069 }
1070 REG(IER.UINT8[0]) = enable ? 0x63 : 0x00;
1071}
1072
1073/******************************************************************************
1074 * ASYNCHRONOUS HAL
1075 ******************************************************************************/
1076
1077void i2c_transfer_asynch(i2c_t *obj, const void *tx, size_t tx_length, void *rx, size_t rx_length, uint32_t address, uint32_t stop, uint32_t handler, uint32_t event, DMAUsage hint)
1078{
1079 MBED_ASSERT(obj);
1080 MBED_ASSERT(tx ? tx_length : 1);
1081 MBED_ASSERT(rx ? rx_length : 1);
1082 MBED_ASSERT((REG(SER.UINT32) & SER_SAR0E) == 0); /* Slave mode */
1083
1084 obj->tx_buff.buffer = (void *)tx;
1085 obj->tx_buff.length = tx_length;
1086 obj->tx_buff.pos = 0;
1087 obj->tx_buff.width = 8;
1088 obj->rx_buff.buffer = rx;
1089 obj->rx_buff.length = rx_length;
1090 obj->rx_buff.pos = SIZE_MAX;
1091 obj->rx_buff.width = 8;
1092 i2c_data[obj->i2c.i2c].async_obj = obj;
1093 i2c_data[obj->i2c.i2c].async_callback = handler;
1094 i2c_data[obj->i2c.i2c].event = 0;
1095 i2c_data[obj->i2c.i2c].shouldStop = stop;
1096 i2c_data[obj->i2c.i2c].address = address;
1097 i2c_irqs_set(obj, 1);
1098
1099 /* There is a STOP condition for last processing */
1100 if (obj->i2c.last_stop_flag != 0) {
1101 if (i2c_start(obj) != 0) {
1102 i2c_set_err_noslave(obj);
1103 i2c_data[obj->i2c.i2c].event = I2C_EVENT_ERROR | I2C_EVENT_ERROR_NO_SLAVE;
1104 i2c_abort_asynch(obj);
1105 ((void (*)())handler)();
1106 return;
1107 }
1108 }
1109 obj->i2c.last_stop_flag = stop;
1110
1111 if (rx_length && tx_length == 0) {
1112 /* Ready to read */
1113 i2c_set_MR3_ACK(obj);
1114
1115 /* Disable INTRIICTEI */
1116 REG(IER.UINT8[0]) &= ~(1 << 6);
1117
1118 address |= 0x01;
1119 }
1120 /* Send Slave address */
1121 if (i2c_do_write(obj, address) != 0) {
1122 i2c_set_err_noslave(obj);
1123 i2c_data[obj->i2c.i2c].event = I2C_EVENT_ERROR | I2C_EVENT_ERROR_NO_SLAVE;
1124 i2c_abort_asynch(obj);
1125 ((void (*)())handler)();
1126 return;
1127 }
1128}
1129
1130uint32_t i2c_irq_handler_asynch(i2c_t *obj)
1131{
1132 return i2c_data[obj->i2c.i2c].event;
1133}
1134
1135uint8_t i2c_active(i2c_t *obj)
1136{
1137 return i2c_data[obj->i2c.i2c].async_obj != NULL;
1138}
1139
1140void i2c_abort_asynch(i2c_t *obj)
1141{
1142 i2c_data[obj->i2c.i2c].async_obj = NULL;
1143 i2c_irqs_set(obj, 0);
1144 i2c_reg_reset(obj);
1145}
1146
1147#endif
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