[352] | 1 | /* mbed Microcontroller Library
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| 2 | * Copyright (c) 2006-2013 ARM Limited
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| 3 | *
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| 4 | * Licensed under the Apache License, Version 2.0 (the "License");
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| 5 | * you may not use this file except in compliance with the License.
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| 6 | * You may obtain a copy of the License at
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| 7 | *
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| 8 | * http://www.apache.org/licenses/LICENSE-2.0
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| 9 | *
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| 10 | * Unless required by applicable law or agreed to in writing, software
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| 11 | * distributed under the License is distributed on an "AS IS" BASIS,
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| 12 | * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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| 13 | * See the License for the specific language governing permissions and
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| 14 | * limitations under the License.
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| 15 | */
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| 16 | #include <stddef.h>
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| 17 |
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| 18 | #include "gpio_irq_api.h"
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| 19 | #include "intc_iodefine.h"
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| 20 | #include "pinmap.h"
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| 21 | #include "cmsis.h"
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| 22 | #include "gpio_addrdefine.h"
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| 23 |
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| 24 | #define CHANNEL_NUM 8
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| 25 |
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| 26 | static void gpio_irq0(void);
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| 27 | static void gpio_irq1(void);
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| 28 | static void gpio_irq2(void);
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| 29 | static void gpio_irq3(void);
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| 30 | static void gpio_irq4(void);
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| 31 | static void gpio_irq5(void);
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| 32 | static void gpio_irq6(void);
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| 33 | static void gpio_irq7(void);
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| 34 |
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| 35 | static gpio_irq_t *channel_obj[CHANNEL_NUM] = {NULL};
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| 36 | static gpio_irq_handler irq_handler;
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| 37 | static const int nIRQn_h = 32;
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| 38 | extern PinName gpio_multi_guard;
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| 39 |
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| 40 | enum {
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| 41 | IRQ0,IRQ1,
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| 42 | IRQ2,IRQ3,
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| 43 | IRQ4,IRQ5,
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| 44 | IRQ6,IRQ7,
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| 45 |
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| 46 | } IRQNo;
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| 47 |
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| 48 | static const IRQHandler irq_tbl[CHANNEL_NUM] = {
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| 49 | &gpio_irq0,
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| 50 | &gpio_irq1,
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| 51 | &gpio_irq2,
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| 52 | &gpio_irq3,
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| 53 | &gpio_irq4,
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| 54 | &gpio_irq5,
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| 55 | &gpio_irq6,
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| 56 | &gpio_irq7,
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| 57 | };
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| 58 |
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| 59 | static const PinMap PinMap_IRQ[] = {
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| 60 | {P1_0, IRQ0, 4}, {P1_1, IRQ1, 4}, {P1_2, IRQ2, 4},
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| 61 | {P1_3, IRQ3, 4}, {P1_4, IRQ4, 4}, {P1_5, IRQ5, 4},
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| 62 | {P1_6, IRQ6, 4}, {P1_7, IRQ7, 4}, {P1_8, IRQ2, 3},
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| 63 | {P1_9, IRQ3, 3}, {P1_10, IRQ4, 3}, {P1_11, IRQ5, 3}, // 11
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| 64 | {P2_0, IRQ5, 6}, {P2_12, IRQ6, 6}, {P2_13, IRQ7, 8},
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| 65 | {P2_14, IRQ0, 8}, {P2_15, IRQ1, 8}, // 16
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| 66 | {P3_0, IRQ2, 3}, {P3_1, IRQ6, 3}, {P3_3, IRQ4, 3},
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| 67 | {P3_9, IRQ6, 8}, // 20
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| 68 | {P4_8, IRQ0, 8}, {P4_9, IRQ1, 8}, {P4_10, IRQ2, 8},
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| 69 | {P4_11, IRQ3, 8}, {P4_12, IRQ4, 8}, {P4_13, IRQ5, 8},
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| 70 | {P4_14, IRQ6, 8}, {P4_15, IRQ7, 8}, // 28
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| 71 | {P5_6, IRQ6, 6}, {P5_8, IRQ0, 2}, {P5_9, IRQ2, 4}, // 31
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| 72 | {P6_0, IRQ5, 6}, {P6_1, IRQ4, 4}, {P6_2, IRQ7, 4},
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| 73 | {P6_3, IRQ2, 4}, {P6_4, IRQ3, 4}, {P6_8, IRQ0, 8},
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| 74 | {P6_9, IRQ1, 8}, {P6_10, IRQ2, 8}, {P6_11, IRQ3, 8},
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| 75 | {P6_12, IRQ4, 8}, {P6_13, IRQ5, 8}, {P6_14, IRQ6, 8},
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| 76 | {P6_15, IRQ7, 8}, // 44
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| 77 | {P7_8, IRQ1, 8}, {P7_9, IRQ0, 8}, {P7_10, IRQ2, 8},
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| 78 | {P7_11, IRQ3, 8}, {P7_12, IRQ4, 8}, {P7_13, IRQ5, 8},
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| 79 | {P7_14, IRQ6, 8}, // 51
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| 80 | {P8_2, IRQ0, 5}, {P8_3, IRQ1, 6}, {P8_7, IRQ5, 4},
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| 81 | {P9_1, IRQ0, 4}, // 55
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| 82 | {P11_12,IRQ3, 3}, {P11_15,IRQ1, 3}, // 57
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| 83 |
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| 84 | {NC, NC, 0}
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| 85 | };
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| 86 |
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| 87 | static void handle_interrupt_in(int irq_num) {
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| 88 | uint16_t irqs;
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| 89 | uint16_t edge_req;
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| 90 | gpio_irq_t *obj;
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| 91 | gpio_irq_event irq_event;
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| 92 |
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| 93 | irqs = INTCIRQRR;
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| 94 | if (irqs & (1 << irq_num)) {
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| 95 | obj = channel_obj[irq_num];
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| 96 | if (obj != NULL) {
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| 97 | edge_req = ((INTCICR1 >> (obj->ch * 2)) & 3);
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| 98 | if (edge_req == 1) {
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| 99 | irq_event = IRQ_FALL;
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| 100 | } else if (edge_req == 2) {
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| 101 | irq_event = IRQ_RISE;
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| 102 | } else {
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| 103 | uint32_t mask = (1 << (obj->pin & 0x0F));
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| 104 | __I uint32_t *reg_in = (volatile uint32_t *) PPR((int)PINGROUP(obj->pin));
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| 105 |
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| 106 | if ((*reg_in & mask) == 0) {
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| 107 | irq_event = IRQ_FALL;
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| 108 | } else {
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| 109 | irq_event = IRQ_RISE;
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| 110 | }
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| 111 | }
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| 112 | irq_handler(obj->port, irq_event);
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| 113 | }
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| 114 | INTCIRQRR &= ~(1 << irq_num);
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| 115 | }
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| 116 | }
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| 117 |
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| 118 | static void gpio_irq0(void) {
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| 119 | handle_interrupt_in(0);
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| 120 | }
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| 121 |
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| 122 | static void gpio_irq1(void) {
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| 123 | handle_interrupt_in(1);
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| 124 | }
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| 125 |
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| 126 | static void gpio_irq2(void) {
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| 127 | handle_interrupt_in(2);
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| 128 | }
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| 129 |
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| 130 | static void gpio_irq3(void) {
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| 131 | handle_interrupt_in(3);
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| 132 | }
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| 133 |
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| 134 | static void gpio_irq4(void) {
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| 135 | handle_interrupt_in(4);
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| 136 | }
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| 137 |
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| 138 | static void gpio_irq5(void) {
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| 139 | handle_interrupt_in(5);
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| 140 | }
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| 141 |
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| 142 | static void gpio_irq6(void) {
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| 143 | handle_interrupt_in(6);
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| 144 | }
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| 145 |
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| 146 | static void gpio_irq7(void) {
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| 147 | handle_interrupt_in(7);
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| 148 | }
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| 149 |
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| 150 | int gpio_irq_init(gpio_irq_t *obj, PinName pin, gpio_irq_handler handler, uint32_t id) {
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| 151 | int shift;
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| 152 | if (pin == NC) return -1;
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| 153 |
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| 154 | obj->ch = pinmap_peripheral(pin, PinMap_IRQ);
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| 155 | obj->pin = (int)pin ;
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| 156 | obj->port = (int)id ;
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| 157 |
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| 158 | shift = obj->ch*2;
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| 159 | channel_obj[obj->ch] = obj;
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| 160 | irq_handler = handler;
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| 161 |
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| 162 | pinmap_pinout(pin, PinMap_IRQ);
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| 163 | gpio_multi_guard = pin; /* Set multi guard */
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| 164 |
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| 165 | // INTC settings
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| 166 | InterruptHandlerRegister((IRQn_Type)(nIRQn_h+obj->ch), (void (*)(uint32_t))irq_tbl[obj->ch]);
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| 167 | INTCICR1 &= ~(0x3 << shift);
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| 168 | GIC_SetPriority((IRQn_Type)(nIRQn_h+obj->ch), 5);
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| 169 | obj->int_enable = 1;
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| 170 | __enable_irq();
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| 171 |
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| 172 | return 0;
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| 173 | }
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| 174 |
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| 175 | void gpio_irq_free(gpio_irq_t *obj) {
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| 176 | channel_obj[obj->ch] = NULL;
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| 177 | }
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| 178 |
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| 179 | void gpio_irq_set(gpio_irq_t *obj, gpio_irq_event event, uint32_t enable) {
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| 180 | int shift = obj->ch*2;
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| 181 | uint16_t val = event == IRQ_RISE ? 2 :
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| 182 | event == IRQ_FALL ? 1 : 0;
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| 183 | uint16_t work_icr_val;
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| 184 |
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| 185 | /* check edge interrupt setting */
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| 186 | work_icr_val = INTCICR1;
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| 187 | if (enable == 1) {
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| 188 | /* Set interrupt serect */
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| 189 | work_icr_val |= (val << shift);
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| 190 | } else {
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| 191 | /* Clear interrupt serect */
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| 192 | work_icr_val &= ~(val << shift);
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| 193 | }
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| 194 |
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| 195 | if ((work_icr_val & (3 << shift)) == 0) {
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| 196 | /* No edge interrupt setting */
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| 197 | GIC_DisableIRQ((IRQn_Type)(nIRQn_h+obj->ch));
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| 198 | /* Clear Interrupt flags */
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| 199 | INTCIRQRR &= ~(1 << obj->ch);
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| 200 | INTCICR1 = work_icr_val;
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| 201 | } else if (obj->int_enable == 1) {
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| 202 | INTCICR1 = work_icr_val;
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| 203 | GIC_EnableIRQ((IRQn_Type)(nIRQn_h + obj->ch));
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| 204 | } else {
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| 205 | INTCICR1 = work_icr_val;
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| 206 | }
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| 207 | }
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| 208 |
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| 209 | void gpio_irq_enable(gpio_irq_t *obj) {
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| 210 | int shift = obj->ch*2;
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| 211 | uint16_t work_icr_val = INTCICR1;
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| 212 |
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| 213 | /* check edge interrupt setting */
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| 214 | if ((work_icr_val & (3 << shift)) != 0) {
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| 215 | GIC_EnableIRQ((IRQn_Type)(nIRQn_h + obj->ch));
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| 216 | }
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| 217 | obj->int_enable = 1;
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| 218 | }
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| 219 |
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| 220 | void gpio_irq_disable(gpio_irq_t *obj) {
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| 221 | GIC_DisableIRQ((IRQn_Type)(nIRQn_h + obj->ch));
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| 222 | obj->int_enable = 0;
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| 223 | }
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| 224 |
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