source: asp3_tinet_ecnl_arm/trunk/asp3_dcre/mbed/targets/TARGET_RENESAS/TARGET_RZ_A1H/device/system_MBRZA1H.c@ 352

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[352]1/**************************************************************************//**
2 * @file system_MBRZA1H.c
3 * @brief CMSIS Device System Source File for
4 * ARM Cortex-A9 Device Series
5 * @version V1.00
6 * @date 09 January 2015
7 *
8 * @note
9 *
10 ******************************************************************************/
11/* Copyright (c) 2011 - 2015 ARM LIMITED
12
13 All rights reserved.
14 Redistribution and use in source and binary forms, with or without
15 modification, are permitted provided that the following conditions are met:
16 - Redistributions of source code must retain the above copyright
17 notice, this list of conditions and the following disclaimer.
18 - Redistributions in binary form must reproduce the above copyright
19 notice, this list of conditions and the following disclaimer in the
20 documentation and/or other materials provided with the distribution.
21 - Neither the name of ARM nor the names of its contributors may be used
22 to endorse or promote products derived from this software without
23 specific prior written permission.
24 *
25 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
26 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
27 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
28 ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
29 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
30 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
31 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
32 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
33 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
34 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
35 POSSIBILITY OF SUCH DAMAGE.
36 ---------------------------------------------------------------------------*/
37
38
39#include <stdint.h>
40#include "MBRZA1H.h"
41#include "RZ_A1_Init.h"
42
43
44#if defined(__ARMCC_VERSION)
45extern void $Super$$main(void);
46__asm void FPUEnable(void);
47#else
48void FPUEnable(void);
49
50#endif
51
52#define FRQCR_IFC_MSK (0x0030)
53#define FRQCR_IFC_SHFT (8)
54#define FRQCR_IFC_1P1 (0) /* x1/1 */
55#define FRQCR_IFC_2P3 (1) /* x2/3 */
56#define FRQCR_IFC_1P3 (3) /* x1/3 */
57
58extern uint32_t IRQNestLevel;
59unsigned char seen_id0_active = 0; // single byte to hold a flag used in the workaround for GIC errata 733075
60uint32_t SystemCoreClock = CM0_RENESAS_RZ_A1_I_CLK; /*!< System Clock Frequency (Core Clock) */
61
62
63/**
64 * Initialize the cache.
65 *
66 * @param none
67 * @return none
68 *
69 * @brief Initialise caches. Requires PL1, so implemented as an SVC in case threads are USR mode.
70 */
71#if defined(__ARMCC_VERSION)
72#pragma push
73#pragma arm
74
75void InitMemorySubsystem(void) {
76
77 /* This SVC is specific for reset where data / tlb / btac may contain undefined data, therefore before
78 * enabling the cache you must invalidate the instruction cache, the data cache, TLB, and BTAC.
79 * You are not required to invalidate the main TLB, even though it is recommended for safety
80 * reasons. This ensures compatibility with future revisions of the processor. */
81
82 unsigned int l2_id;
83
84 /* Invalidate undefined data */
85 __ca9u_inv_tlb_all();
86 __v7_inv_icache_all();
87 __v7_inv_dcache_all();
88 __v7_inv_btac();
89
90 /* Don't use this function during runtime since caches may contain valid data. For a correct cache maintenance you may need to execute a clean and
91 * invalidate in order to flush the valid data to the next level cache.
92 */
93 __enable_mmu();
94
95 /* After MMU is enabled and data has been invalidated, enable caches and BTAC */
96 __enable_caches();
97 __enable_btac();
98
99 /* If present, you may also need to Invalidate and Enable L2 cache here */
100 l2_id = PL310_GetID();
101 if (l2_id)
102 {
103 PL310_InvAllByWay();
104 PL310_Enable();
105 }
106}
107#pragma pop
108
109#elif defined(__GNUC__)
110
111void InitMemorySubsystem(void) {
112
113 /* This SVC is specific for reset where data / tlb / btac may contain undefined data, therefore before
114 * enabling the cache you must invalidate the instruction cache, the data cache, TLB, and BTAC.
115 * You are not required to invalidate the main TLB, even though it is recommended for safety
116 * reasons. This ensures compatibility with future revisions of the processor. */
117
118 unsigned int l2_id;
119
120 /* Invalidate undefined data */
121 __ca9u_inv_tlb_all();
122 __v7_inv_icache_all();
123 __v7_inv_dcache_all();
124 __v7_inv_btac();
125
126 /* Don't use this function during runtime since caches may contain valid data. For a correct cache maintenance you may need to execute a clean and
127 * invalidate in order to flush the valid data to the next level cache.
128 */
129 __enable_mmu();
130
131 /* After MMU is enabled and data has been invalidated, enable caches and BTAC */
132 __enable_caches();
133 __enable_btac();
134
135 /* If present, you may also need to Invalidate and Enable L2 cache here */
136 l2_id = PL310_GetID();
137 if (l2_id)
138 {
139 PL310_InvAllByWay();
140 PL310_Enable();
141 }
142}
143#elif defined ( __ICCARM__ )
144
145void InitMemorySubsystem(void) {
146
147 /* This SVC is specific for reset where data / tlb / btac may contain undefined data, therefore before
148 * enabling the cache you must invalidate the instruction cache, the data cache, TLB, and BTAC.
149 * You are not required to invalidate the main TLB, even though it is recommended for safety
150 * reasons. This ensures compatibility with future revisions of the processor. */
151
152 unsigned int l2_id;
153
154 /* Invalidate undefined data */
155 __ca9u_inv_tlb_all();
156 __v7_inv_icache_all();
157 __v7_inv_dcache_all();
158 __v7_inv_btac();
159
160 /* Don't use this function during runtime since caches may contain valid data. For a correct cache maintenance you may need to execute a clean and
161 * invalidate in order to flush the valid data to the next level cache.
162 */
163 __enable_mmu();
164
165 /* After MMU is enabled and data has been invalidated, enable caches and BTAC */
166 __enable_caches();
167 __enable_btac();
168
169 /* If present, you may also need to Invalidate and Enable L2 cache here */
170 l2_id = PL310_GetID();
171 if (l2_id)
172 {
173 PL310_InvAllByWay();
174 PL310_Enable();
175 }
176}
177#else
178
179#endif
180
181
182extern IRQHandler IRQTable[Renesas_RZ_A1_IRQ_MAX+1];
183
184uint32_t IRQCount = sizeof IRQTable / 4;
185
186uint32_t InterruptHandlerRegister (IRQn_Type irq, IRQHandler handler)
187{
188 if (irq < IRQCount) {
189 IRQTable[irq] = handler;
190 return 0;
191 }
192 else {
193 return 1;
194 }
195}
196
197uint32_t InterruptHandlerUnregister (IRQn_Type irq)
198{
199 if (irq < IRQCount) {
200 IRQTable[irq] = 0;
201 return 0;
202 }
203 else {
204 return 1;
205 }
206}
207
208/**
209 * Update SystemCoreClock variable
210 *
211 * @param none
212 * @return none
213 *
214 * @brief Updates the SystemCoreClock with current core Clock.
215 */
216void SystemCoreClockUpdate (void)
217{
218 uint32_t frqcr_ifc = ((uint32_t)CPG.FRQCR & (uint32_t)FRQCR_IFC_MSK) >> FRQCR_IFC_SHFT;
219
220 switch (frqcr_ifc) {
221 case FRQCR_IFC_1P1:
222 SystemCoreClock = CM0_RENESAS_RZ_A1_I_CLK;
223 break;
224 case FRQCR_IFC_2P3:
225 SystemCoreClock = CM0_RENESAS_RZ_A1_I_CLK * 2 / 3;
226 break;
227 case FRQCR_IFC_1P3:
228 SystemCoreClock = CM0_RENESAS_RZ_A1_I_CLK / 3;
229 break;
230 default:
231 /* do nothing */
232 break;
233 }
234}
235
236
237/**
238 * Initialize the system
239 *
240 * @param none
241 * @return none
242 *
243 * @brief Setup the microcontroller system.
244 * Initialize the System.
245 */
246void SystemInit (void)
247{
248 IRQNestLevel = 0;
249/* do not use global variables because this function is called before
250 reaching pre-main. RW section maybe overwritten afterwards. */
251 RZ_A1_InitClock();
252 RZ_A1_InitBus();
253
254 //Configure GIC ICDICFR GIC_SetICDICFR()
255 GIC_Enable();
256 __enable_irq();
257
258}
259
260
261//Fault Status Register (IFSR/DFSR) definitions
262#define FSR_ALIGNMENT_FAULT 0x01 //DFSR only. Fault on first lookup
263#define FSR_INSTRUCTION_CACHE_MAINTENANCE 0x04 //DFSR only - async/external
264#define FSR_SYNC_EXT_TTB_WALK_FIRST 0x0c //sync/external
265#define FSR_SYNC_EXT_TTB_WALK_SECOND 0x0e //sync/external
266#define FSR_SYNC_PARITY_TTB_WALK_FIRST 0x1c //sync/external
267#define FSR_SYNC_PARITY_TTB_WALK_SECOND 0x1e //sync/external
268#define FSR_TRANSLATION_FAULT_FIRST 0x05 //MMU Fault - internal
269#define FSR_TRANSLATION_FAULT_SECOND 0x07 //MMU Fault - internal
270#define FSR_ACCESS_FLAG_FAULT_FIRST 0x03 //MMU Fault - internal
271#define FSR_ACCESS_FLAG_FAULT_SECOND 0x06 //MMU Fault - internal
272#define FSR_DOMAIN_FAULT_FIRST 0x09 //MMU Fault - internal
273#define FSR_DOMAIN_FAULT_SECOND 0x0b //MMU Fault - internal
274#define FSR_PERMISION_FAULT_FIRST 0x0f //MMU Fault - internal
275#define FSR_PERMISION_FAULT_SECOND 0x0d //MMU Fault - internal
276#define FSR_DEBUG_EVENT 0x02 //internal
277#define FSR_SYNC_EXT_ABORT 0x08 //sync/external
278#define FSR_TLB_CONFLICT_ABORT 0x10 //sync/external
279#define FSR_LOCKDOWN 0x14 //internal
280#define FSR_COPROCESSOR_ABORT 0x1a //internal
281#define FSR_SYNC_PARITY_ERROR 0x19 //sync/external
282#define FSR_ASYNC_EXTERNAL_ABORT 0x16 //DFSR only - async/external
283#define FSR_ASYNC_PARITY_ERROR 0x18 //DFSR only - async/external
284
285void CDAbtHandler(uint32_t DFSR, uint32_t DFAR, uint32_t LR) {
286 uint32_t FS = (DFSR & (1 << 10)) >> 6 | (DFSR & 0x0f); //Store Fault Status
287
288 switch(FS) {
289 //Synchronous parity errors - retry
290 case FSR_SYNC_PARITY_ERROR:
291 case FSR_SYNC_PARITY_TTB_WALK_FIRST:
292 case FSR_SYNC_PARITY_TTB_WALK_SECOND:
293 return;
294
295 //Your code here. Value in DFAR is invalid for some fault statuses.
296 case FSR_ALIGNMENT_FAULT:
297 case FSR_INSTRUCTION_CACHE_MAINTENANCE:
298 case FSR_SYNC_EXT_TTB_WALK_FIRST:
299 case FSR_SYNC_EXT_TTB_WALK_SECOND:
300 case FSR_TRANSLATION_FAULT_FIRST:
301 case FSR_TRANSLATION_FAULT_SECOND:
302 case FSR_ACCESS_FLAG_FAULT_FIRST:
303 case FSR_ACCESS_FLAG_FAULT_SECOND:
304 case FSR_DOMAIN_FAULT_FIRST:
305 case FSR_DOMAIN_FAULT_SECOND:
306 case FSR_PERMISION_FAULT_FIRST:
307 case FSR_PERMISION_FAULT_SECOND:
308 case FSR_DEBUG_EVENT:
309 case FSR_SYNC_EXT_ABORT:
310 case FSR_TLB_CONFLICT_ABORT:
311 case FSR_LOCKDOWN:
312 case FSR_COPROCESSOR_ABORT:
313 case FSR_ASYNC_EXTERNAL_ABORT: //DFAR invalid
314 case FSR_ASYNC_PARITY_ERROR: //DFAR invalid
315 default:
316 _kernel_default_exc_handler();
317 }
318}
319
320void CPAbtHandler(uint32_t IFSR, uint32_t IFAR, uint32_t LR) {
321 uint32_t FS = (IFSR & (1 << 10)) >> 6 | (IFSR & 0x0f); //Store Fault Status
322
323 switch(FS) {
324 //Synchronous parity errors - retry
325 case FSR_SYNC_PARITY_ERROR:
326 case FSR_SYNC_PARITY_TTB_WALK_FIRST:
327 case FSR_SYNC_PARITY_TTB_WALK_SECOND:
328 return;
329
330 //Your code here. Value in IFAR is invalid for some fault statuses.
331 case FSR_SYNC_EXT_TTB_WALK_FIRST:
332 case FSR_SYNC_EXT_TTB_WALK_SECOND:
333 case FSR_TRANSLATION_FAULT_FIRST:
334 case FSR_TRANSLATION_FAULT_SECOND:
335 case FSR_ACCESS_FLAG_FAULT_FIRST:
336 case FSR_ACCESS_FLAG_FAULT_SECOND:
337 case FSR_DOMAIN_FAULT_FIRST:
338 case FSR_DOMAIN_FAULT_SECOND:
339 case FSR_PERMISION_FAULT_FIRST:
340 case FSR_PERMISION_FAULT_SECOND:
341 case FSR_DEBUG_EVENT: //IFAR invalid
342 case FSR_SYNC_EXT_ABORT:
343 case FSR_TLB_CONFLICT_ABORT:
344 case FSR_LOCKDOWN:
345 case FSR_COPROCESSOR_ABORT:
346 default:
347 _kernel_default_exc_handler();
348 }
349}
350
351//returns amount to decrement lr by
352//this will be 0 when we have emulated the instruction and want to execute the next instruction
353//this will be 2 when we have performed some maintenance and want to retry the instruction in Thumb (state == 2)
354//this will be 4 when we have performed some maintenance and want to retry the instruction in ARM (state == 4)
355uint32_t CUndefHandler(uint32_t opcode, uint32_t state, uint32_t LR) {
356 const unsigned int THUMB = 2;
357 const unsigned int ARM = 4;
358 //Lazy VFP/NEON initialisation and switching
359
360 // (ARM ARM section A7.5) VFP data processing instruction?
361 // (ARM ARM section A7.6) VFP/NEON register load/store instruction?
362 // (ARM ARM section A7.8) VFP/NEON register data transfer instruction?
363 // (ARM ARM section A7.9) VFP/NEON 64-bit register data transfer instruction?
364 if ((state == ARM && ((opcode & 0x0C000000) >> 26 == 0x03)) ||
365 (state == THUMB && ((opcode & 0xEC000000) >> 26 == 0x3B))) {
366 if (((opcode & 0x00000E00) >> 9) == 5) {
367 FPUEnable();
368 return state;
369 }
370 }
371
372 // (ARM ARM section A7.4) NEON data processing instruction?
373 if ((state == ARM && ((opcode & 0xFE000000) >> 24 == 0xF2)) ||
374 (state == THUMB && ((opcode & 0xEF000000) >> 24 == 0xEF)) ||
375 // (ARM ARM section A7.7) NEON load/store instruction?
376 (state == ARM && ((opcode >> 24) == 0xF4)) ||
377 (state == THUMB && ((opcode >> 24) == 0xF9))) {
378 FPUEnable();
379 return state;
380 }
381
382 //Add code here for other Undef cases
383 _kernel_default_exc_handler();
384 return 0;
385}
386
387#if defined(__ARMCC_VERSION)
388#pragma push
389#pragma arm
390//Critical section, called from undef handler, so systick is disabled
391__asm void FPUEnable(void) {
392 ARM
393
394 //Permit access to VFP/NEON, registers by modifying CPACR
395 MRC p15,0,R1,c1,c0,2
396 ORR R1,R1,#0x00F00000
397 MCR p15,0,R1,c1,c0,2
398
399 //Ensure that subsequent instructions occur in the context of VFP/NEON access permitted
400 ISB
401
402 //Enable VFP/NEON
403 VMRS R1,FPEXC
404 ORR R1,R1,#0x40000000
405 VMSR FPEXC,R1
406
407 //Initialise VFP/NEON registers to 0
408 MOV R2,#0
409 //Initialise D16 registers to 0
410 VMOV D0, R2,R2
411 VMOV D1, R2,R2
412 VMOV D2, R2,R2
413 VMOV D3, R2,R2
414 VMOV D4, R2,R2
415 VMOV D5, R2,R2
416 VMOV D6, R2,R2
417 VMOV D7, R2,R2
418 VMOV D8, R2,R2
419 VMOV D9, R2,R2
420 VMOV D10,R2,R2
421 VMOV D11,R2,R2
422 VMOV D12,R2,R2
423 VMOV D13,R2,R2
424 VMOV D14,R2,R2
425 VMOV D15,R2,R2
426 //Initialise D32 registers to 0
427 VMOV D16,R2,R2
428 VMOV D17,R2,R2
429 VMOV D18,R2,R2
430 VMOV D19,R2,R2
431 VMOV D20,R2,R2
432 VMOV D21,R2,R2
433 VMOV D22,R2,R2
434 VMOV D23,R2,R2
435 VMOV D24,R2,R2
436 VMOV D25,R2,R2
437 VMOV D26,R2,R2
438 VMOV D27,R2,R2
439 VMOV D28,R2,R2
440 VMOV D29,R2,R2
441 VMOV D30,R2,R2
442 VMOV D31,R2,R2
443 //Initialise FPSCR to a known state
444 VMRS R2,FPSCR
445 LDR R3,=0x00086060 //Mask off all bits that do not have to be preserved. Non-preserved bits can/should be zero.
446 AND R2,R2,R3
447 VMSR FPSCR,R2
448
449 BX LR
450}
451#pragma pop
452
453#elif defined(__GNUC__)
454void FPUEnable(void) {
455 __asm__ (
456 ".ARM;"
457
458 //Permit access to VFP/NEON, registers by modifying CPACR
459 "MRC p15,0,R1,c1,c0,2;"
460 "ORR R1,R1,#0x00F00000;"
461 "MCR p15,0,R1,c1,c0,2;"
462
463 //Ensure that subsequent instructions occur in the context of VFP/NEON access permitted
464 "ISB;"
465
466 //Enable VFP/NEON
467 "VMRS R1,FPEXC;"
468 "ORR R1,R1,#0x40000000;"
469 "VMSR FPEXC,R1;"
470
471 //Initialise VFP/NEON registers to 0
472 "MOV R2,#0;"
473 //Initialise D16 registers to 0
474 "VMOV D0, R2,R2;"
475 "VMOV D1, R2,R2;"
476 "VMOV D2, R2,R2;"
477 "VMOV D3, R2,R2;"
478 "VMOV D4, R2,R2;"
479 "VMOV D5, R2,R2;"
480 "VMOV D6, R2,R2;"
481 "VMOV D7, R2,R2;"
482 "VMOV D8, R2,R2;"
483 "VMOV D9, R2,R2;"
484 "VMOV D10,R2,R2;"
485 "VMOV D11,R2,R2;"
486 "VMOV D12,R2,R2;"
487 "VMOV D13,R2,R2;"
488 "VMOV D14,R2,R2;"
489 "VMOV D15,R2,R2;"
490 //Initialise D32 registers to 0
491 "VMOV D16,R2,R2;"
492 "VMOV D17,R2,R2;"
493 "VMOV D18,R2,R2;"
494 "VMOV D19,R2,R2;"
495 "VMOV D20,R2,R2;"
496 "VMOV D21,R2,R2;"
497 "VMOV D22,R2,R2;"
498 "VMOV D23,R2,R2;"
499 "VMOV D24,R2,R2;"
500 "VMOV D25,R2,R2;"
501 "VMOV D26,R2,R2;"
502 "VMOV D27,R2,R2;"
503 "VMOV D28,R2,R2;"
504 "VMOV D29,R2,R2;"
505 "VMOV D30,R2,R2;"
506 "VMOV D31,R2,R2;"
507
508 //Initialise FPSCR to a known state
509 "VMRS R2,FPSCR;"
510 "LDR R3,=0x00086060;" //Mask off all bits that do not have to be preserved. Non-preserved bits can/should be zero.
511 "AND R2,R2,R3;"
512 "VMSR FPSCR,R2;"
513
514 //"BX LR;"
515 :
516 :
517 :"r1", "r2", "r3");
518 return;
519}
520#else
521#endif
522
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