[352] | 1 | /*******************************************************************************
|
---|
| 2 | * DISCLAIMER
|
---|
| 3 | * This software is supplied by Renesas Electronics Corporation and is only
|
---|
| 4 | * intended for use with Renesas products. No other uses are authorized. This
|
---|
| 5 | * software is owned by Renesas Electronics Corporation and is protected under
|
---|
| 6 | * all applicable laws, including copyright laws.
|
---|
| 7 | * THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
|
---|
| 8 | * THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
|
---|
| 9 | * LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
|
---|
| 10 | * AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
|
---|
| 11 | * TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
|
---|
| 12 | * ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
|
---|
| 13 | * FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
|
---|
| 14 | * ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
|
---|
| 15 | * BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
|
---|
| 16 | * Renesas reserves the right, without notice, to make changes to this software
|
---|
| 17 | * and to discontinue the availability of this software. By using this software,
|
---|
| 18 | * you agree to the additional terms and conditions found by accessing the
|
---|
| 19 | * following link:
|
---|
| 20 | * http://www.renesas.com/disclaimer*
|
---|
| 21 | * Copyright (C) 2013-2014 Renesas Electronics Corporation. All rights reserved.
|
---|
| 22 | *******************************************************************************/
|
---|
| 23 | /*******************************************************************************
|
---|
| 24 | * File Name : vdc5_iodefine.h
|
---|
| 25 | * $Rev: $
|
---|
| 26 | * $Date:: $
|
---|
| 27 | * Description : Definition of I/O Register (V1.00a)
|
---|
| 28 | ******************************************************************************/
|
---|
| 29 | #ifndef VDC5_IODEFINE_H
|
---|
| 30 | #define VDC5_IODEFINE_H
|
---|
| 31 | /* ->QAC 0639 : Over 127 members (C90) */
|
---|
| 32 | /* ->SEC M1.10.1 : Not magic number */
|
---|
| 33 |
|
---|
| 34 | struct st_vdc5
|
---|
| 35 | { /* VDC5 */
|
---|
| 36 | volatile uint32_t INP_UPDATE; /* INP_UPDATE */
|
---|
| 37 | volatile uint32_t INP_SEL_CNT; /* INP_SEL_CNT */
|
---|
| 38 | volatile uint32_t INP_EXT_SYNC_CNT; /* INP_EXT_SYNC_CNT */
|
---|
| 39 | volatile uint32_t INP_VSYNC_PH_ADJ; /* INP_VSYNC_PH_ADJ */
|
---|
| 40 | volatile uint32_t INP_DLY_ADJ; /* INP_DLY_ADJ */
|
---|
| 41 | volatile uint8_t dummy1[108]; /* */
|
---|
| 42 | volatile uint32_t IMGCNT_UPDATE; /* IMGCNT_UPDATE */
|
---|
| 43 | #define VDC5_IMGCNT_NR_CNT0_COUNT 2
|
---|
| 44 | volatile uint32_t IMGCNT_NR_CNT0; /* IMGCNT_NR_CNT0 */
|
---|
| 45 | volatile uint32_t IMGCNT_NR_CNT1; /* IMGCNT_NR_CNT1 */
|
---|
| 46 | volatile uint8_t dummy2[20]; /* */
|
---|
| 47 | volatile uint32_t IMGCNT_MTX_MODE; /* IMGCNT_MTX_MODE */
|
---|
| 48 | volatile uint32_t IMGCNT_MTX_YG_ADJ0; /* IMGCNT_MTX_YG_ADJ0 */
|
---|
| 49 | volatile uint32_t IMGCNT_MTX_YG_ADJ1; /* IMGCNT_MTX_YG_ADJ1 */
|
---|
| 50 | volatile uint32_t IMGCNT_MTX_CBB_ADJ0; /* IMGCNT_MTX_CBB_ADJ0 */
|
---|
| 51 | volatile uint32_t IMGCNT_MTX_CBB_ADJ1; /* IMGCNT_MTX_CBB_ADJ1 */
|
---|
| 52 | volatile uint32_t IMGCNT_MTX_CRR_ADJ0; /* IMGCNT_MTX_CRR_ADJ0 */
|
---|
| 53 | volatile uint32_t IMGCNT_MTX_CRR_ADJ1; /* IMGCNT_MTX_CRR_ADJ1 */
|
---|
| 54 | volatile uint8_t dummy3[4]; /* */
|
---|
| 55 | volatile uint32_t IMGCNT_DRC_REG; /* IMGCNT_DRC_REG */
|
---|
| 56 | volatile uint8_t dummy4[60]; /* */
|
---|
| 57 | /* start of struct st_vdc5_from_sc0_scl0_update */
|
---|
| 58 | volatile uint32_t SC0_SCL0_UPDATE; /* SC0_SCL0_UPDATE */
|
---|
| 59 | #define VDC5_SC0_SCL0_FRC1_COUNT 7
|
---|
| 60 | volatile uint32_t SC0_SCL0_FRC1; /* SC0_SCL0_FRC1 */
|
---|
| 61 | volatile uint32_t SC0_SCL0_FRC2; /* SC0_SCL0_FRC2 */
|
---|
| 62 | volatile uint32_t SC0_SCL0_FRC3; /* SC0_SCL0_FRC3 */
|
---|
| 63 | volatile uint32_t SC0_SCL0_FRC4; /* SC0_SCL0_FRC4 */
|
---|
| 64 | volatile uint32_t SC0_SCL0_FRC5; /* SC0_SCL0_FRC5 */
|
---|
| 65 | volatile uint32_t SC0_SCL0_FRC6; /* SC0_SCL0_FRC6 */
|
---|
| 66 | volatile uint32_t SC0_SCL0_FRC7; /* SC0_SCL0_FRC7 */
|
---|
| 67 | volatile uint8_t dummy5[4]; /* */
|
---|
| 68 | volatile uint32_t SC0_SCL0_FRC9; /* SC0_SCL0_FRC9 */
|
---|
| 69 | volatile uint16_t SC0_SCL0_MON0; /* SC0_SCL0_MON0 */
|
---|
| 70 | volatile uint16_t SC0_SCL0_INT; /* SC0_SCL0_INT */
|
---|
| 71 | #define VDC5_SC0_SCL0_DS1_COUNT 7
|
---|
| 72 | volatile uint32_t SC0_SCL0_DS1; /* SC0_SCL0_DS1 */
|
---|
| 73 | volatile uint32_t SC0_SCL0_DS2; /* SC0_SCL0_DS2 */
|
---|
| 74 | volatile uint32_t SC0_SCL0_DS3; /* SC0_SCL0_DS3 */
|
---|
| 75 | volatile uint32_t SC0_SCL0_DS4; /* SC0_SCL0_DS4 */
|
---|
| 76 | volatile uint32_t SC0_SCL0_DS5; /* SC0_SCL0_DS5 */
|
---|
| 77 | volatile uint32_t SC0_SCL0_DS6; /* SC0_SCL0_DS6 */
|
---|
| 78 | volatile uint32_t SC0_SCL0_DS7; /* SC0_SCL0_DS7 */
|
---|
| 79 | #define VDC5_SC0_SCL0_US1_COUNT 8
|
---|
| 80 | volatile uint32_t SC0_SCL0_US1; /* SC0_SCL0_US1 */
|
---|
| 81 | volatile uint32_t SC0_SCL0_US2; /* SC0_SCL0_US2 */
|
---|
| 82 | volatile uint32_t SC0_SCL0_US3; /* SC0_SCL0_US3 */
|
---|
| 83 | volatile uint32_t SC0_SCL0_US4; /* SC0_SCL0_US4 */
|
---|
| 84 | volatile uint32_t SC0_SCL0_US5; /* SC0_SCL0_US5 */
|
---|
| 85 | volatile uint32_t SC0_SCL0_US6; /* SC0_SCL0_US6 */
|
---|
| 86 | volatile uint32_t SC0_SCL0_US7; /* SC0_SCL0_US7 */
|
---|
| 87 | volatile uint32_t SC0_SCL0_US8; /* SC0_SCL0_US8 */
|
---|
| 88 | volatile uint8_t dummy6[4]; /* */
|
---|
| 89 | volatile uint32_t SC0_SCL0_OVR1; /* SC0_SCL0_OVR1 */
|
---|
| 90 | volatile uint8_t dummy7[16]; /* */
|
---|
| 91 | volatile uint32_t SC0_SCL1_UPDATE; /* SC0_SCL1_UPDATE */
|
---|
| 92 | volatile uint8_t dummy8[4]; /* */
|
---|
| 93 | #define VDC5_SC0_SCL1_WR1_COUNT 4
|
---|
| 94 | volatile uint32_t SC0_SCL1_WR1; /* SC0_SCL1_WR1 */
|
---|
| 95 | volatile uint32_t SC0_SCL1_WR2; /* SC0_SCL1_WR2 */
|
---|
| 96 | volatile uint32_t SC0_SCL1_WR3; /* SC0_SCL1_WR3 */
|
---|
| 97 | volatile uint32_t SC0_SCL1_WR4; /* SC0_SCL1_WR4 */
|
---|
| 98 | volatile uint8_t dummy9[4]; /* */
|
---|
| 99 | volatile uint32_t SC0_SCL1_WR5; /* SC0_SCL1_WR5 */
|
---|
| 100 | volatile uint32_t SC0_SCL1_WR6; /* SC0_SCL1_WR6 */
|
---|
| 101 | volatile uint32_t SC0_SCL1_WR7; /* SC0_SCL1_WR7 */
|
---|
| 102 | volatile uint32_t SC0_SCL1_WR8; /* SC0_SCL1_WR8 */
|
---|
| 103 | volatile uint32_t SC0_SCL1_WR9; /* SC0_SCL1_WR9 */
|
---|
| 104 | volatile uint32_t SC0_SCL1_WR10; /* SC0_SCL1_WR10 */
|
---|
| 105 | /* end of struct st_vdc5_from_sc0_scl0_update */
|
---|
| 106 | volatile uint32_t SC0_SCL1_WR11; /* SC0_SCL1_WR11 */
|
---|
| 107 | volatile uint32_t SC0_SCL1_MON1; /* SC0_SCL1_MON1 */
|
---|
| 108 | /* start of struct st_vdc5_from_sc0_scl1_pbuf0 */
|
---|
| 109 | #define VDC5_SC0_SCL1_PBUF0_COUNT 4
|
---|
| 110 | volatile uint32_t SC0_SCL1_PBUF0; /* SC0_SCL1_PBUF0 */
|
---|
| 111 | volatile uint32_t SC0_SCL1_PBUF1; /* SC0_SCL1_PBUF1 */
|
---|
| 112 | volatile uint32_t SC0_SCL1_PBUF2; /* SC0_SCL1_PBUF2 */
|
---|
| 113 | volatile uint32_t SC0_SCL1_PBUF3; /* SC0_SCL1_PBUF3 */
|
---|
| 114 | volatile uint32_t SC0_SCL1_PBUF_FLD; /* SC0_SCL1_PBUF_FLD */
|
---|
| 115 | volatile uint32_t SC0_SCL1_PBUF_CNT; /* SC0_SCL1_PBUF_CNT */
|
---|
| 116 | /* end of struct st_vdc5_from_sc0_scl1_pbuf0 */
|
---|
| 117 | volatile uint8_t dummy10[44]; /* */
|
---|
| 118 | /* start of struct st_vdc5_from_gr0_update */
|
---|
| 119 | volatile uint32_t GR0_UPDATE; /* GR0_UPDATE */
|
---|
| 120 | volatile uint32_t GR0_FLM_RD; /* GR0_FLM_RD */
|
---|
| 121 | #define VDC5_GR0_FLM1_COUNT 6
|
---|
| 122 | volatile uint32_t GR0_FLM1; /* GR0_FLM1 */
|
---|
| 123 | volatile uint32_t GR0_FLM2; /* GR0_FLM2 */
|
---|
| 124 | volatile uint32_t GR0_FLM3; /* GR0_FLM3 */
|
---|
| 125 | volatile uint32_t GR0_FLM4; /* GR0_FLM4 */
|
---|
| 126 | volatile uint32_t GR0_FLM5; /* GR0_FLM5 */
|
---|
| 127 | volatile uint32_t GR0_FLM6; /* GR0_FLM6 */
|
---|
| 128 | #define VDC5_GR0_AB1_COUNT 3
|
---|
| 129 | volatile uint32_t GR0_AB1; /* GR0_AB1 */
|
---|
| 130 | volatile uint32_t GR0_AB2; /* GR0_AB2 */
|
---|
| 131 | volatile uint32_t GR0_AB3; /* GR0_AB3 */
|
---|
| 132 | /* end of struct st_vdc5_from_gr0_update */
|
---|
| 133 | volatile uint8_t dummy11[12]; /* */
|
---|
| 134 | /* start of struct st_vdc5_from_gr0_ab7 */
|
---|
| 135 | volatile uint32_t GR0_AB7; /* GR0_AB7 */
|
---|
| 136 | volatile uint32_t GR0_AB8; /* GR0_AB8 */
|
---|
| 137 | volatile uint32_t GR0_AB9; /* GR0_AB9 */
|
---|
| 138 | volatile uint32_t GR0_AB10; /* GR0_AB10 */
|
---|
| 139 | volatile uint32_t GR0_AB11; /* GR0_AB11 */
|
---|
| 140 | volatile uint32_t GR0_BASE; /* GR0_BASE */
|
---|
| 141 | /* end of struct st_vdc5_from_gr0_ab7 */
|
---|
| 142 | volatile uint32_t GR0_CLUT; /* GR0_CLUT */
|
---|
| 143 | volatile uint8_t dummy12[44]; /* */
|
---|
| 144 | /* start of struct st_vdc5_from_adj0_update */
|
---|
| 145 | volatile uint32_t ADJ0_UPDATE; /* ADJ0_UPDATE */
|
---|
| 146 | volatile uint32_t ADJ0_BKSTR_SET; /* ADJ0_BKSTR_SET */
|
---|
| 147 | #define VDC5_ADJ0_ENH_TIM1_COUNT 3
|
---|
| 148 | volatile uint32_t ADJ0_ENH_TIM1; /* ADJ0_ENH_TIM1 */
|
---|
| 149 | volatile uint32_t ADJ0_ENH_TIM2; /* ADJ0_ENH_TIM2 */
|
---|
| 150 | volatile uint32_t ADJ0_ENH_TIM3; /* ADJ0_ENH_TIM3 */
|
---|
| 151 | #define VDC5_ADJ0_ENH_SHP1_COUNT 6
|
---|
| 152 | volatile uint32_t ADJ0_ENH_SHP1; /* ADJ0_ENH_SHP1 */
|
---|
| 153 | volatile uint32_t ADJ0_ENH_SHP2; /* ADJ0_ENH_SHP2 */
|
---|
| 154 | volatile uint32_t ADJ0_ENH_SHP3; /* ADJ0_ENH_SHP3 */
|
---|
| 155 | volatile uint32_t ADJ0_ENH_SHP4; /* ADJ0_ENH_SHP4 */
|
---|
| 156 | volatile uint32_t ADJ0_ENH_SHP5; /* ADJ0_ENH_SHP5 */
|
---|
| 157 | volatile uint32_t ADJ0_ENH_SHP6; /* ADJ0_ENH_SHP6 */
|
---|
| 158 | #define VDC5_ADJ0_ENH_LTI1_COUNT 2
|
---|
| 159 | volatile uint32_t ADJ0_ENH_LTI1; /* ADJ0_ENH_LTI1 */
|
---|
| 160 | volatile uint32_t ADJ0_ENH_LTI2; /* ADJ0_ENH_LTI2 */
|
---|
| 161 | volatile uint32_t ADJ0_MTX_MODE; /* ADJ0_MTX_MODE */
|
---|
| 162 | volatile uint32_t ADJ0_MTX_YG_ADJ0; /* ADJ0_MTX_YG_ADJ0 */
|
---|
| 163 | volatile uint32_t ADJ0_MTX_YG_ADJ1; /* ADJ0_MTX_YG_ADJ1 */
|
---|
| 164 | volatile uint32_t ADJ0_MTX_CBB_ADJ0; /* ADJ0_MTX_CBB_ADJ0 */
|
---|
| 165 | volatile uint32_t ADJ0_MTX_CBB_ADJ1; /* ADJ0_MTX_CBB_ADJ1 */
|
---|
| 166 | volatile uint32_t ADJ0_MTX_CRR_ADJ0; /* ADJ0_MTX_CRR_ADJ0 */
|
---|
| 167 | volatile uint32_t ADJ0_MTX_CRR_ADJ1; /* ADJ0_MTX_CRR_ADJ1 */
|
---|
| 168 | /* end of struct st_vdc5_from_adj0_update */
|
---|
| 169 | volatile uint8_t dummy13[48]; /* */
|
---|
| 170 | /* start of struct st_vdc5_from_gr0_update */
|
---|
| 171 | volatile uint32_t GR2_UPDATE; /* GR2_UPDATE */
|
---|
| 172 | volatile uint32_t GR2_FLM_RD; /* GR2_FLM_RD */
|
---|
| 173 | #define VDC5_GR2_FLM1_COUNT 6
|
---|
| 174 | volatile uint32_t GR2_FLM1; /* GR2_FLM1 */
|
---|
| 175 | volatile uint32_t GR2_FLM2; /* GR2_FLM2 */
|
---|
| 176 | volatile uint32_t GR2_FLM3; /* GR2_FLM3 */
|
---|
| 177 | volatile uint32_t GR2_FLM4; /* GR2_FLM4 */
|
---|
| 178 | volatile uint32_t GR2_FLM5; /* GR2_FLM5 */
|
---|
| 179 | volatile uint32_t GR2_FLM6; /* GR2_FLM6 */
|
---|
| 180 | #define VDC5_GR2_AB1_COUNT 3
|
---|
| 181 | volatile uint32_t GR2_AB1; /* GR2_AB1 */
|
---|
| 182 | volatile uint32_t GR2_AB2; /* GR2_AB2 */
|
---|
| 183 | volatile uint32_t GR2_AB3; /* GR2_AB3 */
|
---|
| 184 | /* end of struct st_vdc5_from_gr0_update */
|
---|
| 185 | volatile uint32_t GR2_AB4; /* GR2_AB4 */
|
---|
| 186 | volatile uint32_t GR2_AB5; /* GR2_AB5 */
|
---|
| 187 | volatile uint32_t GR2_AB6; /* GR2_AB6 */
|
---|
| 188 | /* start of struct st_vdc5_from_gr0_ab7 */
|
---|
| 189 | volatile uint32_t GR2_AB7; /* GR2_AB7 */
|
---|
| 190 | volatile uint32_t GR2_AB8; /* GR2_AB8 */
|
---|
| 191 | volatile uint32_t GR2_AB9; /* GR2_AB9 */
|
---|
| 192 | volatile uint32_t GR2_AB10; /* GR2_AB10 */
|
---|
| 193 | volatile uint32_t GR2_AB11; /* GR2_AB11 */
|
---|
| 194 | volatile uint32_t GR2_BASE; /* GR2_BASE */
|
---|
| 195 | /* end of struct st_vdc5_from_gr0_ab7 */
|
---|
| 196 | volatile uint32_t GR2_CLUT; /* GR2_CLUT */
|
---|
| 197 | volatile uint32_t GR2_MON; /* GR2_MON */
|
---|
| 198 | volatile uint8_t dummy14[40]; /* */
|
---|
| 199 | /* start of struct st_vdc5_from_gr0_update */
|
---|
| 200 | volatile uint32_t GR3_UPDATE; /* GR3_UPDATE */
|
---|
| 201 | volatile uint32_t GR3_FLM_RD; /* GR3_FLM_RD */
|
---|
| 202 | #define VDC5_GR3_FLM1_COUNT 6
|
---|
| 203 | volatile uint32_t GR3_FLM1; /* GR3_FLM1 */
|
---|
| 204 | volatile uint32_t GR3_FLM2; /* GR3_FLM2 */
|
---|
| 205 | volatile uint32_t GR3_FLM3; /* GR3_FLM3 */
|
---|
| 206 | volatile uint32_t GR3_FLM4; /* GR3_FLM4 */
|
---|
| 207 | volatile uint32_t GR3_FLM5; /* GR3_FLM5 */
|
---|
| 208 | volatile uint32_t GR3_FLM6; /* GR3_FLM6 */
|
---|
| 209 | #define VDC5_GR3_AB1_COUNT 3
|
---|
| 210 | volatile uint32_t GR3_AB1; /* GR3_AB1 */
|
---|
| 211 | volatile uint32_t GR3_AB2; /* GR3_AB2 */
|
---|
| 212 | volatile uint32_t GR3_AB3; /* GR3_AB3 */
|
---|
| 213 | /* end of struct st_vdc5_from_gr0_update */
|
---|
| 214 | volatile uint32_t GR3_AB4; /* GR3_AB4 */
|
---|
| 215 | volatile uint32_t GR3_AB5; /* GR3_AB5 */
|
---|
| 216 | volatile uint32_t GR3_AB6; /* GR3_AB6 */
|
---|
| 217 | /* start of struct st_vdc5_from_gr0_ab7 */
|
---|
| 218 | volatile uint32_t GR3_AB7; /* GR3_AB7 */
|
---|
| 219 | volatile uint32_t GR3_AB8; /* GR3_AB8 */
|
---|
| 220 | volatile uint32_t GR3_AB9; /* GR3_AB9 */
|
---|
| 221 | volatile uint32_t GR3_AB10; /* GR3_AB10 */
|
---|
| 222 | volatile uint32_t GR3_AB11; /* GR3_AB11 */
|
---|
| 223 | volatile uint32_t GR3_BASE; /* GR3_BASE */
|
---|
| 224 | /* end of struct st_vdc5_from_gr0_ab7 */
|
---|
| 225 | volatile uint32_t GR3_CLUT_INT; /* GR3_CLUT_INT */
|
---|
| 226 | volatile uint32_t GR3_MON; /* GR3_MON */
|
---|
| 227 | volatile uint8_t dummy15[40]; /* */
|
---|
| 228 | volatile uint32_t GAM_G_UPDATE; /* GAM_G_UPDATE */
|
---|
| 229 | volatile uint32_t GAM_SW; /* GAM_SW */
|
---|
| 230 | #define VDC5_GAM_G_LUT1_COUNT 16
|
---|
| 231 | volatile uint32_t GAM_G_LUT1; /* GAM_G_LUT1 */
|
---|
| 232 | volatile uint32_t GAM_G_LUT2; /* GAM_G_LUT2 */
|
---|
| 233 | volatile uint32_t GAM_G_LUT3; /* GAM_G_LUT3 */
|
---|
| 234 | volatile uint32_t GAM_G_LUT4; /* GAM_G_LUT4 */
|
---|
| 235 | volatile uint32_t GAM_G_LUT5; /* GAM_G_LUT5 */
|
---|
| 236 | volatile uint32_t GAM_G_LUT6; /* GAM_G_LUT6 */
|
---|
| 237 | volatile uint32_t GAM_G_LUT7; /* GAM_G_LUT7 */
|
---|
| 238 | volatile uint32_t GAM_G_LUT8; /* GAM_G_LUT8 */
|
---|
| 239 | volatile uint32_t GAM_G_LUT9; /* GAM_G_LUT9 */
|
---|
| 240 | volatile uint32_t GAM_G_LUT10; /* GAM_G_LUT10 */
|
---|
| 241 | volatile uint32_t GAM_G_LUT11; /* GAM_G_LUT11 */
|
---|
| 242 | volatile uint32_t GAM_G_LUT12; /* GAM_G_LUT12 */
|
---|
| 243 | volatile uint32_t GAM_G_LUT13; /* GAM_G_LUT13 */
|
---|
| 244 | volatile uint32_t GAM_G_LUT14; /* GAM_G_LUT14 */
|
---|
| 245 | volatile uint32_t GAM_G_LUT15; /* GAM_G_LUT15 */
|
---|
| 246 | volatile uint32_t GAM_G_LUT16; /* GAM_G_LUT16 */
|
---|
| 247 | #define VDC5_GAM_G_AREA1_COUNT 8
|
---|
| 248 | volatile uint32_t GAM_G_AREA1; /* GAM_G_AREA1 */
|
---|
| 249 | volatile uint32_t GAM_G_AREA2; /* GAM_G_AREA2 */
|
---|
| 250 | volatile uint32_t GAM_G_AREA3; /* GAM_G_AREA3 */
|
---|
| 251 | volatile uint32_t GAM_G_AREA4; /* GAM_G_AREA4 */
|
---|
| 252 | volatile uint32_t GAM_G_AREA5; /* GAM_G_AREA5 */
|
---|
| 253 | volatile uint32_t GAM_G_AREA6; /* GAM_G_AREA6 */
|
---|
| 254 | volatile uint32_t GAM_G_AREA7; /* GAM_G_AREA7 */
|
---|
| 255 | volatile uint32_t GAM_G_AREA8; /* GAM_G_AREA8 */
|
---|
| 256 | volatile uint8_t dummy16[24]; /* */
|
---|
| 257 | volatile uint32_t GAM_B_UPDATE; /* GAM_B_UPDATE */
|
---|
| 258 | volatile uint8_t dummy17[4]; /* */
|
---|
| 259 | #define VDC5_GAM_B_LUT1_COUNT 16
|
---|
| 260 | volatile uint32_t GAM_B_LUT1; /* GAM_B_LUT1 */
|
---|
| 261 | volatile uint32_t GAM_B_LUT2; /* GAM_B_LUT2 */
|
---|
| 262 | volatile uint32_t GAM_B_LUT3; /* GAM_B_LUT3 */
|
---|
| 263 | volatile uint32_t GAM_B_LUT4; /* GAM_B_LUT4 */
|
---|
| 264 | volatile uint32_t GAM_B_LUT5; /* GAM_B_LUT5 */
|
---|
| 265 | volatile uint32_t GAM_B_LUT6; /* GAM_B_LUT6 */
|
---|
| 266 | volatile uint32_t GAM_B_LUT7; /* GAM_B_LUT7 */
|
---|
| 267 | volatile uint32_t GAM_B_LUT8; /* GAM_B_LUT8 */
|
---|
| 268 | volatile uint32_t GAM_B_LUT9; /* GAM_B_LUT9 */
|
---|
| 269 | volatile uint32_t GAM_B_LUT10; /* GAM_B_LUT10 */
|
---|
| 270 | volatile uint32_t GAM_B_LUT11; /* GAM_B_LUT11 */
|
---|
| 271 | volatile uint32_t GAM_B_LUT12; /* GAM_B_LUT12 */
|
---|
| 272 | volatile uint32_t GAM_B_LUT13; /* GAM_B_LUT13 */
|
---|
| 273 | volatile uint32_t GAM_B_LUT14; /* GAM_B_LUT14 */
|
---|
| 274 | volatile uint32_t GAM_B_LUT15; /* GAM_B_LUT15 */
|
---|
| 275 | volatile uint32_t GAM_B_LUT16; /* GAM_B_LUT16 */
|
---|
| 276 | #define VDC5_GAM_B_AREA1_COUNT 8
|
---|
| 277 | volatile uint32_t GAM_B_AREA1; /* GAM_B_AREA1 */
|
---|
| 278 | volatile uint32_t GAM_B_AREA2; /* GAM_B_AREA2 */
|
---|
| 279 | volatile uint32_t GAM_B_AREA3; /* GAM_B_AREA3 */
|
---|
| 280 | volatile uint32_t GAM_B_AREA4; /* GAM_B_AREA4 */
|
---|
| 281 | volatile uint32_t GAM_B_AREA5; /* GAM_B_AREA5 */
|
---|
| 282 | volatile uint32_t GAM_B_AREA6; /* GAM_B_AREA6 */
|
---|
| 283 | volatile uint32_t GAM_B_AREA7; /* GAM_B_AREA7 */
|
---|
| 284 | volatile uint32_t GAM_B_AREA8; /* GAM_B_AREA8 */
|
---|
| 285 | volatile uint8_t dummy18[24]; /* */
|
---|
| 286 | volatile uint32_t GAM_R_UPDATE; /* GAM_R_UPDATE */
|
---|
| 287 | volatile uint8_t dummy19[4]; /* */
|
---|
| 288 | #define VDC5_GAM_R_LUT1_COUNT 16
|
---|
| 289 | volatile uint32_t GAM_R_LUT1; /* GAM_R_LUT1 */
|
---|
| 290 | volatile uint32_t GAM_R_LUT2; /* GAM_R_LUT2 */
|
---|
| 291 | volatile uint32_t GAM_R_LUT3; /* GAM_R_LUT3 */
|
---|
| 292 | volatile uint32_t GAM_R_LUT4; /* GAM_R_LUT4 */
|
---|
| 293 | volatile uint32_t GAM_R_LUT5; /* GAM_R_LUT5 */
|
---|
| 294 | volatile uint32_t GAM_R_LUT6; /* GAM_R_LUT6 */
|
---|
| 295 | volatile uint32_t GAM_R_LUT7; /* GAM_R_LUT7 */
|
---|
| 296 | volatile uint32_t GAM_R_LUT8; /* GAM_R_LUT8 */
|
---|
| 297 | volatile uint32_t GAM_R_LUT9; /* GAM_R_LUT9 */
|
---|
| 298 | volatile uint32_t GAM_R_LUT10; /* GAM_R_LUT10 */
|
---|
| 299 | volatile uint32_t GAM_R_LUT11; /* GAM_R_LUT11 */
|
---|
| 300 | volatile uint32_t GAM_R_LUT12; /* GAM_R_LUT12 */
|
---|
| 301 | volatile uint32_t GAM_R_LUT13; /* GAM_R_LUT13 */
|
---|
| 302 | volatile uint32_t GAM_R_LUT14; /* GAM_R_LUT14 */
|
---|
| 303 | volatile uint32_t GAM_R_LUT15; /* GAM_R_LUT15 */
|
---|
| 304 | volatile uint32_t GAM_R_LUT16; /* GAM_R_LUT16 */
|
---|
| 305 | #define VDC5_GAM_R_AREA1_COUNT 8
|
---|
| 306 | volatile uint32_t GAM_R_AREA1; /* GAM_R_AREA1 */
|
---|
| 307 | volatile uint32_t GAM_R_AREA2; /* GAM_R_AREA2 */
|
---|
| 308 | volatile uint32_t GAM_R_AREA3; /* GAM_R_AREA3 */
|
---|
| 309 | volatile uint32_t GAM_R_AREA4; /* GAM_R_AREA4 */
|
---|
| 310 | volatile uint32_t GAM_R_AREA5; /* GAM_R_AREA5 */
|
---|
| 311 | volatile uint32_t GAM_R_AREA6; /* GAM_R_AREA6 */
|
---|
| 312 | volatile uint32_t GAM_R_AREA7; /* GAM_R_AREA7 */
|
---|
| 313 | volatile uint32_t GAM_R_AREA8; /* GAM_R_AREA8 */
|
---|
| 314 | volatile uint8_t dummy20[24]; /* */
|
---|
| 315 | volatile uint32_t TCON_UPDATE; /* TCON_UPDATE */
|
---|
| 316 | volatile uint32_t TCON_TIM; /* TCON_TIM */
|
---|
| 317 | #define VDC5_TCON_TIM_STVA1_COUNT 2
|
---|
| 318 | volatile uint32_t TCON_TIM_STVA1; /* TCON_TIM_STVA1 */
|
---|
| 319 | volatile uint32_t TCON_TIM_STVA2; /* TCON_TIM_STVA2 */
|
---|
| 320 | #define VDC5_TCON_TIM_STVB1_COUNT 2
|
---|
| 321 | volatile uint32_t TCON_TIM_STVB1; /* TCON_TIM_STVB1 */
|
---|
| 322 | volatile uint32_t TCON_TIM_STVB2; /* TCON_TIM_STVB2 */
|
---|
| 323 | #define VDC5_TCON_TIM_STH1_COUNT 2
|
---|
| 324 | volatile uint32_t TCON_TIM_STH1; /* TCON_TIM_STH1 */
|
---|
| 325 | volatile uint32_t TCON_TIM_STH2; /* TCON_TIM_STH2 */
|
---|
| 326 | #define VDC5_TCON_TIM_STB1_COUNT 2
|
---|
| 327 | volatile uint32_t TCON_TIM_STB1; /* TCON_TIM_STB1 */
|
---|
| 328 | volatile uint32_t TCON_TIM_STB2; /* TCON_TIM_STB2 */
|
---|
| 329 | #define VDC5_TCON_TIM_CPV1_COUNT 2
|
---|
| 330 | volatile uint32_t TCON_TIM_CPV1; /* TCON_TIM_CPV1 */
|
---|
| 331 | volatile uint32_t TCON_TIM_CPV2; /* TCON_TIM_CPV2 */
|
---|
| 332 | #define VDC5_TCON_TIM_POLA1_COUNT 2
|
---|
| 333 | volatile uint32_t TCON_TIM_POLA1; /* TCON_TIM_POLA1 */
|
---|
| 334 | volatile uint32_t TCON_TIM_POLA2; /* TCON_TIM_POLA2 */
|
---|
| 335 | #define VDC5_TCON_TIM_POLB1_COUNT 2
|
---|
| 336 | volatile uint32_t TCON_TIM_POLB1; /* TCON_TIM_POLB1 */
|
---|
| 337 | volatile uint32_t TCON_TIM_POLB2; /* TCON_TIM_POLB2 */
|
---|
| 338 | volatile uint32_t TCON_TIM_DE; /* TCON_TIM_DE */
|
---|
| 339 | volatile uint8_t dummy21[60]; /* */
|
---|
| 340 | volatile uint32_t OUT_UPDATE; /* OUT_UPDATE */
|
---|
| 341 | volatile uint32_t OUT_SET; /* OUT_SET */
|
---|
| 342 | #define VDC5_OUT_BRIGHT1_COUNT 2
|
---|
| 343 | volatile uint32_t OUT_BRIGHT1; /* OUT_BRIGHT1 */
|
---|
| 344 | volatile uint32_t OUT_BRIGHT2; /* OUT_BRIGHT2 */
|
---|
| 345 | volatile uint32_t OUT_CONTRAST; /* OUT_CONTRAST */
|
---|
| 346 | volatile uint32_t OUT_PDTHA; /* OUT_PDTHA */
|
---|
| 347 | volatile uint8_t dummy22[12]; /* */
|
---|
| 348 | volatile uint32_t OUT_CLK_PHASE; /* OUT_CLK_PHASE */
|
---|
| 349 | volatile uint8_t dummy23[88]; /* */
|
---|
| 350 | #define VDC5_SYSCNT_INT1_COUNT 6
|
---|
| 351 | volatile uint32_t SYSCNT_INT1; /* SYSCNT_INT1 */
|
---|
| 352 | volatile uint32_t SYSCNT_INT2; /* SYSCNT_INT2 */
|
---|
| 353 | volatile uint32_t SYSCNT_INT3; /* SYSCNT_INT3 */
|
---|
| 354 | volatile uint32_t SYSCNT_INT4; /* SYSCNT_INT4 */
|
---|
| 355 | volatile uint32_t SYSCNT_INT5; /* SYSCNT_INT5 */
|
---|
| 356 | volatile uint32_t SYSCNT_INT6; /* SYSCNT_INT6 */
|
---|
| 357 | volatile uint16_t SYSCNT_PANEL_CLK; /* SYSCNT_PANEL_CLK */
|
---|
| 358 | volatile uint16_t SYSCNT_CLUT; /* SYSCNT_CLUT */
|
---|
| 359 | volatile uint8_t dummy24[356]; /* */
|
---|
| 360 | /* start of struct st_vdc5_from_sc0_scl0_update */
|
---|
| 361 | volatile uint32_t SC1_SCL0_UPDATE; /* SC1_SCL0_UPDATE */
|
---|
| 362 | #define VDC5_SC1_SCL0_FRC1_COUNT 7
|
---|
| 363 | volatile uint32_t SC1_SCL0_FRC1; /* SC1_SCL0_FRC1 */
|
---|
| 364 | volatile uint32_t SC1_SCL0_FRC2; /* SC1_SCL0_FRC2 */
|
---|
| 365 | volatile uint32_t SC1_SCL0_FRC3; /* SC1_SCL0_FRC3 */
|
---|
| 366 | volatile uint32_t SC1_SCL0_FRC4; /* SC1_SCL0_FRC4 */
|
---|
| 367 | volatile uint32_t SC1_SCL0_FRC5; /* SC1_SCL0_FRC5 */
|
---|
| 368 | volatile uint32_t SC1_SCL0_FRC6; /* SC1_SCL0_FRC6 */
|
---|
| 369 | volatile uint32_t SC1_SCL0_FRC7; /* SC1_SCL0_FRC7 */
|
---|
| 370 | volatile uint8_t dummy25[4]; /* */
|
---|
| 371 | volatile uint32_t SC1_SCL0_FRC9; /* SC1_SCL0_FRC9 */
|
---|
| 372 | volatile uint16_t SC1_SCL0_MON0; /* SC1_SCL0_MON0 */
|
---|
| 373 | volatile uint16_t SC1_SCL0_INT; /* SC1_SCL0_INT */
|
---|
| 374 | #define VDC5_SC1_SC1_SCL0_DS1_COUNT 7
|
---|
| 375 | volatile uint32_t SC1_SCL0_DS1; /* SC1_SCL0_DS1 */
|
---|
| 376 | volatile uint32_t SC1_SCL0_DS2; /* SC1_SCL0_DS2 */
|
---|
| 377 | volatile uint32_t SC1_SCL0_DS3; /* SC1_SCL0_DS3 */
|
---|
| 378 | volatile uint32_t SC1_SCL0_DS4; /* SC1_SCL0_DS4 */
|
---|
| 379 | volatile uint32_t SC1_SCL0_DS5; /* SC1_SCL0_DS5 */
|
---|
| 380 | volatile uint32_t SC1_SCL0_DS6; /* SC1_SCL0_DS6 */
|
---|
| 381 | volatile uint32_t SC1_SCL0_DS7; /* SC1_SCL0_DS7 */
|
---|
| 382 | #define VDC5_SC1_SC1_SCL0_US1_COUNT 8
|
---|
| 383 | volatile uint32_t SC1_SCL0_US1; /* SC1_SCL0_US1 */
|
---|
| 384 | volatile uint32_t SC1_SCL0_US2; /* SC1_SCL0_US2 */
|
---|
| 385 | volatile uint32_t SC1_SCL0_US3; /* SC1_SCL0_US3 */
|
---|
| 386 | volatile uint32_t SC1_SCL0_US4; /* SC1_SCL0_US4 */
|
---|
| 387 | volatile uint32_t SC1_SCL0_US5; /* SC1_SCL0_US5 */
|
---|
| 388 | volatile uint32_t SC1_SCL0_US6; /* SC1_SCL0_US6 */
|
---|
| 389 | volatile uint32_t SC1_SCL0_US7; /* SC1_SCL0_US7 */
|
---|
| 390 | volatile uint32_t SC1_SCL0_US8; /* SC1_SCL0_US8 */
|
---|
| 391 | volatile uint8_t dummy26[4]; /* */
|
---|
| 392 | volatile uint32_t SC1_SCL0_OVR1; /* SC1_SCL0_OVR1 */
|
---|
| 393 | volatile uint8_t dummy27[16]; /* */
|
---|
| 394 | volatile uint32_t SC1_SCL1_UPDATE; /* SC1_SCL1_UPDATE */
|
---|
| 395 | volatile uint8_t dummy28[4]; /* */
|
---|
| 396 | #define VDC5_SC1_SCL1_WR1_COUNT 4
|
---|
| 397 | volatile uint32_t SC1_SCL1_WR1; /* SC1_SCL1_WR1 */
|
---|
| 398 | volatile uint32_t SC1_SCL1_WR2; /* SC1_SCL1_WR2 */
|
---|
| 399 | volatile uint32_t SC1_SCL1_WR3; /* SC1_SCL1_WR3 */
|
---|
| 400 | volatile uint32_t SC1_SCL1_WR4; /* SC1_SCL1_WR4 */
|
---|
| 401 | volatile uint8_t dummy29[4]; /* */
|
---|
| 402 | volatile uint32_t SC1_SCL1_WR5; /* SC1_SCL1_WR5 */
|
---|
| 403 | volatile uint32_t SC1_SCL1_WR6; /* SC1_SCL1_WR6 */
|
---|
| 404 | volatile uint32_t SC1_SCL1_WR7; /* SC1_SCL1_WR7 */
|
---|
| 405 | volatile uint32_t SC1_SCL1_WR8; /* SC1_SCL1_WR8 */
|
---|
| 406 | volatile uint32_t SC1_SCL1_WR9; /* SC1_SCL1_WR9 */
|
---|
| 407 | volatile uint32_t SC1_SCL1_WR10; /* SC1_SCL1_WR10 */
|
---|
| 408 | /* end of struct st_vdc5_from_sc0_scl0_update */
|
---|
| 409 | volatile uint32_t SC1_SCL1_WR11; /* SC1_SCL1_WR11 */
|
---|
| 410 | volatile uint32_t SC1_SCL1_MON1; /* SC1_SCL1_MON1 */
|
---|
| 411 | /* start of struct st_vdc5_from_sc0_scl1_pbuf0 */
|
---|
| 412 | #define VDC5_SC1_SCL1_PBUF0_COUNT 4
|
---|
| 413 | volatile uint32_t SC1_SCL1_PBUF0; /* SC1_SCL1_PBUF0 */
|
---|
| 414 | volatile uint32_t SC1_SCL1_PBUF1; /* SC1_SCL1_PBUF1 */
|
---|
| 415 | volatile uint32_t SC1_SCL1_PBUF2; /* SC1_SCL1_PBUF2 */
|
---|
| 416 | volatile uint32_t SC1_SCL1_PBUF3; /* SC1_SCL1_PBUF3 */
|
---|
| 417 | volatile uint32_t SC1_SCL1_PBUF_FLD; /* SC1_SCL1_PBUF_FLD */
|
---|
| 418 | volatile uint32_t SC1_SCL1_PBUF_CNT; /* SC1_SCL1_PBUF_CNT */
|
---|
| 419 | /* end of struct st_vdc5_from_sc0_scl1_pbuf0 */
|
---|
| 420 | volatile uint8_t dummy30[44]; /* */
|
---|
| 421 | /* start of struct st_vdc5_from_gr0_update */
|
---|
| 422 | volatile uint32_t GR1_UPDATE; /* GR1_UPDATE */
|
---|
| 423 | volatile uint32_t GR1_FLM_RD; /* GR1_FLM_RD */
|
---|
| 424 | #define VDC5_GR1_FLM1_COUNT 6
|
---|
| 425 | volatile uint32_t GR1_FLM1; /* GR1_FLM1 */
|
---|
| 426 | volatile uint32_t GR1_FLM2; /* GR1_FLM2 */
|
---|
| 427 | volatile uint32_t GR1_FLM3; /* GR1_FLM3 */
|
---|
| 428 | volatile uint32_t GR1_FLM4; /* GR1_FLM4 */
|
---|
| 429 | volatile uint32_t GR1_FLM5; /* GR1_FLM5 */
|
---|
| 430 | volatile uint32_t GR1_FLM6; /* GR1_FLM6 */
|
---|
| 431 | #define VDC5_GR1_AB1_COUNT 3
|
---|
| 432 | volatile uint32_t GR1_AB1; /* GR1_AB1 */
|
---|
| 433 | volatile uint32_t GR1_AB2; /* GR1_AB2 */
|
---|
| 434 | volatile uint32_t GR1_AB3; /* GR1_AB3 */
|
---|
| 435 | /* end of struct st_vdc5_from_gr0_update */
|
---|
| 436 | volatile uint32_t GR1_AB4; /* GR1_AB4 */
|
---|
| 437 | volatile uint32_t GR1_AB5; /* GR1_AB5 */
|
---|
| 438 | volatile uint32_t GR1_AB6; /* GR1_AB6 */
|
---|
| 439 | /* start of struct st_vdc5_from_gr0_ab7 */
|
---|
| 440 | volatile uint32_t GR1_AB7; /* GR1_AB7 */
|
---|
| 441 | volatile uint32_t GR1_AB8; /* GR1_AB8 */
|
---|
| 442 | volatile uint32_t GR1_AB9; /* GR1_AB9 */
|
---|
| 443 | volatile uint32_t GR1_AB10; /* GR1_AB10 */
|
---|
| 444 | volatile uint32_t GR1_AB11; /* GR1_AB11 */
|
---|
| 445 | volatile uint32_t GR1_BASE; /* GR1_BASE */
|
---|
| 446 | /* end of struct st_vdc5_from_gr0_ab7 */
|
---|
| 447 | volatile uint32_t GR1_CLUT; /* GR1_CLUT */
|
---|
| 448 | volatile uint32_t GR1_MON; /* GR1_MON */
|
---|
| 449 | volatile uint8_t dummy31[40]; /* */
|
---|
| 450 | /* start of struct st_vdc5_from_adj0_update */
|
---|
| 451 | volatile uint32_t ADJ1_UPDATE; /* ADJ1_UPDATE */
|
---|
| 452 | volatile uint32_t ADJ1_BKSTR_SET; /* ADJ1_BKSTR_SET */
|
---|
| 453 | #define VDC5_ADJ1_ENH_TIM1_COUNT 3
|
---|
| 454 | volatile uint32_t ADJ1_ENH_TIM1; /* ADJ1_ENH_TIM1 */
|
---|
| 455 | volatile uint32_t ADJ1_ENH_TIM2; /* ADJ1_ENH_TIM2 */
|
---|
| 456 | volatile uint32_t ADJ1_ENH_TIM3; /* ADJ1_ENH_TIM3 */
|
---|
| 457 | #define VDC5_ADJ1_ENH_SHP1_COUNT 6
|
---|
| 458 | volatile uint32_t ADJ1_ENH_SHP1; /* ADJ1_ENH_SHP1 */
|
---|
| 459 | volatile uint32_t ADJ1_ENH_SHP2; /* ADJ1_ENH_SHP2 */
|
---|
| 460 | volatile uint32_t ADJ1_ENH_SHP3; /* ADJ1_ENH_SHP3 */
|
---|
| 461 | volatile uint32_t ADJ1_ENH_SHP4; /* ADJ1_ENH_SHP4 */
|
---|
| 462 | volatile uint32_t ADJ1_ENH_SHP5; /* ADJ1_ENH_SHP5 */
|
---|
| 463 | volatile uint32_t ADJ1_ENH_SHP6; /* ADJ1_ENH_SHP6 */
|
---|
| 464 | #define VDC5_ADJ1_ENH_LTI1_COUNT 2
|
---|
| 465 | volatile uint32_t ADJ1_ENH_LTI1; /* ADJ1_ENH_LTI1 */
|
---|
| 466 | volatile uint32_t ADJ1_ENH_LTI2; /* ADJ1_ENH_LTI2 */
|
---|
| 467 | volatile uint32_t ADJ1_MTX_MODE; /* ADJ1_MTX_MODE */
|
---|
| 468 | volatile uint32_t ADJ1_MTX_YG_ADJ0; /* ADJ1_MTX_YG_ADJ0 */
|
---|
| 469 | volatile uint32_t ADJ1_MTX_YG_ADJ1; /* ADJ1_MTX_YG_ADJ1 */
|
---|
| 470 | volatile uint32_t ADJ1_MTX_CBB_ADJ0; /* ADJ1_MTX_CBB_ADJ0 */
|
---|
| 471 | volatile uint32_t ADJ1_MTX_CBB_ADJ1; /* ADJ1_MTX_CBB_ADJ1 */
|
---|
| 472 | volatile uint32_t ADJ1_MTX_CRR_ADJ0; /* ADJ1_MTX_CRR_ADJ0 */
|
---|
| 473 | volatile uint32_t ADJ1_MTX_CRR_ADJ1; /* ADJ1_MTX_CRR_ADJ1 */
|
---|
| 474 | /* end of struct st_vdc5_from_adj0_update */
|
---|
| 475 | volatile uint8_t dummy32[48]; /* */
|
---|
| 476 | volatile uint32_t GR_VIN_UPDATE; /* GR_VIN_UPDATE */
|
---|
| 477 | volatile uint8_t dummy33[28]; /* */
|
---|
| 478 | #define VDC5_GR_VIN_AB1_COUNT 7
|
---|
| 479 | volatile uint32_t GR_VIN_AB1; /* GR_VIN_AB1 */
|
---|
| 480 | volatile uint32_t GR_VIN_AB2; /* GR_VIN_AB2 */
|
---|
| 481 | volatile uint32_t GR_VIN_AB3; /* GR_VIN_AB3 */
|
---|
| 482 | volatile uint32_t GR_VIN_AB4; /* GR_VIN_AB4 */
|
---|
| 483 | volatile uint32_t GR_VIN_AB5; /* GR_VIN_AB5 */
|
---|
| 484 | volatile uint32_t GR_VIN_AB6; /* GR_VIN_AB6 */
|
---|
| 485 | volatile uint32_t GR_VIN_AB7; /* GR_VIN_AB7 */
|
---|
| 486 | volatile uint8_t dummy34[16]; /* */
|
---|
| 487 | volatile uint32_t GR_VIN_BASE; /* GR_VIN_BASE */
|
---|
| 488 | volatile uint8_t dummy35[4]; /* */
|
---|
| 489 | volatile uint32_t GR_VIN_MON; /* GR_VIN_MON */
|
---|
| 490 | volatile uint8_t dummy36[40]; /* */
|
---|
| 491 | volatile uint32_t OIR_SCL0_UPDATE; /* OIR_SCL0_UPDATE */
|
---|
| 492 | #define VDC5_OIR_SCL0_FRC1_COUNT 7
|
---|
| 493 | volatile uint32_t OIR_SCL0_FRC1; /* OIR_SCL0_FRC1 */
|
---|
| 494 | volatile uint32_t OIR_SCL0_FRC2; /* OIR_SCL0_FRC2 */
|
---|
| 495 | volatile uint32_t OIR_SCL0_FRC3; /* OIR_SCL0_FRC3 */
|
---|
| 496 | volatile uint32_t OIR_SCL0_FRC4; /* OIR_SCL0_FRC4 */
|
---|
| 497 | volatile uint32_t OIR_SCL0_FRC5; /* OIR_SCL0_FRC5 */
|
---|
| 498 | volatile uint32_t OIR_SCL0_FRC6; /* OIR_SCL0_FRC6 */
|
---|
| 499 | volatile uint32_t OIR_SCL0_FRC7; /* OIR_SCL0_FRC7 */
|
---|
| 500 | volatile uint8_t dummy37[12]; /* */
|
---|
| 501 | #define VDC5_OIR_SCL0_DS1_COUNT 3
|
---|
| 502 | volatile uint32_t OIR_SCL0_DS1; /* OIR_SCL0_DS1 */
|
---|
| 503 | volatile uint32_t OIR_SCL0_DS2; /* OIR_SCL0_DS2 */
|
---|
| 504 | volatile uint32_t OIR_SCL0_DS3; /* OIR_SCL0_DS3 */
|
---|
| 505 | volatile uint8_t dummy38[12]; /* */
|
---|
| 506 | volatile uint32_t OIR_SCL0_DS7; /* OIR_SCL0_DS7 */
|
---|
| 507 | volatile uint32_t OIR_SCL0_US1; /* OIR_SCL0_US1 */
|
---|
| 508 | volatile uint32_t OIR_SCL0_US2; /* OIR_SCL0_US2 */
|
---|
| 509 | volatile uint32_t OIR_SCL0_US3; /* OIR_SCL0_US3 */
|
---|
| 510 | volatile uint8_t dummy39[16]; /* */
|
---|
| 511 | volatile uint32_t OIR_SCL0_US8; /* OIR_SCL0_US8 */
|
---|
| 512 | volatile uint8_t dummy40[4]; /* */
|
---|
| 513 | volatile uint32_t OIR_SCL0_OVR1; /* OIR_SCL0_OVR1 */
|
---|
| 514 | volatile uint8_t dummy41[16]; /* */
|
---|
| 515 | volatile uint32_t OIR_SCL1_UPDATE; /* OIR_SCL1_UPDATE */
|
---|
| 516 | volatile uint8_t dummy42[4]; /* */
|
---|
| 517 | #define VDC5_OIR_SCL1_WR1_COUNT 4
|
---|
| 518 | volatile uint32_t OIR_SCL1_WR1; /* OIR_SCL1_WR1 */
|
---|
| 519 | volatile uint32_t OIR_SCL1_WR2; /* OIR_SCL1_WR2 */
|
---|
| 520 | volatile uint32_t OIR_SCL1_WR3; /* OIR_SCL1_WR3 */
|
---|
| 521 | volatile uint32_t OIR_SCL1_WR4; /* OIR_SCL1_WR4 */
|
---|
| 522 | volatile uint8_t dummy43[4]; /* */
|
---|
| 523 | volatile uint32_t OIR_SCL1_WR5; /* OIR_SCL1_WR5 */
|
---|
| 524 | volatile uint32_t OIR_SCL1_WR6; /* OIR_SCL1_WR6 */
|
---|
| 525 | volatile uint32_t OIR_SCL1_WR7; /* OIR_SCL1_WR7 */
|
---|
| 526 | volatile uint8_t dummy44[88]; /* */
|
---|
| 527 | volatile uint32_t GR_OIR_UPDATE; /* GR_OIR_UPDATE */
|
---|
| 528 | volatile uint32_t GR_OIR_FLM_RD; /* GR_OIR_FLM_RD */
|
---|
| 529 | #define VDC5_GR_OIR_FLM1_COUNT 6
|
---|
| 530 | volatile uint32_t GR_OIR_FLM1; /* GR_OIR_FLM1 */
|
---|
| 531 | volatile uint32_t GR_OIR_FLM2; /* GR_OIR_FLM2 */
|
---|
| 532 | volatile uint32_t GR_OIR_FLM3; /* GR_OIR_FLM3 */
|
---|
| 533 | volatile uint32_t GR_OIR_FLM4; /* GR_OIR_FLM4 */
|
---|
| 534 | volatile uint32_t GR_OIR_FLM5; /* GR_OIR_FLM5 */
|
---|
| 535 | volatile uint32_t GR_OIR_FLM6; /* GR_OIR_FLM6 */
|
---|
| 536 | #define VDC5_GR_OIR_AB1_COUNT 3
|
---|
| 537 | volatile uint32_t GR_OIR_AB1; /* GR_OIR_AB1 */
|
---|
| 538 | volatile uint32_t GR_OIR_AB2; /* GR_OIR_AB2 */
|
---|
| 539 | volatile uint32_t GR_OIR_AB3; /* GR_OIR_AB3 */
|
---|
| 540 | volatile uint8_t dummy45[12]; /* */
|
---|
| 541 | volatile uint32_t GR_OIR_AB7; /* GR_OIR_AB7 */
|
---|
| 542 | volatile uint32_t GR_OIR_AB8; /* GR_OIR_AB8 */
|
---|
| 543 | volatile uint32_t GR_OIR_AB9; /* GR_OIR_AB9 */
|
---|
| 544 | volatile uint32_t GR_OIR_AB10; /* GR_OIR_AB10 */
|
---|
| 545 | volatile uint32_t GR_OIR_AB11; /* GR_OIR_AB11 */
|
---|
| 546 | volatile uint32_t GR_OIR_BASE; /* GR_OIR_BASE */
|
---|
| 547 | volatile uint32_t GR_OIR_CLUT; /* GR_OIR_CLUT */
|
---|
| 548 | volatile uint32_t GR_OIR_MON; /* GR_OIR_MON */
|
---|
| 549 | };
|
---|
| 550 |
|
---|
| 551 |
|
---|
| 552 | struct st_vdc5_from_gr0_update
|
---|
| 553 | {
|
---|
| 554 | volatile uint32_t GR0_UPDATE; /* GR0_UPDATE */
|
---|
| 555 | volatile uint32_t GR0_FLM_RD; /* GR0_FLM_RD */
|
---|
| 556 | volatile uint32_t GR0_FLM1; /* GR0_FLM1 */
|
---|
| 557 | volatile uint32_t GR0_FLM2; /* GR0_FLM2 */
|
---|
| 558 | volatile uint32_t GR0_FLM3; /* GR0_FLM3 */
|
---|
| 559 | volatile uint32_t GR0_FLM4; /* GR0_FLM4 */
|
---|
| 560 | volatile uint32_t GR0_FLM5; /* GR0_FLM5 */
|
---|
| 561 | volatile uint32_t GR0_FLM6; /* GR0_FLM6 */
|
---|
| 562 | volatile uint32_t GR0_AB1; /* GR0_AB1 */
|
---|
| 563 | volatile uint32_t GR0_AB2; /* GR0_AB2 */
|
---|
| 564 | volatile uint32_t GR0_AB3; /* GR0_AB3 */
|
---|
| 565 | };
|
---|
| 566 |
|
---|
| 567 |
|
---|
| 568 | struct st_vdc5_from_gr0_ab7
|
---|
| 569 | {
|
---|
| 570 | volatile uint32_t GR0_AB7; /* GR0_AB7 */
|
---|
| 571 | volatile uint32_t GR0_AB8; /* GR0_AB8 */
|
---|
| 572 | volatile uint32_t GR0_AB9; /* GR0_AB9 */
|
---|
| 573 | volatile uint32_t GR0_AB10; /* GR0_AB10 */
|
---|
| 574 | volatile uint32_t GR0_AB11; /* GR0_AB11 */
|
---|
| 575 | volatile uint32_t GR0_BASE; /* GR0_BASE */
|
---|
| 576 | };
|
---|
| 577 |
|
---|
| 578 |
|
---|
| 579 | struct st_vdc5_from_adj0_update
|
---|
| 580 | {
|
---|
| 581 | volatile uint32_t ADJ0_UPDATE; /* ADJ0_UPDATE */
|
---|
| 582 | volatile uint32_t ADJ0_BKSTR_SET; /* ADJ0_BKSTR_SET */
|
---|
| 583 | volatile uint32_t ADJ0_ENH_TIM1; /* ADJ0_ENH_TIM1 */
|
---|
| 584 | volatile uint32_t ADJ0_ENH_TIM2; /* ADJ0_ENH_TIM2 */
|
---|
| 585 | volatile uint32_t ADJ0_ENH_TIM3; /* ADJ0_ENH_TIM3 */
|
---|
| 586 | volatile uint32_t ADJ0_ENH_SHP1; /* ADJ0_ENH_SHP1 */
|
---|
| 587 | volatile uint32_t ADJ0_ENH_SHP2; /* ADJ0_ENH_SHP2 */
|
---|
| 588 | volatile uint32_t ADJ0_ENH_SHP3; /* ADJ0_ENH_SHP3 */
|
---|
| 589 | volatile uint32_t ADJ0_ENH_SHP4; /* ADJ0_ENH_SHP4 */
|
---|
| 590 | volatile uint32_t ADJ0_ENH_SHP5; /* ADJ0_ENH_SHP5 */
|
---|
| 591 | volatile uint32_t ADJ0_ENH_SHP6; /* ADJ0_ENH_SHP6 */
|
---|
| 592 | volatile uint32_t ADJ0_ENH_LTI1; /* ADJ0_ENH_LTI1 */
|
---|
| 593 | volatile uint32_t ADJ0_ENH_LTI2; /* ADJ0_ENH_LTI2 */
|
---|
| 594 | volatile uint32_t ADJ0_MTX_MODE; /* ADJ0_MTX_MODE */
|
---|
| 595 | volatile uint32_t ADJ0_MTX_YG_ADJ0; /* ADJ0_MTX_YG_ADJ0 */
|
---|
| 596 | volatile uint32_t ADJ0_MTX_YG_ADJ1; /* ADJ0_MTX_YG_ADJ1 */
|
---|
| 597 | volatile uint32_t ADJ0_MTX_CBB_ADJ0; /* ADJ0_MTX_CBB_ADJ0 */
|
---|
| 598 | volatile uint32_t ADJ0_MTX_CBB_ADJ1; /* ADJ0_MTX_CBB_ADJ1 */
|
---|
| 599 | volatile uint32_t ADJ0_MTX_CRR_ADJ0; /* ADJ0_MTX_CRR_ADJ0 */
|
---|
| 600 | volatile uint32_t ADJ0_MTX_CRR_ADJ1; /* ADJ0_MTX_CRR_ADJ1 */
|
---|
| 601 | };
|
---|
| 602 |
|
---|
| 603 |
|
---|
| 604 | struct st_vdc5_from_sc0_scl0_update
|
---|
| 605 | {
|
---|
| 606 | volatile uint32_t SC0_SCL0_UPDATE; /* SC0_SCL0_UPDATE */
|
---|
| 607 | volatile uint32_t SC0_SCL0_FRC1; /* SC0_SCL0_FRC1 */
|
---|
| 608 | volatile uint32_t SC0_SCL0_FRC2; /* SC0_SCL0_FRC2 */
|
---|
| 609 | volatile uint32_t SC0_SCL0_FRC3; /* SC0_SCL0_FRC3 */
|
---|
| 610 | volatile uint32_t SC0_SCL0_FRC4; /* SC0_SCL0_FRC4 */
|
---|
| 611 | volatile uint32_t SC0_SCL0_FRC5; /* SC0_SCL0_FRC5 */
|
---|
| 612 | volatile uint32_t SC0_SCL0_FRC6; /* SC0_SCL0_FRC6 */
|
---|
| 613 | volatile uint32_t SC0_SCL0_FRC7; /* SC0_SCL0_FRC7 */
|
---|
| 614 | volatile uint8_t dummy5[4]; /* */
|
---|
| 615 | volatile uint32_t SC0_SCL0_FRC9; /* SC0_SCL0_FRC9 */
|
---|
| 616 | volatile uint16_t SC0_SCL0_MON0; /* SC0_SCL0_MON0 */
|
---|
| 617 | volatile uint16_t SC0_SCL0_INT; /* SC0_SCL0_INT */
|
---|
| 618 | volatile uint32_t SC0_SCL0_DS1; /* SC0_SCL0_DS1 */
|
---|
| 619 | volatile uint32_t SC0_SCL0_DS2; /* SC0_SCL0_DS2 */
|
---|
| 620 | volatile uint32_t SC0_SCL0_DS3; /* SC0_SCL0_DS3 */
|
---|
| 621 | volatile uint32_t SC0_SCL0_DS4; /* SC0_SCL0_DS4 */
|
---|
| 622 | volatile uint32_t SC0_SCL0_DS5; /* SC0_SCL0_DS5 */
|
---|
| 623 | volatile uint32_t SC0_SCL0_DS6; /* SC0_SCL0_DS6 */
|
---|
| 624 | volatile uint32_t SC0_SCL0_DS7; /* SC0_SCL0_DS7 */
|
---|
| 625 | volatile uint32_t SC0_SCL0_US1; /* SC0_SCL0_US1 */
|
---|
| 626 | volatile uint32_t SC0_SCL0_US2; /* SC0_SCL0_US2 */
|
---|
| 627 | volatile uint32_t SC0_SCL0_US3; /* SC0_SCL0_US3 */
|
---|
| 628 | volatile uint32_t SC0_SCL0_US4; /* SC0_SCL0_US4 */
|
---|
| 629 | volatile uint32_t SC0_SCL0_US5; /* SC0_SCL0_US5 */
|
---|
| 630 | volatile uint32_t SC0_SCL0_US6; /* SC0_SCL0_US6 */
|
---|
| 631 | volatile uint32_t SC0_SCL0_US7; /* SC0_SCL0_US7 */
|
---|
| 632 | volatile uint32_t SC0_SCL0_US8; /* SC0_SCL0_US8 */
|
---|
| 633 | volatile uint8_t dummy6[4]; /* */
|
---|
| 634 | volatile uint32_t SC0_SCL0_OVR1; /* SC0_SCL0_OVR1 */
|
---|
| 635 | volatile uint8_t dummy7[16]; /* */
|
---|
| 636 | volatile uint32_t SC0_SCL1_UPDATE; /* SC0_SCL1_UPDATE */
|
---|
| 637 | volatile uint8_t dummy8[4]; /* */
|
---|
| 638 | volatile uint32_t SC0_SCL1_WR1; /* SC0_SCL1_WR1 */
|
---|
| 639 | volatile uint32_t SC0_SCL1_WR2; /* SC0_SCL1_WR2 */
|
---|
| 640 | volatile uint32_t SC0_SCL1_WR3; /* SC0_SCL1_WR3 */
|
---|
| 641 | volatile uint32_t SC0_SCL1_WR4; /* SC0_SCL1_WR4 */
|
---|
| 642 | volatile uint8_t dummy9[4]; /* */
|
---|
| 643 | volatile uint32_t SC0_SCL1_WR5; /* SC0_SCL1_WR5 */
|
---|
| 644 | volatile uint32_t SC0_SCL1_WR6; /* SC0_SCL1_WR6 */
|
---|
| 645 | volatile uint32_t SC0_SCL1_WR7; /* SC0_SCL1_WR7 */
|
---|
| 646 | volatile uint32_t SC0_SCL1_WR8; /* SC0_SCL1_WR8 */
|
---|
| 647 | volatile uint32_t SC0_SCL1_WR9; /* SC0_SCL1_WR9 */
|
---|
| 648 | volatile uint32_t SC0_SCL1_WR10; /* SC0_SCL1_WR10 */
|
---|
| 649 | };
|
---|
| 650 |
|
---|
| 651 |
|
---|
| 652 | struct st_vdc5_from_sc0_scl1_pbuf0
|
---|
| 653 | {
|
---|
| 654 | volatile uint32_t SC0_SCL1_PBUF0; /* SC0_SCL1_PBUF0 */
|
---|
| 655 | volatile uint32_t SC0_SCL1_PBUF1; /* SC0_SCL1_PBUF1 */
|
---|
| 656 | volatile uint32_t SC0_SCL1_PBUF2; /* SC0_SCL1_PBUF2 */
|
---|
| 657 | volatile uint32_t SC0_SCL1_PBUF3; /* SC0_SCL1_PBUF3 */
|
---|
| 658 | volatile uint32_t SC0_SCL1_PBUF_FLD; /* SC0_SCL1_PBUF_FLD */
|
---|
| 659 | volatile uint32_t SC0_SCL1_PBUF_CNT; /* SC0_SCL1_PBUF_CNT */
|
---|
| 660 | };
|
---|
| 661 |
|
---|
| 662 |
|
---|
| 663 | #define VDC50 (*(struct st_vdc5 *)0xFCFF7400uL) /* VDC50 */
|
---|
| 664 | #define VDC51 (*(struct st_vdc5 *)0xFCFF9400uL) /* VDC51 */
|
---|
| 665 |
|
---|
| 666 |
|
---|
| 667 | /* Start of channnel array defines of VDC5 */
|
---|
| 668 |
|
---|
| 669 | /* Channnel array defines of VDC5 */
|
---|
| 670 | /*(Sample) value = VDC5[ channel ]->INP_UPDATE; */
|
---|
| 671 | #define VDC5_COUNT 2
|
---|
| 672 | #define VDC5_ADDRESS_LIST \
|
---|
| 673 | { /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \
|
---|
| 674 | &VDC50, &VDC51 \
|
---|
| 675 | } /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */
|
---|
| 676 |
|
---|
| 677 |
|
---|
| 678 |
|
---|
| 679 | /* Channnel array defines of VDC5n_FROM_GR2_AB7_ARRAY */
|
---|
| 680 | /*(Sample) value = VDC5n_FROM_GR2_AB7_ARRAY[ channel ][ index ]->GR0_AB7; */
|
---|
| 681 | #define VDC5n_FROM_GR2_AB7_ARRAY_COUNT 2
|
---|
| 682 | #define VDC5n_FROM_GR2_AB7_ARRAY_ADDRESS_LIST \
|
---|
| 683 | { /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \
|
---|
| 684 | { \
|
---|
| 685 | &VDC50_FROM_GR2_AB7, &VDC50_FROM_GR3_AB7 },{ \
|
---|
| 686 | &VDC51_FROM_GR2_AB7, &VDC51_FROM_GR3_AB7 \
|
---|
| 687 | } \
|
---|
| 688 | } /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */
|
---|
| 689 | #define VDC50_FROM_GR2_AB7 (*(struct st_vdc5_from_gr0_ab7 *)&VDC50.GR2_AB7) /* VDC50_FROM_GR2_AB7 */
|
---|
| 690 | #define VDC50_FROM_GR3_AB7 (*(struct st_vdc5_from_gr0_ab7 *)&VDC50.GR3_AB7) /* VDC50_FROM_GR3_AB7 */
|
---|
| 691 | #define VDC51_FROM_GR2_AB7 (*(struct st_vdc5_from_gr0_ab7 *)&VDC51.GR2_AB7) /* VDC51_FROM_GR2_AB7 */
|
---|
| 692 | #define VDC51_FROM_GR3_AB7 (*(struct st_vdc5_from_gr0_ab7 *)&VDC51.GR3_AB7) /* VDC51_FROM_GR3_AB7 */
|
---|
| 693 |
|
---|
| 694 |
|
---|
| 695 |
|
---|
| 696 |
|
---|
| 697 | /* Channnel array defines of VDC5n_FROM_GR2_UPDATE_ARRAY */
|
---|
| 698 | /*(Sample) value = VDC5n_FROM_GR2_UPDATE_ARRAY[ channel ][ index ]->GR0_UPDATE; */
|
---|
| 699 | #define VDC5n_FROM_GR2_UPDATE_ARRAY_COUNT 2
|
---|
| 700 | #define VDC5n_FROM_GR2_UPDATE_ARRAY_ADDRESS_LIST \
|
---|
| 701 | { /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \
|
---|
| 702 | { \
|
---|
| 703 | &VDC50_FROM_GR2_UPDATE, &VDC50_FROM_GR3_UPDATE },{ \
|
---|
| 704 | &VDC51_FROM_GR2_UPDATE, &VDC51_FROM_GR3_UPDATE \
|
---|
| 705 | } \
|
---|
| 706 | } /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */
|
---|
| 707 | #define VDC50_FROM_GR2_UPDATE (*(struct st_vdc5_from_gr0_update *)&VDC50.GR2_UPDATE) /* VDC50_FROM_GR2_UPDATE */
|
---|
| 708 | #define VDC50_FROM_GR3_UPDATE (*(struct st_vdc5_from_gr0_update *)&VDC50.GR3_UPDATE) /* VDC50_FROM_GR3_UPDATE */
|
---|
| 709 | #define VDC51_FROM_GR2_UPDATE (*(struct st_vdc5_from_gr0_update *)&VDC51.GR2_UPDATE) /* VDC51_FROM_GR2_UPDATE */
|
---|
| 710 | #define VDC51_FROM_GR3_UPDATE (*(struct st_vdc5_from_gr0_update *)&VDC51.GR3_UPDATE) /* VDC51_FROM_GR3_UPDATE */
|
---|
| 711 |
|
---|
| 712 |
|
---|
| 713 |
|
---|
| 714 |
|
---|
| 715 | /* Channnel array defines of VDC5n_FROM_SC0_SCL1_PBUF0_ARRAY */
|
---|
| 716 | /*(Sample) value = VDC5n_FROM_SC0_SCL1_PBUF0_ARRAY[ channel ][ index ]->SC0_SCL1_PBUF0; */
|
---|
| 717 | #define VDC5n_FROM_SC0_SCL1_PBUF0_ARRAY_COUNT 2
|
---|
| 718 | #define VDC5n_FROM_SC0_SCL1_PBUF0_ARRAY_ADDRESS_LIST \
|
---|
| 719 | { /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \
|
---|
| 720 | { \
|
---|
| 721 | &VDC50_FROM_SC0_SCL1_PBUF0, &VDC50_FROM_SC1_SCL1_PBUF0 },{ \
|
---|
| 722 | &VDC51_FROM_SC0_SCL1_PBUF0, &VDC51_FROM_SC1_SCL1_PBUF0 \
|
---|
| 723 | } \
|
---|
| 724 | } /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */
|
---|
| 725 | #define VDC50_FROM_SC0_SCL1_PBUF0 (*(struct st_vdc5_from_sc0_scl1_pbuf0 *)&VDC50.SC0_SCL1_PBUF0) /* VDC50_FROM_SC0_SCL1_PBUF0 */
|
---|
| 726 | #define VDC50_FROM_SC1_SCL1_PBUF0 (*(struct st_vdc5_from_sc0_scl1_pbuf0 *)&VDC50.SC1_SCL1_PBUF0) /* VDC50_FROM_SC1_SCL1_PBUF0 */
|
---|
| 727 | #define VDC51_FROM_SC0_SCL1_PBUF0 (*(struct st_vdc5_from_sc0_scl1_pbuf0 *)&VDC51.SC0_SCL1_PBUF0) /* VDC51_FROM_SC0_SCL1_PBUF0 */
|
---|
| 728 | #define VDC51_FROM_SC1_SCL1_PBUF0 (*(struct st_vdc5_from_sc0_scl1_pbuf0 *)&VDC51.SC1_SCL1_PBUF0) /* VDC51_FROM_SC1_SCL1_PBUF0 */
|
---|
| 729 |
|
---|
| 730 |
|
---|
| 731 |
|
---|
| 732 |
|
---|
| 733 | /* Channnel array defines of VDC5n_FROM_SC0_SCL0_UPDATE_ARRAY */
|
---|
| 734 | /*(Sample) value = VDC5n_FROM_SC0_SCL0_UPDATE_ARRAY[ channel ][ index ]->SC0_SCL0_UPDATE; */
|
---|
| 735 | #define VDC5n_FROM_SC0_SCL0_UPDATE_ARRAY_COUNT 2
|
---|
| 736 | #define VDC5n_FROM_SC0_SCL0_UPDATE_ARRAY_ADDRESS_LIST \
|
---|
| 737 | { /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \
|
---|
| 738 | { \
|
---|
| 739 | &VDC50_FROM_SC0_SCL0_UPDATE, &VDC50_FROM_SC1_SCL0_UPDATE },{ \
|
---|
| 740 | &VDC51_FROM_SC0_SCL0_UPDATE, &VDC51_FROM_SC1_SCL0_UPDATE \
|
---|
| 741 | } \
|
---|
| 742 | } /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */
|
---|
| 743 | #define VDC50_FROM_SC0_SCL0_UPDATE (*(struct st_vdc5_from_sc0_scl0_update *)&VDC50.SC0_SCL0_UPDATE) /* VDC50_FROM_SC0_SCL0_UPDATE */
|
---|
| 744 | #define VDC50_FROM_SC1_SCL0_UPDATE (*(struct st_vdc5_from_sc0_scl0_update *)&VDC50.SC1_SCL0_UPDATE) /* VDC50_FROM_SC1_SCL0_UPDATE */
|
---|
| 745 | #define VDC51_FROM_SC0_SCL0_UPDATE (*(struct st_vdc5_from_sc0_scl0_update *)&VDC51.SC0_SCL0_UPDATE) /* VDC51_FROM_SC0_SCL0_UPDATE */
|
---|
| 746 | #define VDC51_FROM_SC1_SCL0_UPDATE (*(struct st_vdc5_from_sc0_scl0_update *)&VDC51.SC1_SCL0_UPDATE) /* VDC51_FROM_SC1_SCL0_UPDATE */
|
---|
| 747 |
|
---|
| 748 |
|
---|
| 749 |
|
---|
| 750 |
|
---|
| 751 | /* Channnel array defines of VDC5n_FROM_ADJ0_UPDATE_ARRAY */
|
---|
| 752 | /*(Sample) value = VDC5n_FROM_ADJ0_UPDATE_ARRAY[ channel ][ index ]->ADJ0_UPDATE; */
|
---|
| 753 | #define VDC5n_FROM_ADJ0_UPDATE_ARRAY_COUNT 2
|
---|
| 754 | #define VDC5n_FROM_ADJ0_UPDATE_ARRAY_ADDRESS_LIST \
|
---|
| 755 | { /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \
|
---|
| 756 | { \
|
---|
| 757 | &VDC50_FROM_ADJ0_UPDATE, &VDC50_FROM_ADJ1_UPDATE },{ \
|
---|
| 758 | &VDC51_FROM_ADJ0_UPDATE, &VDC51_FROM_ADJ1_UPDATE \
|
---|
| 759 | } \
|
---|
| 760 | } /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */
|
---|
| 761 | #define VDC50_FROM_ADJ0_UPDATE (*(struct st_vdc5_from_adj0_update *)&VDC50.ADJ0_UPDATE) /* VDC50_FROM_ADJ0_UPDATE */
|
---|
| 762 | #define VDC50_FROM_ADJ1_UPDATE (*(struct st_vdc5_from_adj0_update *)&VDC50.ADJ1_UPDATE) /* VDC50_FROM_ADJ1_UPDATE */
|
---|
| 763 | #define VDC51_FROM_ADJ0_UPDATE (*(struct st_vdc5_from_adj0_update *)&VDC51.ADJ0_UPDATE) /* VDC51_FROM_ADJ0_UPDATE */
|
---|
| 764 | #define VDC51_FROM_ADJ1_UPDATE (*(struct st_vdc5_from_adj0_update *)&VDC51.ADJ1_UPDATE) /* VDC51_FROM_ADJ1_UPDATE */
|
---|
| 765 |
|
---|
| 766 |
|
---|
| 767 |
|
---|
| 768 |
|
---|
| 769 | /* Channnel array defines of VDC5n_FROM_GR0_AB7_ARRAY */
|
---|
| 770 | /*(Sample) value = VDC5n_FROM_GR0_AB7_ARRAY[ channel ][ index ]->GR0_AB7; */
|
---|
| 771 | #define VDC5n_FROM_GR0_AB7_ARRAY_COUNT 2
|
---|
| 772 | #define VDC5n_FROM_GR0_AB7_ARRAY_ADDRESS_LIST \
|
---|
| 773 | { /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \
|
---|
| 774 | { \
|
---|
| 775 | &VDC50_FROM_GR0_AB7, &VDC50_FROM_GR1_AB7 },{ \
|
---|
| 776 | &VDC51_FROM_GR0_AB7, &VDC51_FROM_GR1_AB7 \
|
---|
| 777 | } \
|
---|
| 778 | } /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */
|
---|
| 779 | #define VDC50_FROM_GR0_AB7 (*(struct st_vdc5_from_gr0_ab7 *)&VDC50.GR0_AB7) /* VDC50_FROM_GR0_AB7 */
|
---|
| 780 | #define VDC50_FROM_GR1_AB7 (*(struct st_vdc5_from_gr0_ab7 *)&VDC50.GR1_AB7) /* VDC50_FROM_GR1_AB7 */
|
---|
| 781 | #define VDC51_FROM_GR0_AB7 (*(struct st_vdc5_from_gr0_ab7 *)&VDC51.GR0_AB7) /* VDC51_FROM_GR0_AB7 */
|
---|
| 782 | #define VDC51_FROM_GR1_AB7 (*(struct st_vdc5_from_gr0_ab7 *)&VDC51.GR1_AB7) /* VDC51_FROM_GR1_AB7 */
|
---|
| 783 |
|
---|
| 784 |
|
---|
| 785 |
|
---|
| 786 |
|
---|
| 787 | /* Channnel array defines of VDC5n_FROM_GR0_UPDATE_ARRAY */
|
---|
| 788 | /*(Sample) value = VDC5n_FROM_GR0_UPDATE_ARRAY[ channel ][ index ]->GR0_UPDATE; */
|
---|
| 789 | #define VDC5n_FROM_GR0_UPDATE_ARRAY_COUNT 2
|
---|
| 790 | #define VDC5n_FROM_GR0_UPDATE_ARRAY_ADDRESS_LIST \
|
---|
| 791 | { /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \
|
---|
| 792 | { \
|
---|
| 793 | &VDC50_FROM_GR0_UPDATE, &VDC50_FROM_GR1_UPDATE },{ \
|
---|
| 794 | &VDC51_FROM_GR0_UPDATE, &VDC51_FROM_GR1_UPDATE \
|
---|
| 795 | } \
|
---|
| 796 | } /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */
|
---|
| 797 | #define VDC50_FROM_GR0_UPDATE (*(struct st_vdc5_from_gr0_update *)&VDC50.GR0_UPDATE) /* VDC50_FROM_GR0_UPDATE */
|
---|
| 798 | #define VDC50_FROM_GR1_UPDATE (*(struct st_vdc5_from_gr0_update *)&VDC50.GR1_UPDATE) /* VDC50_FROM_GR1_UPDATE */
|
---|
| 799 | #define VDC51_FROM_GR0_UPDATE (*(struct st_vdc5_from_gr0_update *)&VDC51.GR0_UPDATE) /* VDC51_FROM_GR0_UPDATE */
|
---|
| 800 | #define VDC51_FROM_GR1_UPDATE (*(struct st_vdc5_from_gr0_update *)&VDC51.GR1_UPDATE) /* VDC51_FROM_GR1_UPDATE */
|
---|
| 801 |
|
---|
| 802 |
|
---|
| 803 | /* End of channnel array defines of VDC5 */
|
---|
| 804 |
|
---|
| 805 |
|
---|
| 806 | #define VDC50INP_UPDATE VDC50.INP_UPDATE
|
---|
| 807 | #define VDC50INP_SEL_CNT VDC50.INP_SEL_CNT
|
---|
| 808 | #define VDC50INP_EXT_SYNC_CNT VDC50.INP_EXT_SYNC_CNT
|
---|
| 809 | #define VDC50INP_VSYNC_PH_ADJ VDC50.INP_VSYNC_PH_ADJ
|
---|
| 810 | #define VDC50INP_DLY_ADJ VDC50.INP_DLY_ADJ
|
---|
| 811 | #define VDC50IMGCNT_UPDATE VDC50.IMGCNT_UPDATE
|
---|
| 812 | #define VDC50IMGCNT_NR_CNT0 VDC50.IMGCNT_NR_CNT0
|
---|
| 813 | #define VDC50IMGCNT_NR_CNT1 VDC50.IMGCNT_NR_CNT1
|
---|
| 814 | #define VDC50IMGCNT_MTX_MODE VDC50.IMGCNT_MTX_MODE
|
---|
| 815 | #define VDC50IMGCNT_MTX_YG_ADJ0 VDC50.IMGCNT_MTX_YG_ADJ0
|
---|
| 816 | #define VDC50IMGCNT_MTX_YG_ADJ1 VDC50.IMGCNT_MTX_YG_ADJ1
|
---|
| 817 | #define VDC50IMGCNT_MTX_CBB_ADJ0 VDC50.IMGCNT_MTX_CBB_ADJ0
|
---|
| 818 | #define VDC50IMGCNT_MTX_CBB_ADJ1 VDC50.IMGCNT_MTX_CBB_ADJ1
|
---|
| 819 | #define VDC50IMGCNT_MTX_CRR_ADJ0 VDC50.IMGCNT_MTX_CRR_ADJ0
|
---|
| 820 | #define VDC50IMGCNT_MTX_CRR_ADJ1 VDC50.IMGCNT_MTX_CRR_ADJ1
|
---|
| 821 | #define VDC50IMGCNT_DRC_REG VDC50.IMGCNT_DRC_REG
|
---|
| 822 | #define VDC50SC0_SCL0_UPDATE VDC50.SC0_SCL0_UPDATE
|
---|
| 823 | #define VDC50SC0_SCL0_FRC1 VDC50.SC0_SCL0_FRC1
|
---|
| 824 | #define VDC50SC0_SCL0_FRC2 VDC50.SC0_SCL0_FRC2
|
---|
| 825 | #define VDC50SC0_SCL0_FRC3 VDC50.SC0_SCL0_FRC3
|
---|
| 826 | #define VDC50SC0_SCL0_FRC4 VDC50.SC0_SCL0_FRC4
|
---|
| 827 | #define VDC50SC0_SCL0_FRC5 VDC50.SC0_SCL0_FRC5
|
---|
| 828 | #define VDC50SC0_SCL0_FRC6 VDC50.SC0_SCL0_FRC6
|
---|
| 829 | #define VDC50SC0_SCL0_FRC7 VDC50.SC0_SCL0_FRC7
|
---|
| 830 | #define VDC50SC0_SCL0_FRC9 VDC50.SC0_SCL0_FRC9
|
---|
| 831 | #define VDC50SC0_SCL0_MON0 VDC50.SC0_SCL0_MON0
|
---|
| 832 | #define VDC50SC0_SCL0_INT VDC50.SC0_SCL0_INT
|
---|
| 833 | #define VDC50SC0_SCL0_DS1 VDC50.SC0_SCL0_DS1
|
---|
| 834 | #define VDC50SC0_SCL0_DS2 VDC50.SC0_SCL0_DS2
|
---|
| 835 | #define VDC50SC0_SCL0_DS3 VDC50.SC0_SCL0_DS3
|
---|
| 836 | #define VDC50SC0_SCL0_DS4 VDC50.SC0_SCL0_DS4
|
---|
| 837 | #define VDC50SC0_SCL0_DS5 VDC50.SC0_SCL0_DS5
|
---|
| 838 | #define VDC50SC0_SCL0_DS6 VDC50.SC0_SCL0_DS6
|
---|
| 839 | #define VDC50SC0_SCL0_DS7 VDC50.SC0_SCL0_DS7
|
---|
| 840 | #define VDC50SC0_SCL0_US1 VDC50.SC0_SCL0_US1
|
---|
| 841 | #define VDC50SC0_SCL0_US2 VDC50.SC0_SCL0_US2
|
---|
| 842 | #define VDC50SC0_SCL0_US3 VDC50.SC0_SCL0_US3
|
---|
| 843 | #define VDC50SC0_SCL0_US4 VDC50.SC0_SCL0_US4
|
---|
| 844 | #define VDC50SC0_SCL0_US5 VDC50.SC0_SCL0_US5
|
---|
| 845 | #define VDC50SC0_SCL0_US6 VDC50.SC0_SCL0_US6
|
---|
| 846 | #define VDC50SC0_SCL0_US7 VDC50.SC0_SCL0_US7
|
---|
| 847 | #define VDC50SC0_SCL0_US8 VDC50.SC0_SCL0_US8
|
---|
| 848 | #define VDC50SC0_SCL0_OVR1 VDC50.SC0_SCL0_OVR1
|
---|
| 849 | #define VDC50SC0_SCL1_UPDATE VDC50.SC0_SCL1_UPDATE
|
---|
| 850 | #define VDC50SC0_SCL1_WR1 VDC50.SC0_SCL1_WR1
|
---|
| 851 | #define VDC50SC0_SCL1_WR2 VDC50.SC0_SCL1_WR2
|
---|
| 852 | #define VDC50SC0_SCL1_WR3 VDC50.SC0_SCL1_WR3
|
---|
| 853 | #define VDC50SC0_SCL1_WR4 VDC50.SC0_SCL1_WR4
|
---|
| 854 | #define VDC50SC0_SCL1_WR5 VDC50.SC0_SCL1_WR5
|
---|
| 855 | #define VDC50SC0_SCL1_WR6 VDC50.SC0_SCL1_WR6
|
---|
| 856 | #define VDC50SC0_SCL1_WR7 VDC50.SC0_SCL1_WR7
|
---|
| 857 | #define VDC50SC0_SCL1_WR8 VDC50.SC0_SCL1_WR8
|
---|
| 858 | #define VDC50SC0_SCL1_WR9 VDC50.SC0_SCL1_WR9
|
---|
| 859 | #define VDC50SC0_SCL1_WR10 VDC50.SC0_SCL1_WR10
|
---|
| 860 | #define VDC50SC0_SCL1_WR11 VDC50.SC0_SCL1_WR11
|
---|
| 861 | #define VDC50SC0_SCL1_MON1 VDC50.SC0_SCL1_MON1
|
---|
| 862 | #define VDC50SC0_SCL1_PBUF0 VDC50.SC0_SCL1_PBUF0
|
---|
| 863 | #define VDC50SC0_SCL1_PBUF1 VDC50.SC0_SCL1_PBUF1
|
---|
| 864 | #define VDC50SC0_SCL1_PBUF2 VDC50.SC0_SCL1_PBUF2
|
---|
| 865 | #define VDC50SC0_SCL1_PBUF3 VDC50.SC0_SCL1_PBUF3
|
---|
| 866 | #define VDC50SC0_SCL1_PBUF_FLD VDC50.SC0_SCL1_PBUF_FLD
|
---|
| 867 | #define VDC50SC0_SCL1_PBUF_CNT VDC50.SC0_SCL1_PBUF_CNT
|
---|
| 868 | #define VDC50GR0_UPDATE VDC50.GR0_UPDATE
|
---|
| 869 | #define VDC50GR0_FLM_RD VDC50.GR0_FLM_RD
|
---|
| 870 | #define VDC50GR0_FLM1 VDC50.GR0_FLM1
|
---|
| 871 | #define VDC50GR0_FLM2 VDC50.GR0_FLM2
|
---|
| 872 | #define VDC50GR0_FLM3 VDC50.GR0_FLM3
|
---|
| 873 | #define VDC50GR0_FLM4 VDC50.GR0_FLM4
|
---|
| 874 | #define VDC50GR0_FLM5 VDC50.GR0_FLM5
|
---|
| 875 | #define VDC50GR0_FLM6 VDC50.GR0_FLM6
|
---|
| 876 | #define VDC50GR0_AB1 VDC50.GR0_AB1
|
---|
| 877 | #define VDC50GR0_AB2 VDC50.GR0_AB2
|
---|
| 878 | #define VDC50GR0_AB3 VDC50.GR0_AB3
|
---|
| 879 | #define VDC50GR0_AB7 VDC50.GR0_AB7
|
---|
| 880 | #define VDC50GR0_AB8 VDC50.GR0_AB8
|
---|
| 881 | #define VDC50GR0_AB9 VDC50.GR0_AB9
|
---|
| 882 | #define VDC50GR0_AB10 VDC50.GR0_AB10
|
---|
| 883 | #define VDC50GR0_AB11 VDC50.GR0_AB11
|
---|
| 884 | #define VDC50GR0_BASE VDC50.GR0_BASE
|
---|
| 885 | #define VDC50GR0_CLUT VDC50.GR0_CLUT
|
---|
| 886 | #define VDC50ADJ0_UPDATE VDC50.ADJ0_UPDATE
|
---|
| 887 | #define VDC50ADJ0_BKSTR_SET VDC50.ADJ0_BKSTR_SET
|
---|
| 888 | #define VDC50ADJ0_ENH_TIM1 VDC50.ADJ0_ENH_TIM1
|
---|
| 889 | #define VDC50ADJ0_ENH_TIM2 VDC50.ADJ0_ENH_TIM2
|
---|
| 890 | #define VDC50ADJ0_ENH_TIM3 VDC50.ADJ0_ENH_TIM3
|
---|
| 891 | #define VDC50ADJ0_ENH_SHP1 VDC50.ADJ0_ENH_SHP1
|
---|
| 892 | #define VDC50ADJ0_ENH_SHP2 VDC50.ADJ0_ENH_SHP2
|
---|
| 893 | #define VDC50ADJ0_ENH_SHP3 VDC50.ADJ0_ENH_SHP3
|
---|
| 894 | #define VDC50ADJ0_ENH_SHP4 VDC50.ADJ0_ENH_SHP4
|
---|
| 895 | #define VDC50ADJ0_ENH_SHP5 VDC50.ADJ0_ENH_SHP5
|
---|
| 896 | #define VDC50ADJ0_ENH_SHP6 VDC50.ADJ0_ENH_SHP6
|
---|
| 897 | #define VDC50ADJ0_ENH_LTI1 VDC50.ADJ0_ENH_LTI1
|
---|
| 898 | #define VDC50ADJ0_ENH_LTI2 VDC50.ADJ0_ENH_LTI2
|
---|
| 899 | #define VDC50ADJ0_MTX_MODE VDC50.ADJ0_MTX_MODE
|
---|
| 900 | #define VDC50ADJ0_MTX_YG_ADJ0 VDC50.ADJ0_MTX_YG_ADJ0
|
---|
| 901 | #define VDC50ADJ0_MTX_YG_ADJ1 VDC50.ADJ0_MTX_YG_ADJ1
|
---|
| 902 | #define VDC50ADJ0_MTX_CBB_ADJ0 VDC50.ADJ0_MTX_CBB_ADJ0
|
---|
| 903 | #define VDC50ADJ0_MTX_CBB_ADJ1 VDC50.ADJ0_MTX_CBB_ADJ1
|
---|
| 904 | #define VDC50ADJ0_MTX_CRR_ADJ0 VDC50.ADJ0_MTX_CRR_ADJ0
|
---|
| 905 | #define VDC50ADJ0_MTX_CRR_ADJ1 VDC50.ADJ0_MTX_CRR_ADJ1
|
---|
| 906 | #define VDC50GR2_UPDATE VDC50.GR2_UPDATE
|
---|
| 907 | #define VDC50GR2_FLM_RD VDC50.GR2_FLM_RD
|
---|
| 908 | #define VDC50GR2_FLM1 VDC50.GR2_FLM1
|
---|
| 909 | #define VDC50GR2_FLM2 VDC50.GR2_FLM2
|
---|
| 910 | #define VDC50GR2_FLM3 VDC50.GR2_FLM3
|
---|
| 911 | #define VDC50GR2_FLM4 VDC50.GR2_FLM4
|
---|
| 912 | #define VDC50GR2_FLM5 VDC50.GR2_FLM5
|
---|
| 913 | #define VDC50GR2_FLM6 VDC50.GR2_FLM6
|
---|
| 914 | #define VDC50GR2_AB1 VDC50.GR2_AB1
|
---|
| 915 | #define VDC50GR2_AB2 VDC50.GR2_AB2
|
---|
| 916 | #define VDC50GR2_AB3 VDC50.GR2_AB3
|
---|
| 917 | #define VDC50GR2_AB4 VDC50.GR2_AB4
|
---|
| 918 | #define VDC50GR2_AB5 VDC50.GR2_AB5
|
---|
| 919 | #define VDC50GR2_AB6 VDC50.GR2_AB6
|
---|
| 920 | #define VDC50GR2_AB7 VDC50.GR2_AB7
|
---|
| 921 | #define VDC50GR2_AB8 VDC50.GR2_AB8
|
---|
| 922 | #define VDC50GR2_AB9 VDC50.GR2_AB9
|
---|
| 923 | #define VDC50GR2_AB10 VDC50.GR2_AB10
|
---|
| 924 | #define VDC50GR2_AB11 VDC50.GR2_AB11
|
---|
| 925 | #define VDC50GR2_BASE VDC50.GR2_BASE
|
---|
| 926 | #define VDC50GR2_CLUT VDC50.GR2_CLUT
|
---|
| 927 | #define VDC50GR2_MON VDC50.GR2_MON
|
---|
| 928 | #define VDC50GR3_UPDATE VDC50.GR3_UPDATE
|
---|
| 929 | #define VDC50GR3_FLM_RD VDC50.GR3_FLM_RD
|
---|
| 930 | #define VDC50GR3_FLM1 VDC50.GR3_FLM1
|
---|
| 931 | #define VDC50GR3_FLM2 VDC50.GR3_FLM2
|
---|
| 932 | #define VDC50GR3_FLM3 VDC50.GR3_FLM3
|
---|
| 933 | #define VDC50GR3_FLM4 VDC50.GR3_FLM4
|
---|
| 934 | #define VDC50GR3_FLM5 VDC50.GR3_FLM5
|
---|
| 935 | #define VDC50GR3_FLM6 VDC50.GR3_FLM6
|
---|
| 936 | #define VDC50GR3_AB1 VDC50.GR3_AB1
|
---|
| 937 | #define VDC50GR3_AB2 VDC50.GR3_AB2
|
---|
| 938 | #define VDC50GR3_AB3 VDC50.GR3_AB3
|
---|
| 939 | #define VDC50GR3_AB4 VDC50.GR3_AB4
|
---|
| 940 | #define VDC50GR3_AB5 VDC50.GR3_AB5
|
---|
| 941 | #define VDC50GR3_AB6 VDC50.GR3_AB6
|
---|
| 942 | #define VDC50GR3_AB7 VDC50.GR3_AB7
|
---|
| 943 | #define VDC50GR3_AB8 VDC50.GR3_AB8
|
---|
| 944 | #define VDC50GR3_AB9 VDC50.GR3_AB9
|
---|
| 945 | #define VDC50GR3_AB10 VDC50.GR3_AB10
|
---|
| 946 | #define VDC50GR3_AB11 VDC50.GR3_AB11
|
---|
| 947 | #define VDC50GR3_BASE VDC50.GR3_BASE
|
---|
| 948 | #define VDC50GR3_CLUT_INT VDC50.GR3_CLUT_INT
|
---|
| 949 | #define VDC50GR3_MON VDC50.GR3_MON
|
---|
| 950 | #define VDC50GAM_G_UPDATE VDC50.GAM_G_UPDATE
|
---|
| 951 | #define VDC50GAM_SW VDC50.GAM_SW
|
---|
| 952 | #define VDC50GAM_G_LUT1 VDC50.GAM_G_LUT1
|
---|
| 953 | #define VDC50GAM_G_LUT2 VDC50.GAM_G_LUT2
|
---|
| 954 | #define VDC50GAM_G_LUT3 VDC50.GAM_G_LUT3
|
---|
| 955 | #define VDC50GAM_G_LUT4 VDC50.GAM_G_LUT4
|
---|
| 956 | #define VDC50GAM_G_LUT5 VDC50.GAM_G_LUT5
|
---|
| 957 | #define VDC50GAM_G_LUT6 VDC50.GAM_G_LUT6
|
---|
| 958 | #define VDC50GAM_G_LUT7 VDC50.GAM_G_LUT7
|
---|
| 959 | #define VDC50GAM_G_LUT8 VDC50.GAM_G_LUT8
|
---|
| 960 | #define VDC50GAM_G_LUT9 VDC50.GAM_G_LUT9
|
---|
| 961 | #define VDC50GAM_G_LUT10 VDC50.GAM_G_LUT10
|
---|
| 962 | #define VDC50GAM_G_LUT11 VDC50.GAM_G_LUT11
|
---|
| 963 | #define VDC50GAM_G_LUT12 VDC50.GAM_G_LUT12
|
---|
| 964 | #define VDC50GAM_G_LUT13 VDC50.GAM_G_LUT13
|
---|
| 965 | #define VDC50GAM_G_LUT14 VDC50.GAM_G_LUT14
|
---|
| 966 | #define VDC50GAM_G_LUT15 VDC50.GAM_G_LUT15
|
---|
| 967 | #define VDC50GAM_G_LUT16 VDC50.GAM_G_LUT16
|
---|
| 968 | #define VDC50GAM_G_AREA1 VDC50.GAM_G_AREA1
|
---|
| 969 | #define VDC50GAM_G_AREA2 VDC50.GAM_G_AREA2
|
---|
| 970 | #define VDC50GAM_G_AREA3 VDC50.GAM_G_AREA3
|
---|
| 971 | #define VDC50GAM_G_AREA4 VDC50.GAM_G_AREA4
|
---|
| 972 | #define VDC50GAM_G_AREA5 VDC50.GAM_G_AREA5
|
---|
| 973 | #define VDC50GAM_G_AREA6 VDC50.GAM_G_AREA6
|
---|
| 974 | #define VDC50GAM_G_AREA7 VDC50.GAM_G_AREA7
|
---|
| 975 | #define VDC50GAM_G_AREA8 VDC50.GAM_G_AREA8
|
---|
| 976 | #define VDC50GAM_B_UPDATE VDC50.GAM_B_UPDATE
|
---|
| 977 | #define VDC50GAM_B_LUT1 VDC50.GAM_B_LUT1
|
---|
| 978 | #define VDC50GAM_B_LUT2 VDC50.GAM_B_LUT2
|
---|
| 979 | #define VDC50GAM_B_LUT3 VDC50.GAM_B_LUT3
|
---|
| 980 | #define VDC50GAM_B_LUT4 VDC50.GAM_B_LUT4
|
---|
| 981 | #define VDC50GAM_B_LUT5 VDC50.GAM_B_LUT5
|
---|
| 982 | #define VDC50GAM_B_LUT6 VDC50.GAM_B_LUT6
|
---|
| 983 | #define VDC50GAM_B_LUT7 VDC50.GAM_B_LUT7
|
---|
| 984 | #define VDC50GAM_B_LUT8 VDC50.GAM_B_LUT8
|
---|
| 985 | #define VDC50GAM_B_LUT9 VDC50.GAM_B_LUT9
|
---|
| 986 | #define VDC50GAM_B_LUT10 VDC50.GAM_B_LUT10
|
---|
| 987 | #define VDC50GAM_B_LUT11 VDC50.GAM_B_LUT11
|
---|
| 988 | #define VDC50GAM_B_LUT12 VDC50.GAM_B_LUT12
|
---|
| 989 | #define VDC50GAM_B_LUT13 VDC50.GAM_B_LUT13
|
---|
| 990 | #define VDC50GAM_B_LUT14 VDC50.GAM_B_LUT14
|
---|
| 991 | #define VDC50GAM_B_LUT15 VDC50.GAM_B_LUT15
|
---|
| 992 | #define VDC50GAM_B_LUT16 VDC50.GAM_B_LUT16
|
---|
| 993 | #define VDC50GAM_B_AREA1 VDC50.GAM_B_AREA1
|
---|
| 994 | #define VDC50GAM_B_AREA2 VDC50.GAM_B_AREA2
|
---|
| 995 | #define VDC50GAM_B_AREA3 VDC50.GAM_B_AREA3
|
---|
| 996 | #define VDC50GAM_B_AREA4 VDC50.GAM_B_AREA4
|
---|
| 997 | #define VDC50GAM_B_AREA5 VDC50.GAM_B_AREA5
|
---|
| 998 | #define VDC50GAM_B_AREA6 VDC50.GAM_B_AREA6
|
---|
| 999 | #define VDC50GAM_B_AREA7 VDC50.GAM_B_AREA7
|
---|
| 1000 | #define VDC50GAM_B_AREA8 VDC50.GAM_B_AREA8
|
---|
| 1001 | #define VDC50GAM_R_UPDATE VDC50.GAM_R_UPDATE
|
---|
| 1002 | #define VDC50GAM_R_LUT1 VDC50.GAM_R_LUT1
|
---|
| 1003 | #define VDC50GAM_R_LUT2 VDC50.GAM_R_LUT2
|
---|
| 1004 | #define VDC50GAM_R_LUT3 VDC50.GAM_R_LUT3
|
---|
| 1005 | #define VDC50GAM_R_LUT4 VDC50.GAM_R_LUT4
|
---|
| 1006 | #define VDC50GAM_R_LUT5 VDC50.GAM_R_LUT5
|
---|
| 1007 | #define VDC50GAM_R_LUT6 VDC50.GAM_R_LUT6
|
---|
| 1008 | #define VDC50GAM_R_LUT7 VDC50.GAM_R_LUT7
|
---|
| 1009 | #define VDC50GAM_R_LUT8 VDC50.GAM_R_LUT8
|
---|
| 1010 | #define VDC50GAM_R_LUT9 VDC50.GAM_R_LUT9
|
---|
| 1011 | #define VDC50GAM_R_LUT10 VDC50.GAM_R_LUT10
|
---|
| 1012 | #define VDC50GAM_R_LUT11 VDC50.GAM_R_LUT11
|
---|
| 1013 | #define VDC50GAM_R_LUT12 VDC50.GAM_R_LUT12
|
---|
| 1014 | #define VDC50GAM_R_LUT13 VDC50.GAM_R_LUT13
|
---|
| 1015 | #define VDC50GAM_R_LUT14 VDC50.GAM_R_LUT14
|
---|
| 1016 | #define VDC50GAM_R_LUT15 VDC50.GAM_R_LUT15
|
---|
| 1017 | #define VDC50GAM_R_LUT16 VDC50.GAM_R_LUT16
|
---|
| 1018 | #define VDC50GAM_R_AREA1 VDC50.GAM_R_AREA1
|
---|
| 1019 | #define VDC50GAM_R_AREA2 VDC50.GAM_R_AREA2
|
---|
| 1020 | #define VDC50GAM_R_AREA3 VDC50.GAM_R_AREA3
|
---|
| 1021 | #define VDC50GAM_R_AREA4 VDC50.GAM_R_AREA4
|
---|
| 1022 | #define VDC50GAM_R_AREA5 VDC50.GAM_R_AREA5
|
---|
| 1023 | #define VDC50GAM_R_AREA6 VDC50.GAM_R_AREA6
|
---|
| 1024 | #define VDC50GAM_R_AREA7 VDC50.GAM_R_AREA7
|
---|
| 1025 | #define VDC50GAM_R_AREA8 VDC50.GAM_R_AREA8
|
---|
| 1026 | #define VDC50TCON_UPDATE VDC50.TCON_UPDATE
|
---|
| 1027 | #define VDC50TCON_TIM VDC50.TCON_TIM
|
---|
| 1028 | #define VDC50TCON_TIM_STVA1 VDC50.TCON_TIM_STVA1
|
---|
| 1029 | #define VDC50TCON_TIM_STVA2 VDC50.TCON_TIM_STVA2
|
---|
| 1030 | #define VDC50TCON_TIM_STVB1 VDC50.TCON_TIM_STVB1
|
---|
| 1031 | #define VDC50TCON_TIM_STVB2 VDC50.TCON_TIM_STVB2
|
---|
| 1032 | #define VDC50TCON_TIM_STH1 VDC50.TCON_TIM_STH1
|
---|
| 1033 | #define VDC50TCON_TIM_STH2 VDC50.TCON_TIM_STH2
|
---|
| 1034 | #define VDC50TCON_TIM_STB1 VDC50.TCON_TIM_STB1
|
---|
| 1035 | #define VDC50TCON_TIM_STB2 VDC50.TCON_TIM_STB2
|
---|
| 1036 | #define VDC50TCON_TIM_CPV1 VDC50.TCON_TIM_CPV1
|
---|
| 1037 | #define VDC50TCON_TIM_CPV2 VDC50.TCON_TIM_CPV2
|
---|
| 1038 | #define VDC50TCON_TIM_POLA1 VDC50.TCON_TIM_POLA1
|
---|
| 1039 | #define VDC50TCON_TIM_POLA2 VDC50.TCON_TIM_POLA2
|
---|
| 1040 | #define VDC50TCON_TIM_POLB1 VDC50.TCON_TIM_POLB1
|
---|
| 1041 | #define VDC50TCON_TIM_POLB2 VDC50.TCON_TIM_POLB2
|
---|
| 1042 | #define VDC50TCON_TIM_DE VDC50.TCON_TIM_DE
|
---|
| 1043 | #define VDC50OUT_UPDATE VDC50.OUT_UPDATE
|
---|
| 1044 | #define VDC50OUT_SET VDC50.OUT_SET
|
---|
| 1045 | #define VDC50OUT_BRIGHT1 VDC50.OUT_BRIGHT1
|
---|
| 1046 | #define VDC50OUT_BRIGHT2 VDC50.OUT_BRIGHT2
|
---|
| 1047 | #define VDC50OUT_CONTRAST VDC50.OUT_CONTRAST
|
---|
| 1048 | #define VDC50OUT_PDTHA VDC50.OUT_PDTHA
|
---|
| 1049 | #define VDC50OUT_CLK_PHASE VDC50.OUT_CLK_PHASE
|
---|
| 1050 | #define VDC50SYSCNT_INT1 VDC50.SYSCNT_INT1
|
---|
| 1051 | #define VDC50SYSCNT_INT2 VDC50.SYSCNT_INT2
|
---|
| 1052 | #define VDC50SYSCNT_INT3 VDC50.SYSCNT_INT3
|
---|
| 1053 | #define VDC50SYSCNT_INT4 VDC50.SYSCNT_INT4
|
---|
| 1054 | #define VDC50SYSCNT_INT5 VDC50.SYSCNT_INT5
|
---|
| 1055 | #define VDC50SYSCNT_INT6 VDC50.SYSCNT_INT6
|
---|
| 1056 | #define VDC50SYSCNT_PANEL_CLK VDC50.SYSCNT_PANEL_CLK
|
---|
| 1057 | #define VDC50SYSCNT_CLUT VDC50.SYSCNT_CLUT
|
---|
| 1058 | #define VDC50SC1_SCL0_UPDATE VDC50.SC1_SCL0_UPDATE
|
---|
| 1059 | #define VDC50SC1_SCL0_FRC1 VDC50.SC1_SCL0_FRC1
|
---|
| 1060 | #define VDC50SC1_SCL0_FRC2 VDC50.SC1_SCL0_FRC2
|
---|
| 1061 | #define VDC50SC1_SCL0_FRC3 VDC50.SC1_SCL0_FRC3
|
---|
| 1062 | #define VDC50SC1_SCL0_FRC4 VDC50.SC1_SCL0_FRC4
|
---|
| 1063 | #define VDC50SC1_SCL0_FRC5 VDC50.SC1_SCL0_FRC5
|
---|
| 1064 | #define VDC50SC1_SCL0_FRC6 VDC50.SC1_SCL0_FRC6
|
---|
| 1065 | #define VDC50SC1_SCL0_FRC7 VDC50.SC1_SCL0_FRC7
|
---|
| 1066 | #define VDC50SC1_SCL0_FRC9 VDC50.SC1_SCL0_FRC9
|
---|
| 1067 | #define VDC50SC1_SCL0_MON0 VDC50.SC1_SCL0_MON0
|
---|
| 1068 | #define VDC50SC1_SCL0_INT VDC50.SC1_SCL0_INT
|
---|
| 1069 | #define VDC50SC1_SCL0_DS1 VDC50.SC1_SCL0_DS1
|
---|
| 1070 | #define VDC50SC1_SCL0_DS2 VDC50.SC1_SCL0_DS2
|
---|
| 1071 | #define VDC50SC1_SCL0_DS3 VDC50.SC1_SCL0_DS3
|
---|
| 1072 | #define VDC50SC1_SCL0_DS4 VDC50.SC1_SCL0_DS4
|
---|
| 1073 | #define VDC50SC1_SCL0_DS5 VDC50.SC1_SCL0_DS5
|
---|
| 1074 | #define VDC50SC1_SCL0_DS6 VDC50.SC1_SCL0_DS6
|
---|
| 1075 | #define VDC50SC1_SCL0_DS7 VDC50.SC1_SCL0_DS7
|
---|
| 1076 | #define VDC50SC1_SCL0_US1 VDC50.SC1_SCL0_US1
|
---|
| 1077 | #define VDC50SC1_SCL0_US2 VDC50.SC1_SCL0_US2
|
---|
| 1078 | #define VDC50SC1_SCL0_US3 VDC50.SC1_SCL0_US3
|
---|
| 1079 | #define VDC50SC1_SCL0_US4 VDC50.SC1_SCL0_US4
|
---|
| 1080 | #define VDC50SC1_SCL0_US5 VDC50.SC1_SCL0_US5
|
---|
| 1081 | #define VDC50SC1_SCL0_US6 VDC50.SC1_SCL0_US6
|
---|
| 1082 | #define VDC50SC1_SCL0_US7 VDC50.SC1_SCL0_US7
|
---|
| 1083 | #define VDC50SC1_SCL0_US8 VDC50.SC1_SCL0_US8
|
---|
| 1084 | #define VDC50SC1_SCL0_OVR1 VDC50.SC1_SCL0_OVR1
|
---|
| 1085 | #define VDC50SC1_SCL1_UPDATE VDC50.SC1_SCL1_UPDATE
|
---|
| 1086 | #define VDC50SC1_SCL1_WR1 VDC50.SC1_SCL1_WR1
|
---|
| 1087 | #define VDC50SC1_SCL1_WR2 VDC50.SC1_SCL1_WR2
|
---|
| 1088 | #define VDC50SC1_SCL1_WR3 VDC50.SC1_SCL1_WR3
|
---|
| 1089 | #define VDC50SC1_SCL1_WR4 VDC50.SC1_SCL1_WR4
|
---|
| 1090 | #define VDC50SC1_SCL1_WR5 VDC50.SC1_SCL1_WR5
|
---|
| 1091 | #define VDC50SC1_SCL1_WR6 VDC50.SC1_SCL1_WR6
|
---|
| 1092 | #define VDC50SC1_SCL1_WR7 VDC50.SC1_SCL1_WR7
|
---|
| 1093 | #define VDC50SC1_SCL1_WR8 VDC50.SC1_SCL1_WR8
|
---|
| 1094 | #define VDC50SC1_SCL1_WR9 VDC50.SC1_SCL1_WR9
|
---|
| 1095 | #define VDC50SC1_SCL1_WR10 VDC50.SC1_SCL1_WR10
|
---|
| 1096 | #define VDC50SC1_SCL1_WR11 VDC50.SC1_SCL1_WR11
|
---|
| 1097 | #define VDC50SC1_SCL1_MON1 VDC50.SC1_SCL1_MON1
|
---|
| 1098 | #define VDC50SC1_SCL1_PBUF0 VDC50.SC1_SCL1_PBUF0
|
---|
| 1099 | #define VDC50SC1_SCL1_PBUF1 VDC50.SC1_SCL1_PBUF1
|
---|
| 1100 | #define VDC50SC1_SCL1_PBUF2 VDC50.SC1_SCL1_PBUF2
|
---|
| 1101 | #define VDC50SC1_SCL1_PBUF3 VDC50.SC1_SCL1_PBUF3
|
---|
| 1102 | #define VDC50SC1_SCL1_PBUF_FLD VDC50.SC1_SCL1_PBUF_FLD
|
---|
| 1103 | #define VDC50SC1_SCL1_PBUF_CNT VDC50.SC1_SCL1_PBUF_CNT
|
---|
| 1104 | #define VDC50GR1_UPDATE VDC50.GR1_UPDATE
|
---|
| 1105 | #define VDC50GR1_FLM_RD VDC50.GR1_FLM_RD
|
---|
| 1106 | #define VDC50GR1_FLM1 VDC50.GR1_FLM1
|
---|
| 1107 | #define VDC50GR1_FLM2 VDC50.GR1_FLM2
|
---|
| 1108 | #define VDC50GR1_FLM3 VDC50.GR1_FLM3
|
---|
| 1109 | #define VDC50GR1_FLM4 VDC50.GR1_FLM4
|
---|
| 1110 | #define VDC50GR1_FLM5 VDC50.GR1_FLM5
|
---|
| 1111 | #define VDC50GR1_FLM6 VDC50.GR1_FLM6
|
---|
| 1112 | #define VDC50GR1_AB1 VDC50.GR1_AB1
|
---|
| 1113 | #define VDC50GR1_AB2 VDC50.GR1_AB2
|
---|
| 1114 | #define VDC50GR1_AB3 VDC50.GR1_AB3
|
---|
| 1115 | #define VDC50GR1_AB4 VDC50.GR1_AB4
|
---|
| 1116 | #define VDC50GR1_AB5 VDC50.GR1_AB5
|
---|
| 1117 | #define VDC50GR1_AB6 VDC50.GR1_AB6
|
---|
| 1118 | #define VDC50GR1_AB7 VDC50.GR1_AB7
|
---|
| 1119 | #define VDC50GR1_AB8 VDC50.GR1_AB8
|
---|
| 1120 | #define VDC50GR1_AB9 VDC50.GR1_AB9
|
---|
| 1121 | #define VDC50GR1_AB10 VDC50.GR1_AB10
|
---|
| 1122 | #define VDC50GR1_AB11 VDC50.GR1_AB11
|
---|
| 1123 | #define VDC50GR1_BASE VDC50.GR1_BASE
|
---|
| 1124 | #define VDC50GR1_CLUT VDC50.GR1_CLUT
|
---|
| 1125 | #define VDC50GR1_MON VDC50.GR1_MON
|
---|
| 1126 | #define VDC50ADJ1_UPDATE VDC50.ADJ1_UPDATE
|
---|
| 1127 | #define VDC50ADJ1_BKSTR_SET VDC50.ADJ1_BKSTR_SET
|
---|
| 1128 | #define VDC50ADJ1_ENH_TIM1 VDC50.ADJ1_ENH_TIM1
|
---|
| 1129 | #define VDC50ADJ1_ENH_TIM2 VDC50.ADJ1_ENH_TIM2
|
---|
| 1130 | #define VDC50ADJ1_ENH_TIM3 VDC50.ADJ1_ENH_TIM3
|
---|
| 1131 | #define VDC50ADJ1_ENH_SHP1 VDC50.ADJ1_ENH_SHP1
|
---|
| 1132 | #define VDC50ADJ1_ENH_SHP2 VDC50.ADJ1_ENH_SHP2
|
---|
| 1133 | #define VDC50ADJ1_ENH_SHP3 VDC50.ADJ1_ENH_SHP3
|
---|
| 1134 | #define VDC50ADJ1_ENH_SHP4 VDC50.ADJ1_ENH_SHP4
|
---|
| 1135 | #define VDC50ADJ1_ENH_SHP5 VDC50.ADJ1_ENH_SHP5
|
---|
| 1136 | #define VDC50ADJ1_ENH_SHP6 VDC50.ADJ1_ENH_SHP6
|
---|
| 1137 | #define VDC50ADJ1_ENH_LTI1 VDC50.ADJ1_ENH_LTI1
|
---|
| 1138 | #define VDC50ADJ1_ENH_LTI2 VDC50.ADJ1_ENH_LTI2
|
---|
| 1139 | #define VDC50ADJ1_MTX_MODE VDC50.ADJ1_MTX_MODE
|
---|
| 1140 | #define VDC50ADJ1_MTX_YG_ADJ0 VDC50.ADJ1_MTX_YG_ADJ0
|
---|
| 1141 | #define VDC50ADJ1_MTX_YG_ADJ1 VDC50.ADJ1_MTX_YG_ADJ1
|
---|
| 1142 | #define VDC50ADJ1_MTX_CBB_ADJ0 VDC50.ADJ1_MTX_CBB_ADJ0
|
---|
| 1143 | #define VDC50ADJ1_MTX_CBB_ADJ1 VDC50.ADJ1_MTX_CBB_ADJ1
|
---|
| 1144 | #define VDC50ADJ1_MTX_CRR_ADJ0 VDC50.ADJ1_MTX_CRR_ADJ0
|
---|
| 1145 | #define VDC50ADJ1_MTX_CRR_ADJ1 VDC50.ADJ1_MTX_CRR_ADJ1
|
---|
| 1146 | #define VDC50GR_VIN_UPDATE VDC50.GR_VIN_UPDATE
|
---|
| 1147 | #define VDC50GR_VIN_AB1 VDC50.GR_VIN_AB1
|
---|
| 1148 | #define VDC50GR_VIN_AB2 VDC50.GR_VIN_AB2
|
---|
| 1149 | #define VDC50GR_VIN_AB3 VDC50.GR_VIN_AB3
|
---|
| 1150 | #define VDC50GR_VIN_AB4 VDC50.GR_VIN_AB4
|
---|
| 1151 | #define VDC50GR_VIN_AB5 VDC50.GR_VIN_AB5
|
---|
| 1152 | #define VDC50GR_VIN_AB6 VDC50.GR_VIN_AB6
|
---|
| 1153 | #define VDC50GR_VIN_AB7 VDC50.GR_VIN_AB7
|
---|
| 1154 | #define VDC50GR_VIN_BASE VDC50.GR_VIN_BASE
|
---|
| 1155 | #define VDC50GR_VIN_MON VDC50.GR_VIN_MON
|
---|
| 1156 | #define VDC50OIR_SCL0_UPDATE VDC50.OIR_SCL0_UPDATE
|
---|
| 1157 | #define VDC50OIR_SCL0_FRC1 VDC50.OIR_SCL0_FRC1
|
---|
| 1158 | #define VDC50OIR_SCL0_FRC2 VDC50.OIR_SCL0_FRC2
|
---|
| 1159 | #define VDC50OIR_SCL0_FRC3 VDC50.OIR_SCL0_FRC3
|
---|
| 1160 | #define VDC50OIR_SCL0_FRC4 VDC50.OIR_SCL0_FRC4
|
---|
| 1161 | #define VDC50OIR_SCL0_FRC5 VDC50.OIR_SCL0_FRC5
|
---|
| 1162 | #define VDC50OIR_SCL0_FRC6 VDC50.OIR_SCL0_FRC6
|
---|
| 1163 | #define VDC50OIR_SCL0_FRC7 VDC50.OIR_SCL0_FRC7
|
---|
| 1164 | #define VDC50OIR_SCL0_DS1 VDC50.OIR_SCL0_DS1
|
---|
| 1165 | #define VDC50OIR_SCL0_DS2 VDC50.OIR_SCL0_DS2
|
---|
| 1166 | #define VDC50OIR_SCL0_DS3 VDC50.OIR_SCL0_DS3
|
---|
| 1167 | #define VDC50OIR_SCL0_DS7 VDC50.OIR_SCL0_DS7
|
---|
| 1168 | #define VDC50OIR_SCL0_US1 VDC50.OIR_SCL0_US1
|
---|
| 1169 | #define VDC50OIR_SCL0_US2 VDC50.OIR_SCL0_US2
|
---|
| 1170 | #define VDC50OIR_SCL0_US3 VDC50.OIR_SCL0_US3
|
---|
| 1171 | #define VDC50OIR_SCL0_US8 VDC50.OIR_SCL0_US8
|
---|
| 1172 | #define VDC50OIR_SCL0_OVR1 VDC50.OIR_SCL0_OVR1
|
---|
| 1173 | #define VDC50OIR_SCL1_UPDATE VDC50.OIR_SCL1_UPDATE
|
---|
| 1174 | #define VDC50OIR_SCL1_WR1 VDC50.OIR_SCL1_WR1
|
---|
| 1175 | #define VDC50OIR_SCL1_WR2 VDC50.OIR_SCL1_WR2
|
---|
| 1176 | #define VDC50OIR_SCL1_WR3 VDC50.OIR_SCL1_WR3
|
---|
| 1177 | #define VDC50OIR_SCL1_WR4 VDC50.OIR_SCL1_WR4
|
---|
| 1178 | #define VDC50OIR_SCL1_WR5 VDC50.OIR_SCL1_WR5
|
---|
| 1179 | #define VDC50OIR_SCL1_WR6 VDC50.OIR_SCL1_WR6
|
---|
| 1180 | #define VDC50OIR_SCL1_WR7 VDC50.OIR_SCL1_WR7
|
---|
| 1181 | #define VDC50GR_OIR_UPDATE VDC50.GR_OIR_UPDATE
|
---|
| 1182 | #define VDC50GR_OIR_FLM_RD VDC50.GR_OIR_FLM_RD
|
---|
| 1183 | #define VDC50GR_OIR_FLM1 VDC50.GR_OIR_FLM1
|
---|
| 1184 | #define VDC50GR_OIR_FLM2 VDC50.GR_OIR_FLM2
|
---|
| 1185 | #define VDC50GR_OIR_FLM3 VDC50.GR_OIR_FLM3
|
---|
| 1186 | #define VDC50GR_OIR_FLM4 VDC50.GR_OIR_FLM4
|
---|
| 1187 | #define VDC50GR_OIR_FLM5 VDC50.GR_OIR_FLM5
|
---|
| 1188 | #define VDC50GR_OIR_FLM6 VDC50.GR_OIR_FLM6
|
---|
| 1189 | #define VDC50GR_OIR_AB1 VDC50.GR_OIR_AB1
|
---|
| 1190 | #define VDC50GR_OIR_AB2 VDC50.GR_OIR_AB2
|
---|
| 1191 | #define VDC50GR_OIR_AB3 VDC50.GR_OIR_AB3
|
---|
| 1192 | #define VDC50GR_OIR_AB7 VDC50.GR_OIR_AB7
|
---|
| 1193 | #define VDC50GR_OIR_AB8 VDC50.GR_OIR_AB8
|
---|
| 1194 | #define VDC50GR_OIR_AB9 VDC50.GR_OIR_AB9
|
---|
| 1195 | #define VDC50GR_OIR_AB10 VDC50.GR_OIR_AB10
|
---|
| 1196 | #define VDC50GR_OIR_AB11 VDC50.GR_OIR_AB11
|
---|
| 1197 | #define VDC50GR_OIR_BASE VDC50.GR_OIR_BASE
|
---|
| 1198 | #define VDC50GR_OIR_CLUT VDC50.GR_OIR_CLUT
|
---|
| 1199 | #define VDC50GR_OIR_MON VDC50.GR_OIR_MON
|
---|
| 1200 | #define VDC51INP_UPDATE VDC51.INP_UPDATE
|
---|
| 1201 | #define VDC51INP_SEL_CNT VDC51.INP_SEL_CNT
|
---|
| 1202 | #define VDC51INP_EXT_SYNC_CNT VDC51.INP_EXT_SYNC_CNT
|
---|
| 1203 | #define VDC51INP_VSYNC_PH_ADJ VDC51.INP_VSYNC_PH_ADJ
|
---|
| 1204 | #define VDC51INP_DLY_ADJ VDC51.INP_DLY_ADJ
|
---|
| 1205 | #define VDC51IMGCNT_UPDATE VDC51.IMGCNT_UPDATE
|
---|
| 1206 | #define VDC51IMGCNT_NR_CNT0 VDC51.IMGCNT_NR_CNT0
|
---|
| 1207 | #define VDC51IMGCNT_NR_CNT1 VDC51.IMGCNT_NR_CNT1
|
---|
| 1208 | #define VDC51IMGCNT_MTX_MODE VDC51.IMGCNT_MTX_MODE
|
---|
| 1209 | #define VDC51IMGCNT_MTX_YG_ADJ0 VDC51.IMGCNT_MTX_YG_ADJ0
|
---|
| 1210 | #define VDC51IMGCNT_MTX_YG_ADJ1 VDC51.IMGCNT_MTX_YG_ADJ1
|
---|
| 1211 | #define VDC51IMGCNT_MTX_CBB_ADJ0 VDC51.IMGCNT_MTX_CBB_ADJ0
|
---|
| 1212 | #define VDC51IMGCNT_MTX_CBB_ADJ1 VDC51.IMGCNT_MTX_CBB_ADJ1
|
---|
| 1213 | #define VDC51IMGCNT_MTX_CRR_ADJ0 VDC51.IMGCNT_MTX_CRR_ADJ0
|
---|
| 1214 | #define VDC51IMGCNT_MTX_CRR_ADJ1 VDC51.IMGCNT_MTX_CRR_ADJ1
|
---|
| 1215 | #define VDC51IMGCNT_DRC_REG VDC51.IMGCNT_DRC_REG
|
---|
| 1216 | #define VDC51SC0_SCL0_UPDATE VDC51.SC0_SCL0_UPDATE
|
---|
| 1217 | #define VDC51SC0_SCL0_FRC1 VDC51.SC0_SCL0_FRC1
|
---|
| 1218 | #define VDC51SC0_SCL0_FRC2 VDC51.SC0_SCL0_FRC2
|
---|
| 1219 | #define VDC51SC0_SCL0_FRC3 VDC51.SC0_SCL0_FRC3
|
---|
| 1220 | #define VDC51SC0_SCL0_FRC4 VDC51.SC0_SCL0_FRC4
|
---|
| 1221 | #define VDC51SC0_SCL0_FRC5 VDC51.SC0_SCL0_FRC5
|
---|
| 1222 | #define VDC51SC0_SCL0_FRC6 VDC51.SC0_SCL0_FRC6
|
---|
| 1223 | #define VDC51SC0_SCL0_FRC7 VDC51.SC0_SCL0_FRC7
|
---|
| 1224 | #define VDC51SC0_SCL0_FRC9 VDC51.SC0_SCL0_FRC9
|
---|
| 1225 | #define VDC51SC0_SCL0_MON0 VDC51.SC0_SCL0_MON0
|
---|
| 1226 | #define VDC51SC0_SCL0_INT VDC51.SC0_SCL0_INT
|
---|
| 1227 | #define VDC51SC0_SCL0_DS1 VDC51.SC0_SCL0_DS1
|
---|
| 1228 | #define VDC51SC0_SCL0_DS2 VDC51.SC0_SCL0_DS2
|
---|
| 1229 | #define VDC51SC0_SCL0_DS3 VDC51.SC0_SCL0_DS3
|
---|
| 1230 | #define VDC51SC0_SCL0_DS4 VDC51.SC0_SCL0_DS4
|
---|
| 1231 | #define VDC51SC0_SCL0_DS5 VDC51.SC0_SCL0_DS5
|
---|
| 1232 | #define VDC51SC0_SCL0_DS6 VDC51.SC0_SCL0_DS6
|
---|
| 1233 | #define VDC51SC0_SCL0_DS7 VDC51.SC0_SCL0_DS7
|
---|
| 1234 | #define VDC51SC0_SCL0_US1 VDC51.SC0_SCL0_US1
|
---|
| 1235 | #define VDC51SC0_SCL0_US2 VDC51.SC0_SCL0_US2
|
---|
| 1236 | #define VDC51SC0_SCL0_US3 VDC51.SC0_SCL0_US3
|
---|
| 1237 | #define VDC51SC0_SCL0_US4 VDC51.SC0_SCL0_US4
|
---|
| 1238 | #define VDC51SC0_SCL0_US5 VDC51.SC0_SCL0_US5
|
---|
| 1239 | #define VDC51SC0_SCL0_US6 VDC51.SC0_SCL0_US6
|
---|
| 1240 | #define VDC51SC0_SCL0_US7 VDC51.SC0_SCL0_US7
|
---|
| 1241 | #define VDC51SC0_SCL0_US8 VDC51.SC0_SCL0_US8
|
---|
| 1242 | #define VDC51SC0_SCL0_OVR1 VDC51.SC0_SCL0_OVR1
|
---|
| 1243 | #define VDC51SC0_SCL1_UPDATE VDC51.SC0_SCL1_UPDATE
|
---|
| 1244 | #define VDC51SC0_SCL1_WR1 VDC51.SC0_SCL1_WR1
|
---|
| 1245 | #define VDC51SC0_SCL1_WR2 VDC51.SC0_SCL1_WR2
|
---|
| 1246 | #define VDC51SC0_SCL1_WR3 VDC51.SC0_SCL1_WR3
|
---|
| 1247 | #define VDC51SC0_SCL1_WR4 VDC51.SC0_SCL1_WR4
|
---|
| 1248 | #define VDC51SC0_SCL1_WR5 VDC51.SC0_SCL1_WR5
|
---|
| 1249 | #define VDC51SC0_SCL1_WR6 VDC51.SC0_SCL1_WR6
|
---|
| 1250 | #define VDC51SC0_SCL1_WR7 VDC51.SC0_SCL1_WR7
|
---|
| 1251 | #define VDC51SC0_SCL1_WR8 VDC51.SC0_SCL1_WR8
|
---|
| 1252 | #define VDC51SC0_SCL1_WR9 VDC51.SC0_SCL1_WR9
|
---|
| 1253 | #define VDC51SC0_SCL1_WR10 VDC51.SC0_SCL1_WR10
|
---|
| 1254 | #define VDC51SC0_SCL1_WR11 VDC51.SC0_SCL1_WR11
|
---|
| 1255 | #define VDC51SC0_SCL1_MON1 VDC51.SC0_SCL1_MON1
|
---|
| 1256 | #define VDC51SC0_SCL1_PBUF0 VDC51.SC0_SCL1_PBUF0
|
---|
| 1257 | #define VDC51SC0_SCL1_PBUF1 VDC51.SC0_SCL1_PBUF1
|
---|
| 1258 | #define VDC51SC0_SCL1_PBUF2 VDC51.SC0_SCL1_PBUF2
|
---|
| 1259 | #define VDC51SC0_SCL1_PBUF3 VDC51.SC0_SCL1_PBUF3
|
---|
| 1260 | #define VDC51SC0_SCL1_PBUF_FLD VDC51.SC0_SCL1_PBUF_FLD
|
---|
| 1261 | #define VDC51SC0_SCL1_PBUF_CNT VDC51.SC0_SCL1_PBUF_CNT
|
---|
| 1262 | #define VDC51GR0_UPDATE VDC51.GR0_UPDATE
|
---|
| 1263 | #define VDC51GR0_FLM_RD VDC51.GR0_FLM_RD
|
---|
| 1264 | #define VDC51GR0_FLM1 VDC51.GR0_FLM1
|
---|
| 1265 | #define VDC51GR0_FLM2 VDC51.GR0_FLM2
|
---|
| 1266 | #define VDC51GR0_FLM3 VDC51.GR0_FLM3
|
---|
| 1267 | #define VDC51GR0_FLM4 VDC51.GR0_FLM4
|
---|
| 1268 | #define VDC51GR0_FLM5 VDC51.GR0_FLM5
|
---|
| 1269 | #define VDC51GR0_FLM6 VDC51.GR0_FLM6
|
---|
| 1270 | #define VDC51GR0_AB1 VDC51.GR0_AB1
|
---|
| 1271 | #define VDC51GR0_AB2 VDC51.GR0_AB2
|
---|
| 1272 | #define VDC51GR0_AB3 VDC51.GR0_AB3
|
---|
| 1273 | #define VDC51GR0_AB7 VDC51.GR0_AB7
|
---|
| 1274 | #define VDC51GR0_AB8 VDC51.GR0_AB8
|
---|
| 1275 | #define VDC51GR0_AB9 VDC51.GR0_AB9
|
---|
| 1276 | #define VDC51GR0_AB10 VDC51.GR0_AB10
|
---|
| 1277 | #define VDC51GR0_AB11 VDC51.GR0_AB11
|
---|
| 1278 | #define VDC51GR0_BASE VDC51.GR0_BASE
|
---|
| 1279 | #define VDC51GR0_CLUT VDC51.GR0_CLUT
|
---|
| 1280 | #define VDC51ADJ0_UPDATE VDC51.ADJ0_UPDATE
|
---|
| 1281 | #define VDC51ADJ0_BKSTR_SET VDC51.ADJ0_BKSTR_SET
|
---|
| 1282 | #define VDC51ADJ0_ENH_TIM1 VDC51.ADJ0_ENH_TIM1
|
---|
| 1283 | #define VDC51ADJ0_ENH_TIM2 VDC51.ADJ0_ENH_TIM2
|
---|
| 1284 | #define VDC51ADJ0_ENH_TIM3 VDC51.ADJ0_ENH_TIM3
|
---|
| 1285 | #define VDC51ADJ0_ENH_SHP1 VDC51.ADJ0_ENH_SHP1
|
---|
| 1286 | #define VDC51ADJ0_ENH_SHP2 VDC51.ADJ0_ENH_SHP2
|
---|
| 1287 | #define VDC51ADJ0_ENH_SHP3 VDC51.ADJ0_ENH_SHP3
|
---|
| 1288 | #define VDC51ADJ0_ENH_SHP4 VDC51.ADJ0_ENH_SHP4
|
---|
| 1289 | #define VDC51ADJ0_ENH_SHP5 VDC51.ADJ0_ENH_SHP5
|
---|
| 1290 | #define VDC51ADJ0_ENH_SHP6 VDC51.ADJ0_ENH_SHP6
|
---|
| 1291 | #define VDC51ADJ0_ENH_LTI1 VDC51.ADJ0_ENH_LTI1
|
---|
| 1292 | #define VDC51ADJ0_ENH_LTI2 VDC51.ADJ0_ENH_LTI2
|
---|
| 1293 | #define VDC51ADJ0_MTX_MODE VDC51.ADJ0_MTX_MODE
|
---|
| 1294 | #define VDC51ADJ0_MTX_YG_ADJ0 VDC51.ADJ0_MTX_YG_ADJ0
|
---|
| 1295 | #define VDC51ADJ0_MTX_YG_ADJ1 VDC51.ADJ0_MTX_YG_ADJ1
|
---|
| 1296 | #define VDC51ADJ0_MTX_CBB_ADJ0 VDC51.ADJ0_MTX_CBB_ADJ0
|
---|
| 1297 | #define VDC51ADJ0_MTX_CBB_ADJ1 VDC51.ADJ0_MTX_CBB_ADJ1
|
---|
| 1298 | #define VDC51ADJ0_MTX_CRR_ADJ0 VDC51.ADJ0_MTX_CRR_ADJ0
|
---|
| 1299 | #define VDC51ADJ0_MTX_CRR_ADJ1 VDC51.ADJ0_MTX_CRR_ADJ1
|
---|
| 1300 | #define VDC51GR2_UPDATE VDC51.GR2_UPDATE
|
---|
| 1301 | #define VDC51GR2_FLM_RD VDC51.GR2_FLM_RD
|
---|
| 1302 | #define VDC51GR2_FLM1 VDC51.GR2_FLM1
|
---|
| 1303 | #define VDC51GR2_FLM2 VDC51.GR2_FLM2
|
---|
| 1304 | #define VDC51GR2_FLM3 VDC51.GR2_FLM3
|
---|
| 1305 | #define VDC51GR2_FLM4 VDC51.GR2_FLM4
|
---|
| 1306 | #define VDC51GR2_FLM5 VDC51.GR2_FLM5
|
---|
| 1307 | #define VDC51GR2_FLM6 VDC51.GR2_FLM6
|
---|
| 1308 | #define VDC51GR2_AB1 VDC51.GR2_AB1
|
---|
| 1309 | #define VDC51GR2_AB2 VDC51.GR2_AB2
|
---|
| 1310 | #define VDC51GR2_AB3 VDC51.GR2_AB3
|
---|
| 1311 | #define VDC51GR2_AB4 VDC51.GR2_AB4
|
---|
| 1312 | #define VDC51GR2_AB5 VDC51.GR2_AB5
|
---|
| 1313 | #define VDC51GR2_AB6 VDC51.GR2_AB6
|
---|
| 1314 | #define VDC51GR2_AB7 VDC51.GR2_AB7
|
---|
| 1315 | #define VDC51GR2_AB8 VDC51.GR2_AB8
|
---|
| 1316 | #define VDC51GR2_AB9 VDC51.GR2_AB9
|
---|
| 1317 | #define VDC51GR2_AB10 VDC51.GR2_AB10
|
---|
| 1318 | #define VDC51GR2_AB11 VDC51.GR2_AB11
|
---|
| 1319 | #define VDC51GR2_BASE VDC51.GR2_BASE
|
---|
| 1320 | #define VDC51GR2_CLUT VDC51.GR2_CLUT
|
---|
| 1321 | #define VDC51GR2_MON VDC51.GR2_MON
|
---|
| 1322 | #define VDC51GR3_UPDATE VDC51.GR3_UPDATE
|
---|
| 1323 | #define VDC51GR3_FLM_RD VDC51.GR3_FLM_RD
|
---|
| 1324 | #define VDC51GR3_FLM1 VDC51.GR3_FLM1
|
---|
| 1325 | #define VDC51GR3_FLM2 VDC51.GR3_FLM2
|
---|
| 1326 | #define VDC51GR3_FLM3 VDC51.GR3_FLM3
|
---|
| 1327 | #define VDC51GR3_FLM4 VDC51.GR3_FLM4
|
---|
| 1328 | #define VDC51GR3_FLM5 VDC51.GR3_FLM5
|
---|
| 1329 | #define VDC51GR3_FLM6 VDC51.GR3_FLM6
|
---|
| 1330 | #define VDC51GR3_AB1 VDC51.GR3_AB1
|
---|
| 1331 | #define VDC51GR3_AB2 VDC51.GR3_AB2
|
---|
| 1332 | #define VDC51GR3_AB3 VDC51.GR3_AB3
|
---|
| 1333 | #define VDC51GR3_AB4 VDC51.GR3_AB4
|
---|
| 1334 | #define VDC51GR3_AB5 VDC51.GR3_AB5
|
---|
| 1335 | #define VDC51GR3_AB6 VDC51.GR3_AB6
|
---|
| 1336 | #define VDC51GR3_AB7 VDC51.GR3_AB7
|
---|
| 1337 | #define VDC51GR3_AB8 VDC51.GR3_AB8
|
---|
| 1338 | #define VDC51GR3_AB9 VDC51.GR3_AB9
|
---|
| 1339 | #define VDC51GR3_AB10 VDC51.GR3_AB10
|
---|
| 1340 | #define VDC51GR3_AB11 VDC51.GR3_AB11
|
---|
| 1341 | #define VDC51GR3_BASE VDC51.GR3_BASE
|
---|
| 1342 | #define VDC51GR3_CLUT_INT VDC51.GR3_CLUT_INT
|
---|
| 1343 | #define VDC51GR3_MON VDC51.GR3_MON
|
---|
| 1344 | #define VDC51GAM_G_UPDATE VDC51.GAM_G_UPDATE
|
---|
| 1345 | #define VDC51GAM_SW VDC51.GAM_SW
|
---|
| 1346 | #define VDC51GAM_G_LUT1 VDC51.GAM_G_LUT1
|
---|
| 1347 | #define VDC51GAM_G_LUT2 VDC51.GAM_G_LUT2
|
---|
| 1348 | #define VDC51GAM_G_LUT3 VDC51.GAM_G_LUT3
|
---|
| 1349 | #define VDC51GAM_G_LUT4 VDC51.GAM_G_LUT4
|
---|
| 1350 | #define VDC51GAM_G_LUT5 VDC51.GAM_G_LUT5
|
---|
| 1351 | #define VDC51GAM_G_LUT6 VDC51.GAM_G_LUT6
|
---|
| 1352 | #define VDC51GAM_G_LUT7 VDC51.GAM_G_LUT7
|
---|
| 1353 | #define VDC51GAM_G_LUT8 VDC51.GAM_G_LUT8
|
---|
| 1354 | #define VDC51GAM_G_LUT9 VDC51.GAM_G_LUT9
|
---|
| 1355 | #define VDC51GAM_G_LUT10 VDC51.GAM_G_LUT10
|
---|
| 1356 | #define VDC51GAM_G_LUT11 VDC51.GAM_G_LUT11
|
---|
| 1357 | #define VDC51GAM_G_LUT12 VDC51.GAM_G_LUT12
|
---|
| 1358 | #define VDC51GAM_G_LUT13 VDC51.GAM_G_LUT13
|
---|
| 1359 | #define VDC51GAM_G_LUT14 VDC51.GAM_G_LUT14
|
---|
| 1360 | #define VDC51GAM_G_LUT15 VDC51.GAM_G_LUT15
|
---|
| 1361 | #define VDC51GAM_G_LUT16 VDC51.GAM_G_LUT16
|
---|
| 1362 | #define VDC51GAM_G_AREA1 VDC51.GAM_G_AREA1
|
---|
| 1363 | #define VDC51GAM_G_AREA2 VDC51.GAM_G_AREA2
|
---|
| 1364 | #define VDC51GAM_G_AREA3 VDC51.GAM_G_AREA3
|
---|
| 1365 | #define VDC51GAM_G_AREA4 VDC51.GAM_G_AREA4
|
---|
| 1366 | #define VDC51GAM_G_AREA5 VDC51.GAM_G_AREA5
|
---|
| 1367 | #define VDC51GAM_G_AREA6 VDC51.GAM_G_AREA6
|
---|
| 1368 | #define VDC51GAM_G_AREA7 VDC51.GAM_G_AREA7
|
---|
| 1369 | #define VDC51GAM_G_AREA8 VDC51.GAM_G_AREA8
|
---|
| 1370 | #define VDC51GAM_B_UPDATE VDC51.GAM_B_UPDATE
|
---|
| 1371 | #define VDC51GAM_B_LUT1 VDC51.GAM_B_LUT1
|
---|
| 1372 | #define VDC51GAM_B_LUT2 VDC51.GAM_B_LUT2
|
---|
| 1373 | #define VDC51GAM_B_LUT3 VDC51.GAM_B_LUT3
|
---|
| 1374 | #define VDC51GAM_B_LUT4 VDC51.GAM_B_LUT4
|
---|
| 1375 | #define VDC51GAM_B_LUT5 VDC51.GAM_B_LUT5
|
---|
| 1376 | #define VDC51GAM_B_LUT6 VDC51.GAM_B_LUT6
|
---|
| 1377 | #define VDC51GAM_B_LUT7 VDC51.GAM_B_LUT7
|
---|
| 1378 | #define VDC51GAM_B_LUT8 VDC51.GAM_B_LUT8
|
---|
| 1379 | #define VDC51GAM_B_LUT9 VDC51.GAM_B_LUT9
|
---|
| 1380 | #define VDC51GAM_B_LUT10 VDC51.GAM_B_LUT10
|
---|
| 1381 | #define VDC51GAM_B_LUT11 VDC51.GAM_B_LUT11
|
---|
| 1382 | #define VDC51GAM_B_LUT12 VDC51.GAM_B_LUT12
|
---|
| 1383 | #define VDC51GAM_B_LUT13 VDC51.GAM_B_LUT13
|
---|
| 1384 | #define VDC51GAM_B_LUT14 VDC51.GAM_B_LUT14
|
---|
| 1385 | #define VDC51GAM_B_LUT15 VDC51.GAM_B_LUT15
|
---|
| 1386 | #define VDC51GAM_B_LUT16 VDC51.GAM_B_LUT16
|
---|
| 1387 | #define VDC51GAM_B_AREA1 VDC51.GAM_B_AREA1
|
---|
| 1388 | #define VDC51GAM_B_AREA2 VDC51.GAM_B_AREA2
|
---|
| 1389 | #define VDC51GAM_B_AREA3 VDC51.GAM_B_AREA3
|
---|
| 1390 | #define VDC51GAM_B_AREA4 VDC51.GAM_B_AREA4
|
---|
| 1391 | #define VDC51GAM_B_AREA5 VDC51.GAM_B_AREA5
|
---|
| 1392 | #define VDC51GAM_B_AREA6 VDC51.GAM_B_AREA6
|
---|
| 1393 | #define VDC51GAM_B_AREA7 VDC51.GAM_B_AREA7
|
---|
| 1394 | #define VDC51GAM_B_AREA8 VDC51.GAM_B_AREA8
|
---|
| 1395 | #define VDC51GAM_R_UPDATE VDC51.GAM_R_UPDATE
|
---|
| 1396 | #define VDC51GAM_R_LUT1 VDC51.GAM_R_LUT1
|
---|
| 1397 | #define VDC51GAM_R_LUT2 VDC51.GAM_R_LUT2
|
---|
| 1398 | #define VDC51GAM_R_LUT3 VDC51.GAM_R_LUT3
|
---|
| 1399 | #define VDC51GAM_R_LUT4 VDC51.GAM_R_LUT4
|
---|
| 1400 | #define VDC51GAM_R_LUT5 VDC51.GAM_R_LUT5
|
---|
| 1401 | #define VDC51GAM_R_LUT6 VDC51.GAM_R_LUT6
|
---|
| 1402 | #define VDC51GAM_R_LUT7 VDC51.GAM_R_LUT7
|
---|
| 1403 | #define VDC51GAM_R_LUT8 VDC51.GAM_R_LUT8
|
---|
| 1404 | #define VDC51GAM_R_LUT9 VDC51.GAM_R_LUT9
|
---|
| 1405 | #define VDC51GAM_R_LUT10 VDC51.GAM_R_LUT10
|
---|
| 1406 | #define VDC51GAM_R_LUT11 VDC51.GAM_R_LUT11
|
---|
| 1407 | #define VDC51GAM_R_LUT12 VDC51.GAM_R_LUT12
|
---|
| 1408 | #define VDC51GAM_R_LUT13 VDC51.GAM_R_LUT13
|
---|
| 1409 | #define VDC51GAM_R_LUT14 VDC51.GAM_R_LUT14
|
---|
| 1410 | #define VDC51GAM_R_LUT15 VDC51.GAM_R_LUT15
|
---|
| 1411 | #define VDC51GAM_R_LUT16 VDC51.GAM_R_LUT16
|
---|
| 1412 | #define VDC51GAM_R_AREA1 VDC51.GAM_R_AREA1
|
---|
| 1413 | #define VDC51GAM_R_AREA2 VDC51.GAM_R_AREA2
|
---|
| 1414 | #define VDC51GAM_R_AREA3 VDC51.GAM_R_AREA3
|
---|
| 1415 | #define VDC51GAM_R_AREA4 VDC51.GAM_R_AREA4
|
---|
| 1416 | #define VDC51GAM_R_AREA5 VDC51.GAM_R_AREA5
|
---|
| 1417 | #define VDC51GAM_R_AREA6 VDC51.GAM_R_AREA6
|
---|
| 1418 | #define VDC51GAM_R_AREA7 VDC51.GAM_R_AREA7
|
---|
| 1419 | #define VDC51GAM_R_AREA8 VDC51.GAM_R_AREA8
|
---|
| 1420 | #define VDC51TCON_UPDATE VDC51.TCON_UPDATE
|
---|
| 1421 | #define VDC51TCON_TIM VDC51.TCON_TIM
|
---|
| 1422 | #define VDC51TCON_TIM_STVA1 VDC51.TCON_TIM_STVA1
|
---|
| 1423 | #define VDC51TCON_TIM_STVA2 VDC51.TCON_TIM_STVA2
|
---|
| 1424 | #define VDC51TCON_TIM_STVB1 VDC51.TCON_TIM_STVB1
|
---|
| 1425 | #define VDC51TCON_TIM_STVB2 VDC51.TCON_TIM_STVB2
|
---|
| 1426 | #define VDC51TCON_TIM_STH1 VDC51.TCON_TIM_STH1
|
---|
| 1427 | #define VDC51TCON_TIM_STH2 VDC51.TCON_TIM_STH2
|
---|
| 1428 | #define VDC51TCON_TIM_STB1 VDC51.TCON_TIM_STB1
|
---|
| 1429 | #define VDC51TCON_TIM_STB2 VDC51.TCON_TIM_STB2
|
---|
| 1430 | #define VDC51TCON_TIM_CPV1 VDC51.TCON_TIM_CPV1
|
---|
| 1431 | #define VDC51TCON_TIM_CPV2 VDC51.TCON_TIM_CPV2
|
---|
| 1432 | #define VDC51TCON_TIM_POLA1 VDC51.TCON_TIM_POLA1
|
---|
| 1433 | #define VDC51TCON_TIM_POLA2 VDC51.TCON_TIM_POLA2
|
---|
| 1434 | #define VDC51TCON_TIM_POLB1 VDC51.TCON_TIM_POLB1
|
---|
| 1435 | #define VDC51TCON_TIM_POLB2 VDC51.TCON_TIM_POLB2
|
---|
| 1436 | #define VDC51TCON_TIM_DE VDC51.TCON_TIM_DE
|
---|
| 1437 | #define VDC51OUT_UPDATE VDC51.OUT_UPDATE
|
---|
| 1438 | #define VDC51OUT_SET VDC51.OUT_SET
|
---|
| 1439 | #define VDC51OUT_BRIGHT1 VDC51.OUT_BRIGHT1
|
---|
| 1440 | #define VDC51OUT_BRIGHT2 VDC51.OUT_BRIGHT2
|
---|
| 1441 | #define VDC51OUT_CONTRAST VDC51.OUT_CONTRAST
|
---|
| 1442 | #define VDC51OUT_PDTHA VDC51.OUT_PDTHA
|
---|
| 1443 | #define VDC51OUT_CLK_PHASE VDC51.OUT_CLK_PHASE
|
---|
| 1444 | #define VDC51SYSCNT_INT1 VDC51.SYSCNT_INT1
|
---|
| 1445 | #define VDC51SYSCNT_INT2 VDC51.SYSCNT_INT2
|
---|
| 1446 | #define VDC51SYSCNT_INT3 VDC51.SYSCNT_INT3
|
---|
| 1447 | #define VDC51SYSCNT_INT4 VDC51.SYSCNT_INT4
|
---|
| 1448 | #define VDC51SYSCNT_INT5 VDC51.SYSCNT_INT5
|
---|
| 1449 | #define VDC51SYSCNT_INT6 VDC51.SYSCNT_INT6
|
---|
| 1450 | #define VDC51SYSCNT_PANEL_CLK VDC51.SYSCNT_PANEL_CLK
|
---|
| 1451 | #define VDC51SYSCNT_CLUT VDC51.SYSCNT_CLUT
|
---|
| 1452 | #define VDC51SC1_SCL0_UPDATE VDC51.SC1_SCL0_UPDATE
|
---|
| 1453 | #define VDC51SC1_SCL0_FRC1 VDC51.SC1_SCL0_FRC1
|
---|
| 1454 | #define VDC51SC1_SCL0_FRC2 VDC51.SC1_SCL0_FRC2
|
---|
| 1455 | #define VDC51SC1_SCL0_FRC3 VDC51.SC1_SCL0_FRC3
|
---|
| 1456 | #define VDC51SC1_SCL0_FRC4 VDC51.SC1_SCL0_FRC4
|
---|
| 1457 | #define VDC51SC1_SCL0_FRC5 VDC51.SC1_SCL0_FRC5
|
---|
| 1458 | #define VDC51SC1_SCL0_FRC6 VDC51.SC1_SCL0_FRC6
|
---|
| 1459 | #define VDC51SC1_SCL0_FRC7 VDC51.SC1_SCL0_FRC7
|
---|
| 1460 | #define VDC51SC1_SCL0_FRC9 VDC51.SC1_SCL0_FRC9
|
---|
| 1461 | #define VDC51SC1_SCL0_MON0 VDC51.SC1_SCL0_MON0
|
---|
| 1462 | #define VDC51SC1_SCL0_INT VDC51.SC1_SCL0_INT
|
---|
| 1463 | #define VDC51SC1_SCL0_DS1 VDC51.SC1_SCL0_DS1
|
---|
| 1464 | #define VDC51SC1_SCL0_DS2 VDC51.SC1_SCL0_DS2
|
---|
| 1465 | #define VDC51SC1_SCL0_DS3 VDC51.SC1_SCL0_DS3
|
---|
| 1466 | #define VDC51SC1_SCL0_DS4 VDC51.SC1_SCL0_DS4
|
---|
| 1467 | #define VDC51SC1_SCL0_DS5 VDC51.SC1_SCL0_DS5
|
---|
| 1468 | #define VDC51SC1_SCL0_DS6 VDC51.SC1_SCL0_DS6
|
---|
| 1469 | #define VDC51SC1_SCL0_DS7 VDC51.SC1_SCL0_DS7
|
---|
| 1470 | #define VDC51SC1_SCL0_US1 VDC51.SC1_SCL0_US1
|
---|
| 1471 | #define VDC51SC1_SCL0_US2 VDC51.SC1_SCL0_US2
|
---|
| 1472 | #define VDC51SC1_SCL0_US3 VDC51.SC1_SCL0_US3
|
---|
| 1473 | #define VDC51SC1_SCL0_US4 VDC51.SC1_SCL0_US4
|
---|
| 1474 | #define VDC51SC1_SCL0_US5 VDC51.SC1_SCL0_US5
|
---|
| 1475 | #define VDC51SC1_SCL0_US6 VDC51.SC1_SCL0_US6
|
---|
| 1476 | #define VDC51SC1_SCL0_US7 VDC51.SC1_SCL0_US7
|
---|
| 1477 | #define VDC51SC1_SCL0_US8 VDC51.SC1_SCL0_US8
|
---|
| 1478 | #define VDC51SC1_SCL0_OVR1 VDC51.SC1_SCL0_OVR1
|
---|
| 1479 | #define VDC51SC1_SCL1_UPDATE VDC51.SC1_SCL1_UPDATE
|
---|
| 1480 | #define VDC51SC1_SCL1_WR1 VDC51.SC1_SCL1_WR1
|
---|
| 1481 | #define VDC51SC1_SCL1_WR2 VDC51.SC1_SCL1_WR2
|
---|
| 1482 | #define VDC51SC1_SCL1_WR3 VDC51.SC1_SCL1_WR3
|
---|
| 1483 | #define VDC51SC1_SCL1_WR4 VDC51.SC1_SCL1_WR4
|
---|
| 1484 | #define VDC51SC1_SCL1_WR5 VDC51.SC1_SCL1_WR5
|
---|
| 1485 | #define VDC51SC1_SCL1_WR6 VDC51.SC1_SCL1_WR6
|
---|
| 1486 | #define VDC51SC1_SCL1_WR7 VDC51.SC1_SCL1_WR7
|
---|
| 1487 | #define VDC51SC1_SCL1_WR8 VDC51.SC1_SCL1_WR8
|
---|
| 1488 | #define VDC51SC1_SCL1_WR9 VDC51.SC1_SCL1_WR9
|
---|
| 1489 | #define VDC51SC1_SCL1_WR10 VDC51.SC1_SCL1_WR10
|
---|
| 1490 | #define VDC51SC1_SCL1_WR11 VDC51.SC1_SCL1_WR11
|
---|
| 1491 | #define VDC51SC1_SCL1_MON1 VDC51.SC1_SCL1_MON1
|
---|
| 1492 | #define VDC51SC1_SCL1_PBUF0 VDC51.SC1_SCL1_PBUF0
|
---|
| 1493 | #define VDC51SC1_SCL1_PBUF1 VDC51.SC1_SCL1_PBUF1
|
---|
| 1494 | #define VDC51SC1_SCL1_PBUF2 VDC51.SC1_SCL1_PBUF2
|
---|
| 1495 | #define VDC51SC1_SCL1_PBUF3 VDC51.SC1_SCL1_PBUF3
|
---|
| 1496 | #define VDC51SC1_SCL1_PBUF_FLD VDC51.SC1_SCL1_PBUF_FLD
|
---|
| 1497 | #define VDC51SC1_SCL1_PBUF_CNT VDC51.SC1_SCL1_PBUF_CNT
|
---|
| 1498 | #define VDC51GR1_UPDATE VDC51.GR1_UPDATE
|
---|
| 1499 | #define VDC51GR1_FLM_RD VDC51.GR1_FLM_RD
|
---|
| 1500 | #define VDC51GR1_FLM1 VDC51.GR1_FLM1
|
---|
| 1501 | #define VDC51GR1_FLM2 VDC51.GR1_FLM2
|
---|
| 1502 | #define VDC51GR1_FLM3 VDC51.GR1_FLM3
|
---|
| 1503 | #define VDC51GR1_FLM4 VDC51.GR1_FLM4
|
---|
| 1504 | #define VDC51GR1_FLM5 VDC51.GR1_FLM5
|
---|
| 1505 | #define VDC51GR1_FLM6 VDC51.GR1_FLM6
|
---|
| 1506 | #define VDC51GR1_AB1 VDC51.GR1_AB1
|
---|
| 1507 | #define VDC51GR1_AB2 VDC51.GR1_AB2
|
---|
| 1508 | #define VDC51GR1_AB3 VDC51.GR1_AB3
|
---|
| 1509 | #define VDC51GR1_AB4 VDC51.GR1_AB4
|
---|
| 1510 | #define VDC51GR1_AB5 VDC51.GR1_AB5
|
---|
| 1511 | #define VDC51GR1_AB6 VDC51.GR1_AB6
|
---|
| 1512 | #define VDC51GR1_AB7 VDC51.GR1_AB7
|
---|
| 1513 | #define VDC51GR1_AB8 VDC51.GR1_AB8
|
---|
| 1514 | #define VDC51GR1_AB9 VDC51.GR1_AB9
|
---|
| 1515 | #define VDC51GR1_AB10 VDC51.GR1_AB10
|
---|
| 1516 | #define VDC51GR1_AB11 VDC51.GR1_AB11
|
---|
| 1517 | #define VDC51GR1_BASE VDC51.GR1_BASE
|
---|
| 1518 | #define VDC51GR1_CLUT VDC51.GR1_CLUT
|
---|
| 1519 | #define VDC51GR1_MON VDC51.GR1_MON
|
---|
| 1520 | #define VDC51ADJ1_UPDATE VDC51.ADJ1_UPDATE
|
---|
| 1521 | #define VDC51ADJ1_BKSTR_SET VDC51.ADJ1_BKSTR_SET
|
---|
| 1522 | #define VDC51ADJ1_ENH_TIM1 VDC51.ADJ1_ENH_TIM1
|
---|
| 1523 | #define VDC51ADJ1_ENH_TIM2 VDC51.ADJ1_ENH_TIM2
|
---|
| 1524 | #define VDC51ADJ1_ENH_TIM3 VDC51.ADJ1_ENH_TIM3
|
---|
| 1525 | #define VDC51ADJ1_ENH_SHP1 VDC51.ADJ1_ENH_SHP1
|
---|
| 1526 | #define VDC51ADJ1_ENH_SHP2 VDC51.ADJ1_ENH_SHP2
|
---|
| 1527 | #define VDC51ADJ1_ENH_SHP3 VDC51.ADJ1_ENH_SHP3
|
---|
| 1528 | #define VDC51ADJ1_ENH_SHP4 VDC51.ADJ1_ENH_SHP4
|
---|
| 1529 | #define VDC51ADJ1_ENH_SHP5 VDC51.ADJ1_ENH_SHP5
|
---|
| 1530 | #define VDC51ADJ1_ENH_SHP6 VDC51.ADJ1_ENH_SHP6
|
---|
| 1531 | #define VDC51ADJ1_ENH_LTI1 VDC51.ADJ1_ENH_LTI1
|
---|
| 1532 | #define VDC51ADJ1_ENH_LTI2 VDC51.ADJ1_ENH_LTI2
|
---|
| 1533 | #define VDC51ADJ1_MTX_MODE VDC51.ADJ1_MTX_MODE
|
---|
| 1534 | #define VDC51ADJ1_MTX_YG_ADJ0 VDC51.ADJ1_MTX_YG_ADJ0
|
---|
| 1535 | #define VDC51ADJ1_MTX_YG_ADJ1 VDC51.ADJ1_MTX_YG_ADJ1
|
---|
| 1536 | #define VDC51ADJ1_MTX_CBB_ADJ0 VDC51.ADJ1_MTX_CBB_ADJ0
|
---|
| 1537 | #define VDC51ADJ1_MTX_CBB_ADJ1 VDC51.ADJ1_MTX_CBB_ADJ1
|
---|
| 1538 | #define VDC51ADJ1_MTX_CRR_ADJ0 VDC51.ADJ1_MTX_CRR_ADJ0
|
---|
| 1539 | #define VDC51ADJ1_MTX_CRR_ADJ1 VDC51.ADJ1_MTX_CRR_ADJ1
|
---|
| 1540 | #define VDC51GR_VIN_UPDATE VDC51.GR_VIN_UPDATE
|
---|
| 1541 | #define VDC51GR_VIN_AB1 VDC51.GR_VIN_AB1
|
---|
| 1542 | #define VDC51GR_VIN_AB2 VDC51.GR_VIN_AB2
|
---|
| 1543 | #define VDC51GR_VIN_AB3 VDC51.GR_VIN_AB3
|
---|
| 1544 | #define VDC51GR_VIN_AB4 VDC51.GR_VIN_AB4
|
---|
| 1545 | #define VDC51GR_VIN_AB5 VDC51.GR_VIN_AB5
|
---|
| 1546 | #define VDC51GR_VIN_AB6 VDC51.GR_VIN_AB6
|
---|
| 1547 | #define VDC51GR_VIN_AB7 VDC51.GR_VIN_AB7
|
---|
| 1548 | #define VDC51GR_VIN_BASE VDC51.GR_VIN_BASE
|
---|
| 1549 | #define VDC51GR_VIN_MON VDC51.GR_VIN_MON
|
---|
| 1550 | #define VDC51OIR_SCL0_UPDATE VDC51.OIR_SCL0_UPDATE
|
---|
| 1551 | #define VDC51OIR_SCL0_FRC1 VDC51.OIR_SCL0_FRC1
|
---|
| 1552 | #define VDC51OIR_SCL0_FRC2 VDC51.OIR_SCL0_FRC2
|
---|
| 1553 | #define VDC51OIR_SCL0_FRC3 VDC51.OIR_SCL0_FRC3
|
---|
| 1554 | #define VDC51OIR_SCL0_FRC4 VDC51.OIR_SCL0_FRC4
|
---|
| 1555 | #define VDC51OIR_SCL0_FRC5 VDC51.OIR_SCL0_FRC5
|
---|
| 1556 | #define VDC51OIR_SCL0_FRC6 VDC51.OIR_SCL0_FRC6
|
---|
| 1557 | #define VDC51OIR_SCL0_FRC7 VDC51.OIR_SCL0_FRC7
|
---|
| 1558 | #define VDC51OIR_SCL0_DS1 VDC51.OIR_SCL0_DS1
|
---|
| 1559 | #define VDC51OIR_SCL0_DS2 VDC51.OIR_SCL0_DS2
|
---|
| 1560 | #define VDC51OIR_SCL0_DS3 VDC51.OIR_SCL0_DS3
|
---|
| 1561 | #define VDC51OIR_SCL0_DS7 VDC51.OIR_SCL0_DS7
|
---|
| 1562 | #define VDC51OIR_SCL0_US1 VDC51.OIR_SCL0_US1
|
---|
| 1563 | #define VDC51OIR_SCL0_US2 VDC51.OIR_SCL0_US2
|
---|
| 1564 | #define VDC51OIR_SCL0_US3 VDC51.OIR_SCL0_US3
|
---|
| 1565 | #define VDC51OIR_SCL0_US8 VDC51.OIR_SCL0_US8
|
---|
| 1566 | #define VDC51OIR_SCL0_OVR1 VDC51.OIR_SCL0_OVR1
|
---|
| 1567 | #define VDC51OIR_SCL1_UPDATE VDC51.OIR_SCL1_UPDATE
|
---|
| 1568 | #define VDC51OIR_SCL1_WR1 VDC51.OIR_SCL1_WR1
|
---|
| 1569 | #define VDC51OIR_SCL1_WR2 VDC51.OIR_SCL1_WR2
|
---|
| 1570 | #define VDC51OIR_SCL1_WR3 VDC51.OIR_SCL1_WR3
|
---|
| 1571 | #define VDC51OIR_SCL1_WR4 VDC51.OIR_SCL1_WR4
|
---|
| 1572 | #define VDC51OIR_SCL1_WR5 VDC51.OIR_SCL1_WR5
|
---|
| 1573 | #define VDC51OIR_SCL1_WR6 VDC51.OIR_SCL1_WR6
|
---|
| 1574 | #define VDC51OIR_SCL1_WR7 VDC51.OIR_SCL1_WR7
|
---|
| 1575 | #define VDC51GR_OIR_UPDATE VDC51.GR_OIR_UPDATE
|
---|
| 1576 | #define VDC51GR_OIR_FLM_RD VDC51.GR_OIR_FLM_RD
|
---|
| 1577 | #define VDC51GR_OIR_FLM1 VDC51.GR_OIR_FLM1
|
---|
| 1578 | #define VDC51GR_OIR_FLM2 VDC51.GR_OIR_FLM2
|
---|
| 1579 | #define VDC51GR_OIR_FLM3 VDC51.GR_OIR_FLM3
|
---|
| 1580 | #define VDC51GR_OIR_FLM4 VDC51.GR_OIR_FLM4
|
---|
| 1581 | #define VDC51GR_OIR_FLM5 VDC51.GR_OIR_FLM5
|
---|
| 1582 | #define VDC51GR_OIR_FLM6 VDC51.GR_OIR_FLM6
|
---|
| 1583 | #define VDC51GR_OIR_AB1 VDC51.GR_OIR_AB1
|
---|
| 1584 | #define VDC51GR_OIR_AB2 VDC51.GR_OIR_AB2
|
---|
| 1585 | #define VDC51GR_OIR_AB3 VDC51.GR_OIR_AB3
|
---|
| 1586 | #define VDC51GR_OIR_AB7 VDC51.GR_OIR_AB7
|
---|
| 1587 | #define VDC51GR_OIR_AB8 VDC51.GR_OIR_AB8
|
---|
| 1588 | #define VDC51GR_OIR_AB9 VDC51.GR_OIR_AB9
|
---|
| 1589 | #define VDC51GR_OIR_AB10 VDC51.GR_OIR_AB10
|
---|
| 1590 | #define VDC51GR_OIR_AB11 VDC51.GR_OIR_AB11
|
---|
| 1591 | #define VDC51GR_OIR_BASE VDC51.GR_OIR_BASE
|
---|
| 1592 | #define VDC51GR_OIR_CLUT VDC51.GR_OIR_CLUT
|
---|
| 1593 | #define VDC51GR_OIR_MON VDC51.GR_OIR_MON
|
---|
| 1594 | /* <-SEC M1.10.1 */
|
---|
| 1595 | /* <-QAC 0639 */
|
---|
| 1596 | #endif
|
---|