source: asp3_tinet_ecnl_arm/trunk/asp3_dcre/mbed/targets/TARGET_RENESAS/TARGET_RZ_A1H/device/inc/iodefines/sdg_iodefine.h@ 352

Last change on this file since 352 was 352, checked in by coas-nagasima, 6 years ago

arm向けASP3版ECNLを追加
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File size: 3.6 KB
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1/*******************************************************************************
2* DISCLAIMER
3* This software is supplied by Renesas Electronics Corporation and is only
4* intended for use with Renesas products. No other uses are authorized. This
5* software is owned by Renesas Electronics Corporation and is protected under
6* all applicable laws, including copyright laws.
7* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
8* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
9* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
10* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
11* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
12* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
13* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
14* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
15* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
16* Renesas reserves the right, without notice, to make changes to this software
17* and to discontinue the availability of this software. By using this software,
18* you agree to the additional terms and conditions found by accessing the
19* following link:
20* http://www.renesas.com/disclaimer*
21* Copyright (C) 2013-2014 Renesas Electronics Corporation. All rights reserved.
22*******************************************************************************/
23/*******************************************************************************
24* File Name : sdg_iodefine.h
25* $Rev: $
26* $Date:: $
27* Description : Definition of I/O Register (V1.00a)
28******************************************************************************/
29#ifndef SDG_IODEFINE_H
30#define SDG_IODEFINE_H
31
32struct st_sdg
33{ /* SDG */
34 volatile uint8_t SGCR1; /* SGCR1 */
35 volatile uint8_t SGCSR; /* SGCSR */
36 volatile uint8_t SGCR2; /* SGCR2 */
37 volatile uint8_t SGLR; /* SGLR */
38 volatile uint8_t SGTFR; /* SGTFR */
39 volatile uint8_t SGSFR; /* SGSFR */
40};
41
42
43#define SDG0 (*(struct st_sdg *)0xFCFF4800uL) /* SDG0 */
44#define SDG1 (*(struct st_sdg *)0xFCFF4A00uL) /* SDG1 */
45#define SDG2 (*(struct st_sdg *)0xFCFF4C00uL) /* SDG2 */
46#define SDG3 (*(struct st_sdg *)0xFCFF4E00uL) /* SDG3 */
47
48
49/* Start of channnel array defines of SDG */
50
51/* Channnel array defines of SDG */
52/*(Sample) value = SDG[ channel ]->SGCR1; */
53#define SDG_COUNT 4
54#define SDG_ADDRESS_LIST \
55{ /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \
56 &SDG0, &SDG1, &SDG2, &SDG3 \
57} /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */
58
59/* End of channnel array defines of SDG */
60
61
62#define SGCR1_0 SDG0.SGCR1
63#define SGCSR_0 SDG0.SGCSR
64#define SGCR2_0 SDG0.SGCR2
65#define SGLR_0 SDG0.SGLR
66#define SGTFR_0 SDG0.SGTFR
67#define SGSFR_0 SDG0.SGSFR
68#define SGCR1_1 SDG1.SGCR1
69#define SGCSR_1 SDG1.SGCSR
70#define SGCR2_1 SDG1.SGCR2
71#define SGLR_1 SDG1.SGLR
72#define SGTFR_1 SDG1.SGTFR
73#define SGSFR_1 SDG1.SGSFR
74#define SGCR1_2 SDG2.SGCR1
75#define SGCSR_2 SDG2.SGCSR
76#define SGCR2_2 SDG2.SGCR2
77#define SGLR_2 SDG2.SGLR
78#define SGTFR_2 SDG2.SGTFR
79#define SGSFR_2 SDG2.SGSFR
80#define SGCR1_3 SDG3.SGCR1
81#define SGCSR_3 SDG3.SGCSR
82#define SGCR2_3 SDG3.SGCR2
83#define SGLR_3 SDG3.SGLR
84#define SGTFR_3 SDG3.SGTFR
85#define SGSFR_3 SDG3.SGSFR
86#endif
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