source: asp3_tinet_ecnl_arm/trunk/asp3_dcre/mbed/targets/TARGET_RENESAS/TARGET_RZ_A1H/device/inc/iodefines/rtc_iodefine.h@ 352

Last change on this file since 352 was 352, checked in by coas-nagasima, 6 years ago

arm向けASP3版ECNLを追加
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  • Property svn:mime-type set to text/x-chdr;charset=UTF-8
File size: 5.8 KB
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1/*******************************************************************************
2* DISCLAIMER
3* This software is supplied by Renesas Electronics Corporation and is only
4* intended for use with Renesas products. No other uses are authorized. This
5* software is owned by Renesas Electronics Corporation and is protected under
6* all applicable laws, including copyright laws.
7* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
8* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
9* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
10* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
11* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
12* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
13* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
14* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
15* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
16* Renesas reserves the right, without notice, to make changes to this software
17* and to discontinue the availability of this software. By using this software,
18* you agree to the additional terms and conditions found by accessing the
19* following link:
20* http://www.renesas.com/disclaimer*
21* Copyright (C) 2013-2014 Renesas Electronics Corporation. All rights reserved.
22*******************************************************************************/
23/*******************************************************************************
24* File Name : rtc_iodefine.h
25* $Rev: $
26* $Date:: $
27* Description : Definition of I/O Register (V1.00a)
28******************************************************************************/
29#ifndef RTC_IODEFINE_H
30#define RTC_IODEFINE_H
31/* ->SEC M1.10.1 : Not magic number */
32
33struct st_rtc
34{ /* RTC */
35 volatile uint8_t R64CNT; /* R64CNT */
36 volatile uint8_t dummy537[1]; /* */
37 volatile uint8_t RSECCNT; /* RSECCNT */
38 volatile uint8_t dummy538[1]; /* */
39 volatile uint8_t RMINCNT; /* RMINCNT */
40 volatile uint8_t dummy539[1]; /* */
41 volatile uint8_t RHRCNT; /* RHRCNT */
42 volatile uint8_t dummy540[1]; /* */
43 volatile uint8_t RWKCNT; /* RWKCNT */
44 volatile uint8_t dummy541[1]; /* */
45 volatile uint8_t RDAYCNT; /* RDAYCNT */
46 volatile uint8_t dummy542[1]; /* */
47 volatile uint8_t RMONCNT; /* RMONCNT */
48 volatile uint8_t dummy543[1]; /* */
49 volatile uint16_t RYRCNT; /* RYRCNT */
50 volatile uint8_t RSECAR; /* RSECAR */
51 volatile uint8_t dummy544[1]; /* */
52 volatile uint8_t RMINAR; /* RMINAR */
53 volatile uint8_t dummy545[1]; /* */
54 volatile uint8_t RHRAR; /* RHRAR */
55 volatile uint8_t dummy546[1]; /* */
56 volatile uint8_t RWKAR; /* RWKAR */
57 volatile uint8_t dummy547[1]; /* */
58 volatile uint8_t RDAYAR; /* RDAYAR */
59 volatile uint8_t dummy548[1]; /* */
60 volatile uint8_t RMONAR; /* RMONAR */
61 volatile uint8_t dummy549[1]; /* */
62 volatile uint8_t RCR1; /* RCR1 */
63 volatile uint8_t dummy550[1]; /* */
64 volatile uint8_t RCR2; /* RCR2 */
65 volatile uint8_t dummy551[1]; /* */
66 volatile uint16_t RYRAR; /* RYRAR */
67 volatile uint8_t dummy552[2]; /* */
68 volatile uint8_t RCR3; /* RCR3 */
69 volatile uint8_t dummy553[1]; /* */
70 volatile uint8_t RCR5; /* RCR5 */
71 volatile uint8_t dummy554[3]; /* */
72 volatile uint16_t RFRH; /* RFRH */
73 volatile uint16_t RFRL; /* RFRL */
74};
75
76
77#define RTC (*(struct st_rtc *)0xFCFF1000uL) /* RTC */
78
79
80#define RTCR64CNT RTC.R64CNT
81#define RTCRSECCNT RTC.RSECCNT
82#define RTCRMINCNT RTC.RMINCNT
83#define RTCRHRCNT RTC.RHRCNT
84#define RTCRWKCNT RTC.RWKCNT
85#define RTCRDAYCNT RTC.RDAYCNT
86#define RTCRMONCNT RTC.RMONCNT
87#define RTCRYRCNT RTC.RYRCNT
88#define RTCRSECAR RTC.RSECAR
89#define RTCRMINAR RTC.RMINAR
90#define RTCRHRAR RTC.RHRAR
91#define RTCRWKAR RTC.RWKAR
92#define RTCRDAYAR RTC.RDAYAR
93#define RTCRMONAR RTC.RMONAR
94#define RTCRCR1 RTC.RCR1
95#define RTCRCR2 RTC.RCR2
96#define RTCRYRAR RTC.RYRAR
97#define RTCRCR3 RTC.RCR3
98#define RTCRCR5 RTC.RCR5
99#define RTCRFRH RTC.RFRH
100#define RTCRFRL RTC.RFRL
101/* <-SEC M1.10.1 */
102#endif
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