source: asp3_tinet_ecnl_arm/trunk/asp3_dcre/mbed/targets/TARGET_RENESAS/TARGET_RZ_A1H/device/inc/iodefines/romdec_iodefine.h@ 352

Last change on this file since 352 was 352, checked in by coas-nagasima, 6 years ago

arm向けASP3版ECNLを追加
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File size: 9.4 KB
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1/*******************************************************************************
2* DISCLAIMER
3* This software is supplied by Renesas Electronics Corporation and is only
4* intended for use with Renesas products. No other uses are authorized. This
5* software is owned by Renesas Electronics Corporation and is protected under
6* all applicable laws, including copyright laws.
7* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
8* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
9* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
10* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
11* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
12* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
13* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
14* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
15* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
16* Renesas reserves the right, without notice, to make changes to this software
17* and to discontinue the availability of this software. By using this software,
18* you agree to the additional terms and conditions found by accessing the
19* following link:
20* http://www.renesas.com/disclaimer*
21* Copyright (C) 2013-2014 Renesas Electronics Corporation. All rights reserved.
22*******************************************************************************/
23/*******************************************************************************
24* File Name : romdec_iodefine.h
25* $Rev: $
26* $Date:: $
27* Description : Definition of I/O Register (V1.00a)
28******************************************************************************/
29#ifndef ROMDEC_IODEFINE_H
30#define ROMDEC_IODEFINE_H
31/* ->SEC M1.10.1 : Not magic number */
32
33struct st_romdec
34{ /* ROMDEC */
35 volatile uint8_t CROMEN; /* CROMEN */
36 volatile uint8_t CROMSY0; /* CROMSY0 */
37#define ROMDEC_CROMCTL0_COUNT 2
38 volatile uint8_t CROMCTL0; /* CROMCTL0 */
39 volatile uint8_t CROMCTL1; /* CROMCTL1 */
40 volatile uint8_t dummy23[1]; /* */
41 volatile uint8_t CROMCTL3; /* CROMCTL3 */
42 volatile uint8_t CROMCTL4; /* CROMCTL4 */
43 volatile uint8_t CROMCTL5; /* CROMCTL5 */
44#define ROMDEC_CROMST0_COUNT 2
45 volatile uint8_t CROMST0; /* CROMST0 */
46 volatile uint8_t CROMST1; /* CROMST1 */
47 volatile uint8_t dummy24[1]; /* */
48 volatile uint8_t CROMST3; /* CROMST3 */
49 volatile uint8_t CROMST4; /* CROMST4 */
50 volatile uint8_t CROMST5; /* CROMST5 */
51 volatile uint8_t CROMST6; /* CROMST6 */
52 volatile uint8_t dummy25[5]; /* */
53#define ROMDEC_CBUFST0_COUNT 3
54 volatile uint8_t CBUFST0; /* CBUFST0 */
55 volatile uint8_t CBUFST1; /* CBUFST1 */
56 volatile uint8_t CBUFST2; /* CBUFST2 */
57 volatile uint8_t dummy26[1]; /* */
58#define ROMDEC_HEAD00_COUNT 4
59 volatile uint8_t HEAD00; /* HEAD00 */
60 volatile uint8_t HEAD01; /* HEAD01 */
61 volatile uint8_t HEAD02; /* HEAD02 */
62 volatile uint8_t HEAD03; /* HEAD03 */
63#define ROMDEC_SHEAD00_COUNT 8
64 volatile uint8_t SHEAD00; /* SHEAD00 */
65 volatile uint8_t SHEAD01; /* SHEAD01 */
66 volatile uint8_t SHEAD02; /* SHEAD02 */
67 volatile uint8_t SHEAD03; /* SHEAD03 */
68 volatile uint8_t SHEAD04; /* SHEAD04 */
69 volatile uint8_t SHEAD05; /* SHEAD05 */
70 volatile uint8_t SHEAD06; /* SHEAD06 */
71 volatile uint8_t SHEAD07; /* SHEAD07 */
72#define ROMDEC_HEAD20_COUNT 4
73 volatile uint8_t HEAD20; /* HEAD20 */
74 volatile uint8_t HEAD21; /* HEAD21 */
75 volatile uint8_t HEAD22; /* HEAD22 */
76 volatile uint8_t HEAD23; /* HEAD23 */
77#define ROMDEC_SHEAD20_COUNT 8
78 volatile uint8_t SHEAD20; /* SHEAD20 */
79 volatile uint8_t SHEAD21; /* SHEAD21 */
80 volatile uint8_t SHEAD22; /* SHEAD22 */
81 volatile uint8_t SHEAD23; /* SHEAD23 */
82 volatile uint8_t SHEAD24; /* SHEAD24 */
83 volatile uint8_t SHEAD25; /* SHEAD25 */
84 volatile uint8_t SHEAD26; /* SHEAD26 */
85 volatile uint8_t SHEAD27; /* SHEAD27 */
86 volatile uint8_t dummy27[16]; /* */
87#define ROMDEC_CBUFCTL0_COUNT 4
88 volatile uint8_t CBUFCTL0; /* CBUFCTL0 */
89 volatile uint8_t CBUFCTL1; /* CBUFCTL1 */
90 volatile uint8_t CBUFCTL2; /* CBUFCTL2 */
91 volatile uint8_t CBUFCTL3; /* CBUFCTL3 */
92 volatile uint8_t dummy28[1]; /* */
93 volatile uint8_t CROMST0M; /* CROMST0M */
94 volatile uint8_t dummy29[186]; /* */
95 volatile uint8_t ROMDECRST; /* ROMDECRST */
96 volatile uint8_t RSTSTAT; /* RSTSTAT */
97 volatile uint8_t SSI; /* SSI */
98 volatile uint8_t dummy30[5]; /* */
99 volatile uint8_t INTHOLD; /* INTHOLD */
100 volatile uint8_t INHINT; /* INHINT */
101 volatile uint8_t dummy31[246]; /* */
102#define ROMDEC_STRMDIN0_COUNT 2
103 volatile uint16_t STRMDIN0; /* STRMDIN0 */
104 volatile uint16_t STRMDIN2; /* STRMDIN2 */
105 volatile uint16_t STRMDOUT0; /* STRMDOUT0 */
106};
107
108
109#define ROMDEC (*(struct st_romdec *)0xE8005000uL) /* ROMDEC */
110
111
112#define ROMDECCROMEN ROMDEC.CROMEN
113#define ROMDECCROMSY0 ROMDEC.CROMSY0
114#define ROMDECCROMCTL0 ROMDEC.CROMCTL0
115#define ROMDECCROMCTL1 ROMDEC.CROMCTL1
116#define ROMDECCROMCTL3 ROMDEC.CROMCTL3
117#define ROMDECCROMCTL4 ROMDEC.CROMCTL4
118#define ROMDECCROMCTL5 ROMDEC.CROMCTL5
119#define ROMDECCROMST0 ROMDEC.CROMST0
120#define ROMDECCROMST1 ROMDEC.CROMST1
121#define ROMDECCROMST3 ROMDEC.CROMST3
122#define ROMDECCROMST4 ROMDEC.CROMST4
123#define ROMDECCROMST5 ROMDEC.CROMST5
124#define ROMDECCROMST6 ROMDEC.CROMST6
125#define ROMDECCBUFST0 ROMDEC.CBUFST0
126#define ROMDECCBUFST1 ROMDEC.CBUFST1
127#define ROMDECCBUFST2 ROMDEC.CBUFST2
128#define ROMDECHEAD00 ROMDEC.HEAD00
129#define ROMDECHEAD01 ROMDEC.HEAD01
130#define ROMDECHEAD02 ROMDEC.HEAD02
131#define ROMDECHEAD03 ROMDEC.HEAD03
132#define ROMDECSHEAD00 ROMDEC.SHEAD00
133#define ROMDECSHEAD01 ROMDEC.SHEAD01
134#define ROMDECSHEAD02 ROMDEC.SHEAD02
135#define ROMDECSHEAD03 ROMDEC.SHEAD03
136#define ROMDECSHEAD04 ROMDEC.SHEAD04
137#define ROMDECSHEAD05 ROMDEC.SHEAD05
138#define ROMDECSHEAD06 ROMDEC.SHEAD06
139#define ROMDECSHEAD07 ROMDEC.SHEAD07
140#define ROMDECHEAD20 ROMDEC.HEAD20
141#define ROMDECHEAD21 ROMDEC.HEAD21
142#define ROMDECHEAD22 ROMDEC.HEAD22
143#define ROMDECHEAD23 ROMDEC.HEAD23
144#define ROMDECSHEAD20 ROMDEC.SHEAD20
145#define ROMDECSHEAD21 ROMDEC.SHEAD21
146#define ROMDECSHEAD22 ROMDEC.SHEAD22
147#define ROMDECSHEAD23 ROMDEC.SHEAD23
148#define ROMDECSHEAD24 ROMDEC.SHEAD24
149#define ROMDECSHEAD25 ROMDEC.SHEAD25
150#define ROMDECSHEAD26 ROMDEC.SHEAD26
151#define ROMDECSHEAD27 ROMDEC.SHEAD27
152#define ROMDECCBUFCTL0 ROMDEC.CBUFCTL0
153#define ROMDECCBUFCTL1 ROMDEC.CBUFCTL1
154#define ROMDECCBUFCTL2 ROMDEC.CBUFCTL2
155#define ROMDECCBUFCTL3 ROMDEC.CBUFCTL3
156#define ROMDECCROMST0M ROMDEC.CROMST0M
157#define ROMDECROMDECRST ROMDEC.ROMDECRST
158#define ROMDECRSTSTAT ROMDEC.RSTSTAT
159#define ROMDECSSI ROMDEC.SSI
160#define ROMDECINTHOLD ROMDEC.INTHOLD
161#define ROMDECINHINT ROMDEC.INHINT
162#define ROMDECSTRMDIN0 ROMDEC.STRMDIN0
163#define ROMDECSTRMDIN2 ROMDEC.STRMDIN2
164#define ROMDECSTRMDOUT0 ROMDEC.STRMDOUT0
165/* <-SEC M1.10.1 */
166#endif
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