source: asp3_tinet_ecnl_arm/trunk/asp3_dcre/mbed/targets/TARGET_RENESAS/TARGET_RZ_A1H/device/inc/iodefines/pwm_iodefine.h@ 352

Last change on this file since 352 was 352, checked in by coas-nagasima, 6 years ago

arm向けASP3版ECNLを追加
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File size: 6.1 KB
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1/*******************************************************************************
2* DISCLAIMER
3* This software is supplied by Renesas Electronics Corporation and is only
4* intended for use with Renesas products. No other uses are authorized. This
5* software is owned by Renesas Electronics Corporation and is protected under
6* all applicable laws, including copyright laws.
7* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
8* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
9* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
10* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
11* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
12* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
13* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
14* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
15* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
16* Renesas reserves the right, without notice, to make changes to this software
17* and to discontinue the availability of this software. By using this software,
18* you agree to the additional terms and conditions found by accessing the
19* following link:
20* http://www.renesas.com/disclaimer*
21* Copyright (C) 2013-2014 Renesas Electronics Corporation. All rights reserved.
22*******************************************************************************/
23/*******************************************************************************
24* File Name : pwm_iodefine.h
25* $Rev: $
26* $Date:: $
27* Description : Definition of I/O Register (V1.00a)
28******************************************************************************/
29#ifndef PWM_IODEFINE_H
30#define PWM_IODEFINE_H
31/* ->MISRA 18.4 : Pack unpack union */ /* ->SEC M1.6.2 */
32/* ->SEC M1.10.1 : Not magic number */
33
34union reg16_8_t
35{
36 volatile uint16_t UINT16; /* 16-bit Access */
37 volatile uint8_t UINT8[2]; /* 8-bit Access */
38};
39
40struct st_pwm
41{ /* PWM */
42 volatile uint8_t dummy559[2]; /* */
43 union reg16_8_t PWBTCR; /* PWBTCR */
44
45 volatile uint8_t dummy560[216]; /* */
46
47/* start of struct st_pwm_common */
48 union reg16_8_t PWCR_1; /* PWCR_1 */
49
50 volatile uint8_t dummy561[2]; /* */
51 union reg16_8_t PWPR_1; /* PWPR_1 */
52
53 volatile uint16_t PWCYR_1; /* PWCYR_1 */
54 volatile uint16_t PWBFR_1A; /* PWBFR_1A */
55 volatile uint16_t PWBFR_1C; /* PWBFR_1C */
56 volatile uint16_t PWBFR_1E; /* PWBFR_1E */
57 volatile uint16_t PWBFR_1G; /* PWBFR_1G */
58/* end of struct st_pwm_common */
59
60/* start of struct st_pwm_common */
61 union reg16_8_t PWCR_2; /* PWCR_2 */
62
63 volatile uint8_t dummy562[2]; /* */
64 union reg16_8_t PWPR_2; /* PWPR_2 */
65
66 volatile uint16_t PWCYR_2; /* PWCYR_2 */
67 volatile uint16_t PWBFR_2A; /* PWBFR_2A */
68 volatile uint16_t PWBFR_2C; /* PWBFR_2C */
69 volatile uint16_t PWBFR_2E; /* PWBFR_2E */
70 volatile uint16_t PWBFR_2G; /* PWBFR_2G */
71/* end of struct st_pwm_common */
72};
73
74
75struct st_pwm_common
76{
77 union reg16_8_t PWCR_1; /* PWCR_1 */
78
79 volatile uint8_t dummy572[2]; /* */
80 union reg16_8_t PWPR_1; /* PWPR_1 */
81
82 volatile uint16_t PWCYR_1; /* PWCYR_1 */
83 volatile uint16_t PWBFR_1A; /* PWBFR_1A */
84 volatile uint16_t PWBFR_1C; /* PWBFR_1C */
85 volatile uint16_t PWBFR_1E; /* PWBFR_1E */
86 volatile uint16_t PWBFR_1G; /* PWBFR_1G */
87};
88
89
90#define PWM (*(struct st_pwm *)0xFCFF5004uL) /* PWM */
91
92
93/* Start of channnel array defines of PWM */
94
95/* Channnel array defines of PWMn */
96/*(Sample) value = PWMn[ channel ]->PWCR_1.UINT16; */
97#define PWMn_COUNT 2
98#define PWMn_ADDRESS_LIST \
99{ /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \
100 &PWM1, &PWM2 \
101} /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */
102#define PWM1 (*(struct st_pwm_common *)&PWM.PWCR_1) /* PWM1 */
103#define PWM2 (*(struct st_pwm_common *)&PWM.PWCR_2) /* PWM2 */
104
105/* End of channnel array defines of PWM */
106
107
108#define PWMPWBTCR PWM.PWBTCR.UINT16
109#define PWMPWBTCR_BYTE_L PWM.PWBTCR.UINT8[0]
110#define PWMPWBTCR_BYTE_H PWM.PWBTCR.UINT8[1]
111#define PWMPWCR_1 PWM.PWCR_1.UINT16
112#define PWMPWCR_1_BYTE_L PWM.PWCR_1.UINT8[0]
113#define PWMPWCR_1_BYTE_H PWM.PWCR_1.UINT8[1]
114#define PWMPWPR_1 PWM.PWPR_1.UINT16
115#define PWMPWPR_1_BYTE_L PWM.PWPR_1.UINT8[0]
116#define PWMPWPR_1_BYTE_H PWM.PWPR_1.UINT8[1]
117#define PWMPWCYR_1 PWM.PWCYR_1
118#define PWMPWBFR_1A PWM.PWBFR_1A
119#define PWMPWBFR_1C PWM.PWBFR_1C
120#define PWMPWBFR_1E PWM.PWBFR_1E
121#define PWMPWBFR_1G PWM.PWBFR_1G
122#define PWMPWCR_2 PWM.PWCR_2.UINT16
123#define PWMPWCR_2_BYTE_L PWM.PWCR_2.UINT8[0]
124#define PWMPWCR_2_BYTE_H PWM.PWCR_2.UINT8[1]
125#define PWMPWPR_2 PWM.PWPR_2.UINT16
126#define PWMPWPR_2_BYTE_L PWM.PWPR_2.UINT8[0]
127#define PWMPWPR_2_BYTE_H PWM.PWPR_2.UINT8[1]
128#define PWMPWCYR_2 PWM.PWCYR_2
129#define PWMPWBFR_2A PWM.PWBFR_2A
130#define PWMPWBFR_2C PWM.PWBFR_2C
131#define PWMPWBFR_2E PWM.PWBFR_2E
132#define PWMPWBFR_2G PWM.PWBFR_2G
133/* <-SEC M1.10.1 */
134/* <-MISRA 18.4 */ /* <-SEC M1.6.2 */
135#endif
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