source: asp3_tinet_ecnl_arm/trunk/asp3_dcre/mbed/targets/TARGET_RENESAS/TARGET_RZ_A1H/device/inc/iobitmasks/scif_iobitmask.h@ 352

Last change on this file since 352 was 352, checked in by coas-nagasima, 6 years ago

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1/*******************************************************************************
2* DISCLAIMER
3* This software is supplied by Renesas Electronics Corporation and is only
4* intended for use with Renesas products. No other uses are authorized. This
5* software is owned by Renesas Electronics Corporation and is protected under
6* all applicable laws, including copyright laws.
7* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
8* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
9* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
10* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
11* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
12* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
13* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
14* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
15* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
16* Renesas reserves the right, without notice, to make changes to this software
17* and to discontinue the availability of this software. By using this software,
18* you agree to the additional terms and conditions found by accessing the
19* following link:
20* http://www.renesas.com/disclaimer
21* Copyright (C) 2012 - 2014 Renesas Electronics Corporation. All rights reserved.
22*******************************************************************************/
23/*******************************************************************************
24* File Name : scif_iobitmask.h
25* $Rev: 1115 $
26* $Date:: 2014-07-09 15:35:02 +0900#$
27* Description : SCIF register define header
28*******************************************************************************/
29#ifndef SCIF_IOBITMASK_H
30#define SCIF_IOBITMASK_H
31
32
33/* ==== Mask values for IO registers ==== */
34/* ---- SCIF0 ---- */
35#define SCIF0_SCSMR_CKS (0x0003u)
36#define SCIF0_SCSMR_STOP (0x0008u)
37#define SCIF0_SCSMR_OE (0x0010u)
38#define SCIF0_SCSMR_PE (0x0020u)
39#define SCIF0_SCSMR_CHR (0x0040u)
40#define SCIF0_SCSMR_CA (0x0080u)
41
42#define SCIF0_SCBRR_D (0xFFu)
43
44#define SCIF0_SCSCR_CKE (0x0003u)
45#define SCIF0_SCSCR_REIE (0x0008u)
46#define SCIF0_SCSCR_RE (0x0010u)
47#define SCIF0_SCSCR_TE (0x0020u)
48#define SCIF0_SCSCR_RIE (0x0040u)
49#define SCIF0_SCSCR_TIE (0x0080u)
50
51#define SCIF0_SCFTDR_D (0xFFu)
52
53#define SCIF0_SCFSR_DR (0x0001u)
54#define SCIF0_SCFSR_RDF (0x0002u)
55#define SCIF0_SCFSR_PER (0x0004u)
56#define SCIF0_SCFSR_FER (0x0008u)
57#define SCIF0_SCFSR_BRK (0x0010u)
58#define SCIF0_SCFSR_TDFE (0x0020u)
59#define SCIF0_SCFSR_TEND (0x0040u)
60#define SCIF0_SCFSR_ER (0x0080u)
61#define SCIF0_SCFSR_FERN (0x0F00u)
62#define SCIF0_SCFSR_PERN (0xF000u)
63
64#define SCIF0_SCFRDR_D (0xFFu)
65
66#define SCIF0_SCFCR_LOOP (0x0001u)
67#define SCIF0_SCFCR_RFRST (0x0002u)
68#define SCIF0_SCFCR_TFRST (0x0004u)
69#define SCIF0_SCFCR_MCE (0x0008u)
70#define SCIF0_SCFCR_TTRG (0x0030u)
71#define SCIF0_SCFCR_RTRG (0x00C0u)
72#define SCIF0_SCFCR_RSTRG (0x0700u)
73
74#define SCIF0_SCFDR_R (0x001Fu)
75#define SCIF0_SCFDR_T (0x1F00u)
76
77#define SCIF0_SCSPTR_SPB2DT (0x0001u)
78#define SCIF0_SCSPTR_SPB2IO (0x0002u)
79#define SCIF0_SCSPTR_SCKDT (0x0004u)
80#define SCIF0_SCSPTR_SCKIO (0x0008u)
81#define SCIF0_SCSPTR_CTSDT (0x0010u)
82#define SCIF0_SCSPTR_CTSIO (0x0020u)
83#define SCIF0_SCSPTR_RTSDT (0x0040u)
84#define SCIF0_SCSPTR_RTSIO (0x0080u)
85
86#define SCIF0_SCLSR_ORER (0x0001u)
87
88#define SCIF0_SCEMR_ABCS (0x0001u)
89#define SCIF0_SCEMR_BGDM (0x0080u)
90
91/* ---- SCIF1 ---- */
92#define SCIF1_SCSMR_CKS (0x0003u)
93#define SCIF1_SCSMR_STOP (0x0008u)
94#define SCIF1_SCSMR_OE (0x0010u)
95#define SCIF1_SCSMR_PE (0x0020u)
96#define SCIF1_SCSMR_CHR (0x0040u)
97#define SCIF1_SCSMR_CA (0x0080u)
98
99#define SCIF1_SCBRR_D (0xFFu)
100
101#define SCIF1_SCSCR_CKE (0x0003u)
102#define SCIF1_SCSCR_REIE (0x0008u)
103#define SCIF1_SCSCR_RE (0x0010u)
104#define SCIF1_SCSCR_TE (0x0020u)
105#define SCIF1_SCSCR_RIE (0x0040u)
106#define SCIF1_SCSCR_TIE (0x0080u)
107
108#define SCIF1_SCFTDR_D (0xFFu)
109
110#define SCIF1_SCFSR_DR (0x0001u)
111#define SCIF1_SCFSR_RDF (0x0002u)
112#define SCIF1_SCFSR_PER (0x0004u)
113#define SCIF1_SCFSR_FER (0x0008u)
114#define SCIF1_SCFSR_BRK (0x0010u)
115#define SCIF1_SCFSR_TDFE (0x0020u)
116#define SCIF1_SCFSR_TEND (0x0040u)
117#define SCIF1_SCFSR_ER (0x0080u)
118#define SCIF1_SCFSR_FERN (0x0F00u)
119#define SCIF1_SCFSR_PERN (0xF000u)
120
121#define SCIF1_SCFRDR_D (0xFFu)
122
123#define SCIF1_SCFCR_LOOP (0x0001u)
124#define SCIF1_SCFCR_RFRST (0x0002u)
125#define SCIF1_SCFCR_TFRST (0x0004u)
126#define SCIF1_SCFCR_MCE (0x0008u)
127#define SCIF1_SCFCR_TTRG (0x0030u)
128#define SCIF1_SCFCR_RTRG (0x00C0u)
129#define SCIF1_SCFCR_RSTRG (0x0700u)
130
131#define SCIF1_SCFDR_R (0x001Fu)
132#define SCIF1_SCFDR_T (0x1F00u)
133
134#define SCIF1_SCSPTR_SPB2DT (0x0001u)
135#define SCIF1_SCSPTR_SPB2IO (0x0002u)
136#define SCIF1_SCSPTR_SCKDT (0x0004u)
137#define SCIF1_SCSPTR_SCKIO (0x0008u)
138#define SCIF1_SCSPTR_CTSDT (0x0010u)
139#define SCIF1_SCSPTR_CTSIO (0x0020u)
140#define SCIF1_SCSPTR_RTSDT (0x0040u)
141#define SCIF1_SCSPTR_RTSIO (0x0080u)
142
143#define SCIF1_SCLSR_ORER (0x0001u)
144
145#define SCIF1_SCEMR_ABCS (0x0001u)
146#define SCIF1_SCEMR_BGDM (0x0080u)
147
148/* ---- SCIF2 ---- */
149#define SCIF2_SCSMR_CKS (0x0003u)
150#define SCIF2_SCSMR_STOP (0x0008u)
151#define SCIF2_SCSMR_OE (0x0010u)
152#define SCIF2_SCSMR_PE (0x0020u)
153#define SCIF2_SCSMR_CHR (0x0040u)
154#define SCIF2_SCSMR_CA (0x0080u)
155
156#define SCIF2_SCBRR_D (0xFFu)
157
158#define SCIF2_SCSCR_CKE (0x0003u)
159#define SCIF2_SCSCR_REIE (0x0008u)
160#define SCIF2_SCSCR_RE (0x0010u)
161#define SCIF2_SCSCR_TE (0x0020u)
162#define SCIF2_SCSCR_RIE (0x0040u)
163#define SCIF2_SCSCR_TIE (0x0080u)
164
165#define SCIF2_SCFTDR_D (0xFFu)
166
167#define SCIF2_SCFSR_DR (0x0001u)
168#define SCIF2_SCFSR_RDF (0x0002u)
169#define SCIF2_SCFSR_PER (0x0004u)
170#define SCIF2_SCFSR_FER (0x0008u)
171#define SCIF2_SCFSR_BRK (0x0010u)
172#define SCIF2_SCFSR_TDFE (0x0020u)
173#define SCIF2_SCFSR_TEND (0x0040u)
174#define SCIF2_SCFSR_ER (0x0080u)
175#define SCIF2_SCFSR_FERN (0x0F00u)
176#define SCIF2_SCFSR_PERN (0xF000u)
177
178#define SCIF2_SCFRDR_D (0xFFu)
179
180#define SCIF2_SCFCR_LOOP (0x0001u)
181#define SCIF2_SCFCR_RFRST (0x0002u)
182#define SCIF2_SCFCR_TFRST (0x0004u)
183#define SCIF2_SCFCR_MCE (0x0008u)
184#define SCIF2_SCFCR_TTRG (0x0030u)
185#define SCIF2_SCFCR_RTRG (0x00C0u)
186#define SCIF2_SCFCR_RSTRG (0x0700u)
187
188#define SCIF2_SCFDR_R (0x001Fu)
189#define SCIF2_SCFDR_T (0x1F00u)
190
191#define SCIF2_SCSPTR_SPB2DT (0x0001u)
192#define SCIF2_SCSPTR_SPB2IO (0x0002u)
193#define SCIF2_SCSPTR_SCKDT (0x0004u)
194#define SCIF2_SCSPTR_SCKIO (0x0008u)
195#define SCIF2_SCSPTR_CTSDT (0x0010u)
196#define SCIF2_SCSPTR_CTSIO (0x0020u)
197#define SCIF2_SCSPTR_RTSDT (0x0040u)
198#define SCIF2_SCSPTR_RTSIO (0x0080u)
199
200#define SCIF2_SCLSR_ORER (0x0001u)
201
202#define SCIF2_SCEMR_ABCS (0x0001u)
203#define SCIF2_SCEMR_BGDM (0x0080u)
204
205/* ---- SCIF3 ---- */
206#define SCIF3_SCSMR_CKS (0x0003u)
207#define SCIF3_SCSMR_STOP (0x0008u)
208#define SCIF3_SCSMR_OE (0x0010u)
209#define SCIF3_SCSMR_PE (0x0020u)
210#define SCIF3_SCSMR_CHR (0x0040u)
211#define SCIF3_SCSMR_CA (0x0080u)
212
213#define SCIF3_SCBRR_D (0xFFu)
214
215#define SCIF3_SCSCR_CKE (0x0003u)
216#define SCIF3_SCSCR_REIE (0x0008u)
217#define SCIF3_SCSCR_RE (0x0010u)
218#define SCIF3_SCSCR_TE (0x0020u)
219#define SCIF3_SCSCR_RIE (0x0040u)
220#define SCIF3_SCSCR_TIE (0x0080u)
221
222#define SCIF3_SCFTDR_D (0xFFu)
223
224#define SCIF3_SCFSR_DR (0x0001u)
225#define SCIF3_SCFSR_RDF (0x0002u)
226#define SCIF3_SCFSR_PER (0x0004u)
227#define SCIF3_SCFSR_FER (0x0008u)
228#define SCIF3_SCFSR_BRK (0x0010u)
229#define SCIF3_SCFSR_TDFE (0x0020u)
230#define SCIF3_SCFSR_TEND (0x0040u)
231#define SCIF3_SCFSR_ER (0x0080u)
232#define SCIF3_SCFSR_FERN (0x0F00u)
233#define SCIF3_SCFSR_PERN (0xF000u)
234
235#define SCIF3_SCFRDR_D (0xFFu)
236
237#define SCIF3_SCFCR_LOOP (0x0001u)
238#define SCIF3_SCFCR_RFRST (0x0002u)
239#define SCIF3_SCFCR_TFRST (0x0004u)
240#define SCIF3_SCFCR_MCE (0x0008u)
241#define SCIF3_SCFCR_TTRG (0x0030u)
242#define SCIF3_SCFCR_RTRG (0x00C0u)
243#define SCIF3_SCFCR_RSTRG (0x0700u)
244
245#define SCIF3_SCFDR_R (0x001Fu)
246#define SCIF3_SCFDR_T (0x1F00u)
247
248#define SCIF3_SCSPTR_SPB2DT (0x0001u)
249#define SCIF3_SCSPTR_SPB2IO (0x0002u)
250#define SCIF3_SCSPTR_SCKDT (0x0004u)
251#define SCIF3_SCSPTR_SCKIO (0x0008u)
252#define SCIF3_SCSPTR_CTSDT (0x0010u)
253#define SCIF3_SCSPTR_CTSIO (0x0020u)
254#define SCIF3_SCSPTR_RTSDT (0x0040u)
255#define SCIF3_SCSPTR_RTSIO (0x0080u)
256
257#define SCIF3_SCLSR_ORER (0x0001u)
258
259#define SCIF3_SCEMR_ABCS (0x0001u)
260#define SCIF3_SCEMR_BGDM (0x0080u)
261
262/* ---- SCIF4 ---- */
263#define SCIF4_SCSMR_CKS (0x0003u)
264#define SCIF4_SCSMR_STOP (0x0008u)
265#define SCIF4_SCSMR_OE (0x0010u)
266#define SCIF4_SCSMR_PE (0x0020u)
267#define SCIF4_SCSMR_CHR (0x0040u)
268#define SCIF4_SCSMR_CA (0x0080u)
269
270#define SCIF4_SCBRR_D (0xFFu)
271
272#define SCIF4_SCSCR_CKE (0x0003u)
273#define SCIF4_SCSCR_REIE (0x0008u)
274#define SCIF4_SCSCR_RE (0x0010u)
275#define SCIF4_SCSCR_TE (0x0020u)
276#define SCIF4_SCSCR_RIE (0x0040u)
277#define SCIF4_SCSCR_TIE (0x0080u)
278
279#define SCIF4_SCFTDR_D (0xFFu)
280
281#define SCIF4_SCFSR_DR (0x0001u)
282#define SCIF4_SCFSR_RDF (0x0002u)
283#define SCIF4_SCFSR_PER (0x0004u)
284#define SCIF4_SCFSR_FER (0x0008u)
285#define SCIF4_SCFSR_BRK (0x0010u)
286#define SCIF4_SCFSR_TDFE (0x0020u)
287#define SCIF4_SCFSR_TEND (0x0040u)
288#define SCIF4_SCFSR_ER (0x0080u)
289#define SCIF4_SCFSR_FERN (0x0F00u)
290#define SCIF4_SCFSR_PERN (0xF000u)
291
292#define SCIF4_SCFRDR_D (0xFFu)
293
294#define SCIF4_SCFCR_LOOP (0x0001u)
295#define SCIF4_SCFCR_RFRST (0x0002u)
296#define SCIF4_SCFCR_TFRST (0x0004u)
297#define SCIF4_SCFCR_MCE (0x0008u)
298#define SCIF4_SCFCR_TTRG (0x0030u)
299#define SCIF4_SCFCR_RTRG (0x00C0u)
300#define SCIF4_SCFCR_RSTRG (0x0700u)
301
302#define SCIF4_SCFDR_R (0x001Fu)
303#define SCIF4_SCFDR_T (0x1F00u)
304
305#define SCIF4_SCSPTR_SPB2DT (0x0001u)
306#define SCIF4_SCSPTR_SPB2IO (0x0002u)
307#define SCIF4_SCSPTR_SCKDT (0x0004u)
308#define SCIF4_SCSPTR_SCKIO (0x0008u)
309#define SCIF4_SCSPTR_CTSDT (0x0010u)
310#define SCIF4_SCSPTR_CTSIO (0x0020u)
311#define SCIF4_SCSPTR_RTSDT (0x0040u)
312#define SCIF4_SCSPTR_RTSIO (0x0080u)
313
314#define SCIF4_SCLSR_ORER (0x0001u)
315
316#define SCIF4_SCEMR_ABCS (0x0001u)
317#define SCIF4_SCEMR_BGDM (0x0080u)
318
319/* ---- SCIF5 ---- */
320#define SCIF5_SCSMR_CKS (0x0003u)
321#define SCIF5_SCSMR_STOP (0x0008u)
322#define SCIF5_SCSMR_OE (0x0010u)
323#define SCIF5_SCSMR_PE (0x0020u)
324#define SCIF5_SCSMR_CHR (0x0040u)
325#define SCIF5_SCSMR_CA (0x0080u)
326
327#define SCIF5_SCBRR_D (0xFFu)
328
329#define SCIF5_SCSCR_CKE (0x0003u)
330#define SCIF5_SCSCR_REIE (0x0008u)
331#define SCIF5_SCSCR_RE (0x0010u)
332#define SCIF5_SCSCR_TE (0x0020u)
333#define SCIF5_SCSCR_RIE (0x0040u)
334#define SCIF5_SCSCR_TIE (0x0080u)
335
336#define SCIF5_SCFTDR_D (0xFFu)
337
338#define SCIF5_SCFSR_DR (0x0001u)
339#define SCIF5_SCFSR_RDF (0x0002u)
340#define SCIF5_SCFSR_PER (0x0004u)
341#define SCIF5_SCFSR_FER (0x0008u)
342#define SCIF5_SCFSR_BRK (0x0010u)
343#define SCIF5_SCFSR_TDFE (0x0020u)
344#define SCIF5_SCFSR_TEND (0x0040u)
345#define SCIF5_SCFSR_ER (0x0080u)
346#define SCIF5_SCFSR_FERN (0x0F00u)
347#define SCIF5_SCFSR_PERN (0xF000u)
348
349#define SCIF5_SCFRDR_D (0xFFu)
350
351#define SCIF5_SCFCR_LOOP (0x0001u)
352#define SCIF5_SCFCR_RFRST (0x0002u)
353#define SCIF5_SCFCR_TFRST (0x0004u)
354#define SCIF5_SCFCR_MCE (0x0008u)
355#define SCIF5_SCFCR_TTRG (0x0030u)
356#define SCIF5_SCFCR_RTRG (0x00C0u)
357#define SCIF5_SCFCR_RSTRG (0x0700u)
358
359#define SCIF5_SCFDR_R (0x001Fu)
360#define SCIF5_SCFDR_T (0x1F00u)
361
362#define SCIF5_SCSPTR_SPB2DT (0x0001u)
363#define SCIF5_SCSPTR_SPB2IO (0x0002u)
364#define SCIF5_SCSPTR_SCKDT (0x0004u)
365#define SCIF5_SCSPTR_SCKIO (0x0008u)
366#define SCIF5_SCSPTR_CTSDT (0x0010u)
367#define SCIF5_SCSPTR_CTSIO (0x0020u)
368#define SCIF5_SCSPTR_RTSDT (0x0040u)
369#define SCIF5_SCSPTR_RTSIO (0x0080u)
370
371#define SCIF5_SCLSR_ORER (0x0001u)
372
373#define SCIF5_SCEMR_ABCS (0x0001u)
374#define SCIF5_SCEMR_BGDM (0x0080u)
375
376/* ---- SCIF6 ---- */
377#define SCIF6_SCSMR_CKS (0x0003u)
378#define SCIF6_SCSMR_STOP (0x0008u)
379#define SCIF6_SCSMR_OE (0x0010u)
380#define SCIF6_SCSMR_PE (0x0020u)
381#define SCIF6_SCSMR_CHR (0x0040u)
382#define SCIF6_SCSMR_CA (0x0080u)
383
384#define SCIF6_SCBRR_D (0xFFu)
385
386#define SCIF6_SCSCR_CKE (0x0003u)
387#define SCIF6_SCSCR_REIE (0x0008u)
388#define SCIF6_SCSCR_RE (0x0010u)
389#define SCIF6_SCSCR_TE (0x0020u)
390#define SCIF6_SCSCR_RIE (0x0040u)
391#define SCIF6_SCSCR_TIE (0x0080u)
392
393#define SCIF6_SCFTDR_D (0xFFu)
394
395#define SCIF6_SCFSR_DR (0x0001u)
396#define SCIF6_SCFSR_RDF (0x0002u)
397#define SCIF6_SCFSR_PER (0x0004u)
398#define SCIF6_SCFSR_FER (0x0008u)
399#define SCIF6_SCFSR_BRK (0x0010u)
400#define SCIF6_SCFSR_TDFE (0x0020u)
401#define SCIF6_SCFSR_TEND (0x0040u)
402#define SCIF6_SCFSR_ER (0x0080u)
403#define SCIF6_SCFSR_FERN (0x0F00u)
404#define SCIF6_SCFSR_PERN (0xF000u)
405
406#define SCIF6_SCFRDR_D (0xFFu)
407
408#define SCIF6_SCFCR_LOOP (0x0001u)
409#define SCIF6_SCFCR_RFRST (0x0002u)
410#define SCIF6_SCFCR_TFRST (0x0004u)
411#define SCIF6_SCFCR_MCE (0x0008u)
412#define SCIF6_SCFCR_TTRG (0x0030u)
413#define SCIF6_SCFCR_RTRG (0x00C0u)
414#define SCIF6_SCFCR_RSTRG (0x0700u)
415
416#define SCIF6_SCFDR_R (0x001Fu)
417#define SCIF6_SCFDR_T (0x1F00u)
418
419#define SCIF6_SCSPTR_SPB2DT (0x0001u)
420#define SCIF6_SCSPTR_SPB2IO (0x0002u)
421#define SCIF6_SCSPTR_SCKDT (0x0004u)
422#define SCIF6_SCSPTR_SCKIO (0x0008u)
423#define SCIF6_SCSPTR_CTSDT (0x0010u)
424#define SCIF6_SCSPTR_CTSIO (0x0020u)
425#define SCIF6_SCSPTR_RTSDT (0x0040u)
426#define SCIF6_SCSPTR_RTSIO (0x0080u)
427
428#define SCIF6_SCLSR_ORER (0x0001u)
429
430#define SCIF6_SCEMR_ABCS (0x0001u)
431#define SCIF6_SCEMR_BGDM (0x0080u)
432
433/* ---- SCIF7 ---- */
434#define SCIF7_SCSMR_CKS (0x0003u)
435#define SCIF7_SCSMR_STOP (0x0008u)
436#define SCIF7_SCSMR_OE (0x0010u)
437#define SCIF7_SCSMR_PE (0x0020u)
438#define SCIF7_SCSMR_CHR (0x0040u)
439#define SCIF7_SCSMR_CA (0x0080u)
440
441#define SCIF7_SCBRR_D (0xFFu)
442
443#define SCIF7_SCSCR_CKE (0x0003u)
444#define SCIF7_SCSCR_REIE (0x0008u)
445#define SCIF7_SCSCR_RE (0x0010u)
446#define SCIF7_SCSCR_TE (0x0020u)
447#define SCIF7_SCSCR_RIE (0x0040u)
448#define SCIF7_SCSCR_TIE (0x0080u)
449
450#define SCIF7_SCFTDR_D (0xFFu)
451
452#define SCIF7_SCFSR_DR (0x0001u)
453#define SCIF7_SCFSR_RDF (0x0002u)
454#define SCIF7_SCFSR_PER (0x0004u)
455#define SCIF7_SCFSR_FER (0x0008u)
456#define SCIF7_SCFSR_BRK (0x0010u)
457#define SCIF7_SCFSR_TDFE (0x0020u)
458#define SCIF7_SCFSR_TEND (0x0040u)
459#define SCIF7_SCFSR_ER (0x0080u)
460#define SCIF7_SCFSR_FERN (0x0F00u)
461#define SCIF7_SCFSR_PERN (0xF000u)
462
463#define SCIF7_SCFRDR_D (0xFFu)
464
465#define SCIF7_SCFCR_LOOP (0x0001u)
466#define SCIF7_SCFCR_RFRST (0x0002u)
467#define SCIF7_SCFCR_TFRST (0x0004u)
468#define SCIF7_SCFCR_MCE (0x0008u)
469#define SCIF7_SCFCR_TTRG (0x0030u)
470#define SCIF7_SCFCR_RTRG (0x00C0u)
471#define SCIF7_SCFCR_RSTRG (0x0700u)
472
473#define SCIF7_SCFDR_R (0x001Fu)
474#define SCIF7_SCFDR_T (0x1F00u)
475
476#define SCIF7_SCSPTR_SPB2DT (0x0001u)
477#define SCIF7_SCSPTR_SPB2IO (0x0002u)
478#define SCIF7_SCSPTR_SCKDT (0x0004u)
479#define SCIF7_SCSPTR_SCKIO (0x0008u)
480#define SCIF7_SCSPTR_CTSDT (0x0010u)
481#define SCIF7_SCSPTR_CTSIO (0x0020u)
482#define SCIF7_SCSPTR_RTSDT (0x0040u)
483#define SCIF7_SCSPTR_RTSIO (0x0080u)
484
485#define SCIF7_SCLSR_ORER (0x0001u)
486
487#define SCIF7_SCEMR_ABCS (0x0001u)
488#define SCIF7_SCEMR_BGDM (0x0080u)
489
490/* ---- SCIFn ---- */
491#define SCIFn_SCSMR_CKS (0x0003u)
492#define SCIFn_SCSMR_STOP (0x0008u)
493#define SCIFn_SCSMR_OE (0x0010u)
494#define SCIFn_SCSMR_PE (0x0020u)
495#define SCIFn_SCSMR_CHR (0x0040u)
496#define SCIFn_SCSMR_CA (0x0080u)
497
498#define SCIFn_SCBRR_D (0xFFu)
499
500#define SCIFn_SCSCR_CKE (0x0003u)
501#define SCIFn_SCSCR_REIE (0x0008u)
502#define SCIFn_SCSCR_RE (0x0010u)
503#define SCIFn_SCSCR_TE (0x0020u)
504#define SCIFn_SCSCR_RIE (0x0040u)
505#define SCIFn_SCSCR_TIE (0x0080u)
506
507#define SCIFn_SCFTDR_D (0xFFu)
508
509#define SCIFn_SCFSR_DR (0x0001u)
510#define SCIFn_SCFSR_RDF (0x0002u)
511#define SCIFn_SCFSR_PER (0x0004u)
512#define SCIFn_SCFSR_FER (0x0008u)
513#define SCIFn_SCFSR_BRK (0x0010u)
514#define SCIFn_SCFSR_TDFE (0x0020u)
515#define SCIFn_SCFSR_TEND (0x0040u)
516#define SCIFn_SCFSR_ER (0x0080u)
517#define SCIFn_SCFSR_FERN (0x0F00u)
518#define SCIFn_SCFSR_PERN (0xF000u)
519
520#define SCIFn_SCFRDR_D (0xFFu)
521
522#define SCIFn_SCFCR_LOOP (0x0001u)
523#define SCIFn_SCFCR_RFRST (0x0002u)
524#define SCIFn_SCFCR_TFRST (0x0004u)
525#define SCIFn_SCFCR_MCE (0x0008u)
526#define SCIFn_SCFCR_TTRG (0x0030u)
527#define SCIFn_SCFCR_RTRG (0x00C0u)
528#define SCIFn_SCFCR_RSTRG (0x0700u)
529
530#define SCIFn_SCFDR_R (0x001Fu)
531#define SCIFn_SCFDR_T (0x1F00u)
532
533#define SCIFn_SCSPTR_SPB2DT (0x0001u)
534#define SCIFn_SCSPTR_SPB2IO (0x0002u)
535#define SCIFn_SCSPTR_SCKDT (0x0004u)
536#define SCIFn_SCSPTR_SCKIO (0x0008u)
537#define SCIFn_SCSPTR_CTSDT (0x0010u)
538#define SCIFn_SCSPTR_CTSIO (0x0020u)
539#define SCIFn_SCSPTR_RTSDT (0x0040u)
540#define SCIFn_SCSPTR_RTSIO (0x0080u)
541
542#define SCIFn_SCLSR_ORER (0x0001u)
543
544#define SCIFn_SCEMR_ABCS (0x0001u)
545#define SCIFn_SCEMR_BGDM (0x0080u)
546
547
548/* ==== Shift values for IO registers ==== */
549/* ---- SCIF0 ---- */
550#define SCIF0_SCSMR_CKS_SHIFT (0u)
551#define SCIF0_SCSMR_STOP_SHIFT (3u)
552#define SCIF0_SCSMR_OE_SHIFT (4u)
553#define SCIF0_SCSMR_PE_SHIFT (5u)
554#define SCIF0_SCSMR_CHR_SHIFT (6u)
555#define SCIF0_SCSMR_CA_SHIFT (7u)
556
557#define SCIF0_SCBRR_D_SHIFT (0u)
558
559#define SCIF0_SCSCR_CKE_SHIFT (0u)
560#define SCIF0_SCSCR_REIE_SHIFT (3u)
561#define SCIF0_SCSCR_RE_SHIFT (4u)
562#define SCIF0_SCSCR_TE_SHIFT (5u)
563#define SCIF0_SCSCR_RIE_SHIFT (6u)
564#define SCIF0_SCSCR_TIE_SHIFT (7u)
565
566#define SCIF0_SCFTDR_D_SHIFT (0u)
567
568#define SCIF0_SCFSR_DR_SHIFT (0u)
569#define SCIF0_SCFSR_RDF_SHIFT (1u)
570#define SCIF0_SCFSR_PER_SHIFT (2u)
571#define SCIF0_SCFSR_FER_SHIFT (3u)
572#define SCIF0_SCFSR_BRK_SHIFT (4u)
573#define SCIF0_SCFSR_TDFE_SHIFT (5u)
574#define SCIF0_SCFSR_TEND_SHIFT (6u)
575#define SCIF0_SCFSR_ER_SHIFT (7u)
576#define SCIF0_SCFSR_FERN_SHIFT (8u)
577#define SCIF0_SCFSR_PERN_SHIFT (12u)
578
579#define SCIF0_SCFRDR_D_SHIFT (0u)
580
581#define SCIF0_SCFCR_LOOP_SHIFT (0u)
582#define SCIF0_SCFCR_RFRST_SHIFT (1u)
583#define SCIF0_SCFCR_TFRST_SHIFT (2u)
584#define SCIF0_SCFCR_MCE_SHIFT (3u)
585#define SCIF0_SCFCR_TTRG_SHIFT (4u)
586#define SCIF0_SCFCR_RTRG_SHIFT (6u)
587#define SCIF0_SCFCR_RSTRG_SHIFT (8u)
588
589#define SCIF0_SCFDR_R_SHIFT (0u)
590#define SCIF0_SCFDR_T_SHIFT (8u)
591
592#define SCIF0_SCSPTR_SPB2DT_SHIFT (0u)
593#define SCIF0_SCSPTR_SPB2IO_SHIFT (1u)
594#define SCIF0_SCSPTR_SCKDT_SHIFT (2u)
595#define SCIF0_SCSPTR_SCKIO_SHIFT (3u)
596#define SCIF0_SCSPTR_CTSDT_SHIFT (4u)
597#define SCIF0_SCSPTR_CTSIO_SHIFT (5u)
598#define SCIF0_SCSPTR_RTSDT_SHIFT (6u)
599#define SCIF0_SCSPTR_RTSIO_SHIFT (7u)
600
601#define SCIF0_SCLSR_ORER_SHIFT (0u)
602
603#define SCIF0_SCEMR_ABCS_SHIFT (0u)
604#define SCIF0_SCEMR_BGDM_SHIFT (7u)
605
606/* ---- SCIF1 ---- */
607#define SCIF1_SCSMR_CKS_SHIFT (0u)
608#define SCIF1_SCSMR_STOP_SHIFT (3u)
609#define SCIF1_SCSMR_OE_SHIFT (4u)
610#define SCIF1_SCSMR_PE_SHIFT (5u)
611#define SCIF1_SCSMR_CHR_SHIFT (6u)
612#define SCIF1_SCSMR_CA_SHIFT (7u)
613
614#define SCIF1_SCBRR_D_SHIFT (0u)
615
616#define SCIF1_SCSCR_CKE_SHIFT (0u)
617#define SCIF1_SCSCR_REIE_SHIFT (3u)
618#define SCIF1_SCSCR_RE_SHIFT (4u)
619#define SCIF1_SCSCR_TE_SHIFT (5u)
620#define SCIF1_SCSCR_RIE_SHIFT (6u)
621#define SCIF1_SCSCR_TIE_SHIFT (7u)
622
623#define SCIF1_SCFTDR_D_SHIFT (0u)
624
625#define SCIF1_SCFSR_DR_SHIFT (0u)
626#define SCIF1_SCFSR_RDF_SHIFT (1u)
627#define SCIF1_SCFSR_PER_SHIFT (2u)
628#define SCIF1_SCFSR_FER_SHIFT (3u)
629#define SCIF1_SCFSR_BRK_SHIFT (4u)
630#define SCIF1_SCFSR_TDFE_SHIFT (5u)
631#define SCIF1_SCFSR_TEND_SHIFT (6u)
632#define SCIF1_SCFSR_ER_SHIFT (7u)
633#define SCIF1_SCFSR_FERN_SHIFT (8u)
634#define SCIF1_SCFSR_PERN_SHIFT (12u)
635
636#define SCIF1_SCFRDR_D_SHIFT (0u)
637
638#define SCIF1_SCFCR_LOOP_SHIFT (0u)
639#define SCIF1_SCFCR_RFRST_SHIFT (1u)
640#define SCIF1_SCFCR_TFRST_SHIFT (2u)
641#define SCIF1_SCFCR_MCE_SHIFT (3u)
642#define SCIF1_SCFCR_TTRG_SHIFT (4u)
643#define SCIF1_SCFCR_RTRG_SHIFT (6u)
644#define SCIF1_SCFCR_RSTRG_SHIFT (8u)
645
646#define SCIF1_SCFDR_R_SHIFT (0u)
647#define SCIF1_SCFDR_T_SHIFT (8u)
648
649#define SCIF1_SCSPTR_SPB2DT_SHIFT (0u)
650#define SCIF1_SCSPTR_SPB2IO_SHIFT (1u)
651#define SCIF1_SCSPTR_SCKDT_SHIFT (2u)
652#define SCIF1_SCSPTR_SCKIO_SHIFT (3u)
653#define SCIF1_SCSPTR_CTSDT_SHIFT (4u)
654#define SCIF1_SCSPTR_CTSIO_SHIFT (5u)
655#define SCIF1_SCSPTR_RTSDT_SHIFT (6u)
656#define SCIF1_SCSPTR_RTSIO_SHIFT (7u)
657
658#define SCIF1_SCLSR_ORER_SHIFT (0u)
659
660#define SCIF1_SCEMR_ABCS_SHIFT (0u)
661#define SCIF1_SCEMR_BGDM_SHIFT (7u)
662
663/* ---- SCIF2 ---- */
664#define SCIF2_SCSMR_CKS_SHIFT (0u)
665#define SCIF2_SCSMR_STOP_SHIFT (3u)
666#define SCIF2_SCSMR_OE_SHIFT (4u)
667#define SCIF2_SCSMR_PE_SHIFT (5u)
668#define SCIF2_SCSMR_CHR_SHIFT (6u)
669#define SCIF2_SCSMR_CA_SHIFT (7u)
670
671#define SCIF2_SCBRR_D_SHIFT (0u)
672
673#define SCIF2_SCSCR_CKE_SHIFT (0u)
674#define SCIF2_SCSCR_REIE_SHIFT (3u)
675#define SCIF2_SCSCR_RE_SHIFT (4u)
676#define SCIF2_SCSCR_TE_SHIFT (5u)
677#define SCIF2_SCSCR_RIE_SHIFT (6u)
678#define SCIF2_SCSCR_TIE_SHIFT (7u)
679
680#define SCIF2_SCFTDR_D_SHIFT (0u)
681
682#define SCIF2_SCFSR_DR_SHIFT (0u)
683#define SCIF2_SCFSR_RDF_SHIFT (1u)
684#define SCIF2_SCFSR_PER_SHIFT (2u)
685#define SCIF2_SCFSR_FER_SHIFT (3u)
686#define SCIF2_SCFSR_BRK_SHIFT (4u)
687#define SCIF2_SCFSR_TDFE_SHIFT (5u)
688#define SCIF2_SCFSR_TEND_SHIFT (6u)
689#define SCIF2_SCFSR_ER_SHIFT (7u)
690#define SCIF2_SCFSR_FERN_SHIFT (8u)
691#define SCIF2_SCFSR_PERN_SHIFT (12u)
692
693#define SCIF2_SCFRDR_D_SHIFT (0u)
694
695#define SCIF2_SCFCR_LOOP_SHIFT (0u)
696#define SCIF2_SCFCR_RFRST_SHIFT (1u)
697#define SCIF2_SCFCR_TFRST_SHIFT (2u)
698#define SCIF2_SCFCR_MCE_SHIFT (3u)
699#define SCIF2_SCFCR_TTRG_SHIFT (4u)
700#define SCIF2_SCFCR_RTRG_SHIFT (6u)
701#define SCIF2_SCFCR_RSTRG_SHIFT (8u)
702
703#define SCIF2_SCFDR_R_SHIFT (0u)
704#define SCIF2_SCFDR_T_SHIFT (8u)
705
706#define SCIF2_SCSPTR_SPB2DT_SHIFT (0u)
707#define SCIF2_SCSPTR_SPB2IO_SHIFT (1u)
708#define SCIF2_SCSPTR_SCKDT_SHIFT (2u)
709#define SCIF2_SCSPTR_SCKIO_SHIFT (3u)
710#define SCIF2_SCSPTR_CTSDT_SHIFT (4u)
711#define SCIF2_SCSPTR_CTSIO_SHIFT (5u)
712#define SCIF2_SCSPTR_RTSDT_SHIFT (6u)
713#define SCIF2_SCSPTR_RTSIO_SHIFT (7u)
714
715#define SCIF2_SCLSR_ORER_SHIFT (0u)
716
717#define SCIF2_SCEMR_ABCS_SHIFT (0u)
718#define SCIF2_SCEMR_BGDM_SHIFT (7u)
719
720/* ---- SCIF3 ---- */
721#define SCIF3_SCSMR_CKS_SHIFT (0u)
722#define SCIF3_SCSMR_STOP_SHIFT (3u)
723#define SCIF3_SCSMR_OE_SHIFT (4u)
724#define SCIF3_SCSMR_PE_SHIFT (5u)
725#define SCIF3_SCSMR_CHR_SHIFT (6u)
726#define SCIF3_SCSMR_CA_SHIFT (7u)
727
728#define SCIF3_SCBRR_D_SHIFT (0u)
729
730#define SCIF3_SCSCR_CKE_SHIFT (0u)
731#define SCIF3_SCSCR_REIE_SHIFT (3u)
732#define SCIF3_SCSCR_RE_SHIFT (4u)
733#define SCIF3_SCSCR_TE_SHIFT (5u)
734#define SCIF3_SCSCR_RIE_SHIFT (6u)
735#define SCIF3_SCSCR_TIE_SHIFT (7u)
736
737#define SCIF3_SCFTDR_D_SHIFT (0u)
738
739#define SCIF3_SCFSR_DR_SHIFT (0u)
740#define SCIF3_SCFSR_RDF_SHIFT (1u)
741#define SCIF3_SCFSR_PER_SHIFT (2u)
742#define SCIF3_SCFSR_FER_SHIFT (3u)
743#define SCIF3_SCFSR_BRK_SHIFT (4u)
744#define SCIF3_SCFSR_TDFE_SHIFT (5u)
745#define SCIF3_SCFSR_TEND_SHIFT (6u)
746#define SCIF3_SCFSR_ER_SHIFT (7u)
747#define SCIF3_SCFSR_FERN_SHIFT (8u)
748#define SCIF3_SCFSR_PERN_SHIFT (12u)
749
750#define SCIF3_SCFRDR_D_SHIFT (0u)
751
752#define SCIF3_SCFCR_LOOP_SHIFT (0u)
753#define SCIF3_SCFCR_RFRST_SHIFT (1u)
754#define SCIF3_SCFCR_TFRST_SHIFT (2u)
755#define SCIF3_SCFCR_MCE_SHIFT (3u)
756#define SCIF3_SCFCR_TTRG_SHIFT (4u)
757#define SCIF3_SCFCR_RTRG_SHIFT (6u)
758#define SCIF3_SCFCR_RSTRG_SHIFT (8u)
759
760#define SCIF3_SCFDR_R_SHIFT (0u)
761#define SCIF3_SCFDR_T_SHIFT (8u)
762
763#define SCIF3_SCSPTR_SPB2DT_SHIFT (0u)
764#define SCIF3_SCSPTR_SPB2IO_SHIFT (1u)
765#define SCIF3_SCSPTR_SCKDT_SHIFT (2u)
766#define SCIF3_SCSPTR_SCKIO_SHIFT (3u)
767#define SCIF3_SCSPTR_CTSDT_SHIFT (4u)
768#define SCIF3_SCSPTR_CTSIO_SHIFT (5u)
769#define SCIF3_SCSPTR_RTSDT_SHIFT (6u)
770#define SCIF3_SCSPTR_RTSIO_SHIFT (7u)
771
772#define SCIF3_SCLSR_ORER_SHIFT (0u)
773
774#define SCIF3_SCEMR_ABCS_SHIFT (0u)
775#define SCIF3_SCEMR_BGDM_SHIFT (7u)
776
777/* ---- SCIF4 ---- */
778#define SCIF4_SCSMR_CKS_SHIFT (0u)
779#define SCIF4_SCSMR_STOP_SHIFT (3u)
780#define SCIF4_SCSMR_OE_SHIFT (4u)
781#define SCIF4_SCSMR_PE_SHIFT (5u)
782#define SCIF4_SCSMR_CHR_SHIFT (6u)
783#define SCIF4_SCSMR_CA_SHIFT (7u)
784
785#define SCIF4_SCBRR_D_SHIFT (0u)
786
787#define SCIF4_SCSCR_CKE_SHIFT (0u)
788#define SCIF4_SCSCR_REIE_SHIFT (3u)
789#define SCIF4_SCSCR_RE_SHIFT (4u)
790#define SCIF4_SCSCR_TE_SHIFT (5u)
791#define SCIF4_SCSCR_RIE_SHIFT (6u)
792#define SCIF4_SCSCR_TIE_SHIFT (7u)
793
794#define SCIF4_SCFTDR_D_SHIFT (0u)
795
796#define SCIF4_SCFSR_DR_SHIFT (0u)
797#define SCIF4_SCFSR_RDF_SHIFT (1u)
798#define SCIF4_SCFSR_PER_SHIFT (2u)
799#define SCIF4_SCFSR_FER_SHIFT (3u)
800#define SCIF4_SCFSR_BRK_SHIFT (4u)
801#define SCIF4_SCFSR_TDFE_SHIFT (5u)
802#define SCIF4_SCFSR_TEND_SHIFT (6u)
803#define SCIF4_SCFSR_ER_SHIFT (7u)
804#define SCIF4_SCFSR_FERN_SHIFT (8u)
805#define SCIF4_SCFSR_PERN_SHIFT (12u)
806
807#define SCIF4_SCFRDR_D_SHIFT (0u)
808
809#define SCIF4_SCFCR_LOOP_SHIFT (0u)
810#define SCIF4_SCFCR_RFRST_SHIFT (1u)
811#define SCIF4_SCFCR_TFRST_SHIFT (2u)
812#define SCIF4_SCFCR_MCE_SHIFT (3u)
813#define SCIF4_SCFCR_TTRG_SHIFT (4u)
814#define SCIF4_SCFCR_RTRG_SHIFT (6u)
815#define SCIF4_SCFCR_RSTRG_SHIFT (8u)
816
817#define SCIF4_SCFDR_R_SHIFT (0u)
818#define SCIF4_SCFDR_T_SHIFT (8u)
819
820#define SCIF4_SCSPTR_SPB2DT_SHIFT (0u)
821#define SCIF4_SCSPTR_SPB2IO_SHIFT (1u)
822#define SCIF4_SCSPTR_SCKDT_SHIFT (2u)
823#define SCIF4_SCSPTR_SCKIO_SHIFT (3u)
824#define SCIF4_SCSPTR_CTSDT_SHIFT (4u)
825#define SCIF4_SCSPTR_CTSIO_SHIFT (5u)
826#define SCIF4_SCSPTR_RTSDT_SHIFT (6u)
827#define SCIF4_SCSPTR_RTSIO_SHIFT (7u)
828
829#define SCIF4_SCLSR_ORER_SHIFT (0u)
830
831#define SCIF4_SCEMR_ABCS_SHIFT (0u)
832#define SCIF4_SCEMR_BGDM_SHIFT (7u)
833
834/* ---- SCIF5 ---- */
835#define SCIF5_SCSMR_CKS_SHIFT (0u)
836#define SCIF5_SCSMR_STOP_SHIFT (3u)
837#define SCIF5_SCSMR_OE_SHIFT (4u)
838#define SCIF5_SCSMR_PE_SHIFT (5u)
839#define SCIF5_SCSMR_CHR_SHIFT (6u)
840#define SCIF5_SCSMR_CA_SHIFT (7u)
841
842#define SCIF5_SCBRR_D_SHIFT (0u)
843
844#define SCIF5_SCSCR_CKE_SHIFT (0u)
845#define SCIF5_SCSCR_REIE_SHIFT (3u)
846#define SCIF5_SCSCR_RE_SHIFT (4u)
847#define SCIF5_SCSCR_TE_SHIFT (5u)
848#define SCIF5_SCSCR_RIE_SHIFT (6u)
849#define SCIF5_SCSCR_TIE_SHIFT (7u)
850
851#define SCIF5_SCFTDR_D_SHIFT (0u)
852
853#define SCIF5_SCFSR_DR_SHIFT (0u)
854#define SCIF5_SCFSR_RDF_SHIFT (1u)
855#define SCIF5_SCFSR_PER_SHIFT (2u)
856#define SCIF5_SCFSR_FER_SHIFT (3u)
857#define SCIF5_SCFSR_BRK_SHIFT (4u)
858#define SCIF5_SCFSR_TDFE_SHIFT (5u)
859#define SCIF5_SCFSR_TEND_SHIFT (6u)
860#define SCIF5_SCFSR_ER_SHIFT (7u)
861#define SCIF5_SCFSR_FERN_SHIFT (8u)
862#define SCIF5_SCFSR_PERN_SHIFT (12u)
863
864#define SCIF5_SCFRDR_D_SHIFT (0u)
865
866#define SCIF5_SCFCR_LOOP_SHIFT (0u)
867#define SCIF5_SCFCR_RFRST_SHIFT (1u)
868#define SCIF5_SCFCR_TFRST_SHIFT (2u)
869#define SCIF5_SCFCR_MCE_SHIFT (3u)
870#define SCIF5_SCFCR_TTRG_SHIFT (4u)
871#define SCIF5_SCFCR_RTRG_SHIFT (6u)
872#define SCIF5_SCFCR_RSTRG_SHIFT (8u)
873
874#define SCIF5_SCFDR_R_SHIFT (0u)
875#define SCIF5_SCFDR_T_SHIFT (8u)
876
877#define SCIF5_SCSPTR_SPB2DT_SHIFT (0u)
878#define SCIF5_SCSPTR_SPB2IO_SHIFT (1u)
879#define SCIF5_SCSPTR_SCKDT_SHIFT (2u)
880#define SCIF5_SCSPTR_SCKIO_SHIFT (3u)
881#define SCIF5_SCSPTR_CTSDT_SHIFT (4u)
882#define SCIF5_SCSPTR_CTSIO_SHIFT (5u)
883#define SCIF5_SCSPTR_RTSDT_SHIFT (6u)
884#define SCIF5_SCSPTR_RTSIO_SHIFT (7u)
885
886#define SCIF5_SCLSR_ORER_SHIFT (0u)
887
888#define SCIF5_SCEMR_ABCS_SHIFT (0u)
889#define SCIF5_SCEMR_BGDM_SHIFT (7u)
890
891/* ---- SCIF6 ---- */
892#define SCIF6_SCSMR_CKS_SHIFT (0u)
893#define SCIF6_SCSMR_STOP_SHIFT (3u)
894#define SCIF6_SCSMR_OE_SHIFT (4u)
895#define SCIF6_SCSMR_PE_SHIFT (5u)
896#define SCIF6_SCSMR_CHR_SHIFT (6u)
897#define SCIF6_SCSMR_CA_SHIFT (7u)
898
899#define SCIF6_SCBRR_D_SHIFT (0u)
900
901#define SCIF6_SCSCR_CKE_SHIFT (0u)
902#define SCIF6_SCSCR_REIE_SHIFT (3u)
903#define SCIF6_SCSCR_RE_SHIFT (4u)
904#define SCIF6_SCSCR_TE_SHIFT (5u)
905#define SCIF6_SCSCR_RIE_SHIFT (6u)
906#define SCIF6_SCSCR_TIE_SHIFT (7u)
907
908#define SCIF6_SCFTDR_D_SHIFT (0u)
909
910#define SCIF6_SCFSR_DR_SHIFT (0u)
911#define SCIF6_SCFSR_RDF_SHIFT (1u)
912#define SCIF6_SCFSR_PER_SHIFT (2u)
913#define SCIF6_SCFSR_FER_SHIFT (3u)
914#define SCIF6_SCFSR_BRK_SHIFT (4u)
915#define SCIF6_SCFSR_TDFE_SHIFT (5u)
916#define SCIF6_SCFSR_TEND_SHIFT (6u)
917#define SCIF6_SCFSR_ER_SHIFT (7u)
918#define SCIF6_SCFSR_FERN_SHIFT (8u)
919#define SCIF6_SCFSR_PERN_SHIFT (12u)
920
921#define SCIF6_SCFRDR_D_SHIFT (0u)
922
923#define SCIF6_SCFCR_LOOP_SHIFT (0u)
924#define SCIF6_SCFCR_RFRST_SHIFT (1u)
925#define SCIF6_SCFCR_TFRST_SHIFT (2u)
926#define SCIF6_SCFCR_MCE_SHIFT (3u)
927#define SCIF6_SCFCR_TTRG_SHIFT (4u)
928#define SCIF6_SCFCR_RTRG_SHIFT (6u)
929#define SCIF6_SCFCR_RSTRG_SHIFT (8u)
930
931#define SCIF6_SCFDR_R_SHIFT (0u)
932#define SCIF6_SCFDR_T_SHIFT (8u)
933
934#define SCIF6_SCSPTR_SPB2DT_SHIFT (0u)
935#define SCIF6_SCSPTR_SPB2IO_SHIFT (1u)
936#define SCIF6_SCSPTR_SCKDT_SHIFT (2u)
937#define SCIF6_SCSPTR_SCKIO_SHIFT (3u)
938#define SCIF6_SCSPTR_CTSDT_SHIFT (4u)
939#define SCIF6_SCSPTR_CTSIO_SHIFT (5u)
940#define SCIF6_SCSPTR_RTSDT_SHIFT (6u)
941#define SCIF6_SCSPTR_RTSIO_SHIFT (7u)
942
943#define SCIF6_SCLSR_ORER_SHIFT (0u)
944
945#define SCIF6_SCEMR_ABCS_SHIFT (0u)
946#define SCIF6_SCEMR_BGDM_SHIFT (7u)
947
948/* ---- SCIF7 ---- */
949#define SCIF7_SCSMR_CKS_SHIFT (0u)
950#define SCIF7_SCSMR_STOP_SHIFT (3u)
951#define SCIF7_SCSMR_OE_SHIFT (4u)
952#define SCIF7_SCSMR_PE_SHIFT (5u)
953#define SCIF7_SCSMR_CHR_SHIFT (6u)
954#define SCIF7_SCSMR_CA_SHIFT (7u)
955
956#define SCIF7_SCBRR_D_SHIFT (0u)
957
958#define SCIF7_SCSCR_CKE_SHIFT (0u)
959#define SCIF7_SCSCR_REIE_SHIFT (3u)
960#define SCIF7_SCSCR_RE_SHIFT (4u)
961#define SCIF7_SCSCR_TE_SHIFT (5u)
962#define SCIF7_SCSCR_RIE_SHIFT (6u)
963#define SCIF7_SCSCR_TIE_SHIFT (7u)
964
965#define SCIF7_SCFTDR_D_SHIFT (0u)
966
967#define SCIF7_SCFSR_DR_SHIFT (0u)
968#define SCIF7_SCFSR_RDF_SHIFT (1u)
969#define SCIF7_SCFSR_PER_SHIFT (2u)
970#define SCIF7_SCFSR_FER_SHIFT (3u)
971#define SCIF7_SCFSR_BRK_SHIFT (4u)
972#define SCIF7_SCFSR_TDFE_SHIFT (5u)
973#define SCIF7_SCFSR_TEND_SHIFT (6u)
974#define SCIF7_SCFSR_ER_SHIFT (7u)
975#define SCIF7_SCFSR_FERN_SHIFT (8u)
976#define SCIF7_SCFSR_PERN_SHIFT (12u)
977
978#define SCIF7_SCFRDR_D_SHIFT (0u)
979
980#define SCIF7_SCFCR_LOOP_SHIFT (0u)
981#define SCIF7_SCFCR_RFRST_SHIFT (1u)
982#define SCIF7_SCFCR_TFRST_SHIFT (2u)
983#define SCIF7_SCFCR_MCE_SHIFT (3u)
984#define SCIF7_SCFCR_TTRG_SHIFT (4u)
985#define SCIF7_SCFCR_RTRG_SHIFT (6u)
986#define SCIF7_SCFCR_RSTRG_SHIFT (8u)
987
988#define SCIF7_SCFDR_R_SHIFT (0u)
989#define SCIF7_SCFDR_T_SHIFT (8u)
990
991#define SCIF7_SCSPTR_SPB2DT_SHIFT (0u)
992#define SCIF7_SCSPTR_SPB2IO_SHIFT (1u)
993#define SCIF7_SCSPTR_SCKDT_SHIFT (2u)
994#define SCIF7_SCSPTR_SCKIO_SHIFT (3u)
995#define SCIF7_SCSPTR_CTSDT_SHIFT (4u)
996#define SCIF7_SCSPTR_CTSIO_SHIFT (5u)
997#define SCIF7_SCSPTR_RTSDT_SHIFT (6u)
998#define SCIF7_SCSPTR_RTSIO_SHIFT (7u)
999
1000#define SCIF7_SCLSR_ORER_SHIFT (0u)
1001
1002#define SCIF7_SCEMR_ABCS_SHIFT (0u)
1003#define SCIF7_SCEMR_BGDM_SHIFT (7u)
1004
1005/* ---- SCIFn ---- */
1006#define SCIFn_SCSMR_CKS_SHIFT (0u)
1007#define SCIFn_SCSMR_STOP_SHIFT (3u)
1008#define SCIFn_SCSMR_OE_SHIFT (4u)
1009#define SCIFn_SCSMR_PE_SHIFT (5u)
1010#define SCIFn_SCSMR_CHR_SHIFT (6u)
1011#define SCIFn_SCSMR_CA_SHIFT (7u)
1012
1013#define SCIFn_SCBRR_D_SHIFT (0u)
1014
1015#define SCIFn_SCSCR_CKE_SHIFT (0u)
1016#define SCIFn_SCSCR_REIE_SHIFT (3u)
1017#define SCIFn_SCSCR_RE_SHIFT (4u)
1018#define SCIFn_SCSCR_TE_SHIFT (5u)
1019#define SCIFn_SCSCR_RIE_SHIFT (6u)
1020#define SCIFn_SCSCR_TIE_SHIFT (7u)
1021
1022#define SCIFn_SCFTDR_D_SHIFT (0u)
1023
1024#define SCIFn_SCFSR_DR_SHIFT (0u)
1025#define SCIFn_SCFSR_RDF_SHIFT (1u)
1026#define SCIFn_SCFSR_PER_SHIFT (2u)
1027#define SCIFn_SCFSR_FER_SHIFT (3u)
1028#define SCIFn_SCFSR_BRK_SHIFT (4u)
1029#define SCIFn_SCFSR_TDFE_SHIFT (5u)
1030#define SCIFn_SCFSR_TEND_SHIFT (6u)
1031#define SCIFn_SCFSR_ER_SHIFT (7u)
1032#define SCIFn_SCFSR_FERN_SHIFT (8u)
1033#define SCIFn_SCFSR_PERN_SHIFT (12u)
1034
1035#define SCIFn_SCFRDR_D_SHIFT (0u)
1036
1037#define SCIFn_SCFCR_LOOP_SHIFT (0u)
1038#define SCIFn_SCFCR_RFRST_SHIFT (1u)
1039#define SCIFn_SCFCR_TFRST_SHIFT (2u)
1040#define SCIFn_SCFCR_MCE_SHIFT (3u)
1041#define SCIFn_SCFCR_TTRG_SHIFT (4u)
1042#define SCIFn_SCFCR_RTRG_SHIFT (6u)
1043#define SCIFn_SCFCR_RSTRG_SHIFT (8u)
1044
1045#define SCIFn_SCFDR_R_SHIFT (0u)
1046#define SCIFn_SCFDR_T_SHIFT (8u)
1047
1048#define SCIFn_SCSPTR_SPB2DT_SHIFT (0u)
1049#define SCIFn_SCSPTR_SPB2IO_SHIFT (1u)
1050#define SCIFn_SCSPTR_SCKDT_SHIFT (2u)
1051#define SCIFn_SCSPTR_SCKIO_SHIFT (3u)
1052#define SCIFn_SCSPTR_CTSDT_SHIFT (4u)
1053#define SCIFn_SCSPTR_CTSIO_SHIFT (5u)
1054#define SCIFn_SCSPTR_RTSDT_SHIFT (6u)
1055#define SCIFn_SCSPTR_RTSIO_SHIFT (7u)
1056
1057#define SCIFn_SCLSR_ORER_SHIFT (0u)
1058
1059#define SCIFn_SCEMR_ABCS_SHIFT (0u)
1060#define SCIFn_SCEMR_BGDM_SHIFT (7u)
1061
1062
1063#endif /* SCIF_IOBITMASK_H */
1064
1065/* End of File */
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