source: asp3_tinet_ecnl_arm/trunk/asp3_dcre/mbed/targets/TARGET_RENESAS/TARGET_RZ_A1H/device/inc/iobitmasks/rspi_iobitmask.h@ 352

Last change on this file since 352 was 352, checked in by coas-nagasima, 6 years ago

arm向けASP3版ECNLを追加
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1/*******************************************************************************
2* DISCLAIMER
3* This software is supplied by Renesas Electronics Corporation and is only
4* intended for use with Renesas products. No other uses are authorized. This
5* software is owned by Renesas Electronics Corporation and is protected under
6* all applicable laws, including copyright laws.
7* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
8* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
9* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
10* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
11* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
12* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
13* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
14* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
15* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
16* Renesas reserves the right, without notice, to make changes to this software
17* and to discontinue the availability of this software. By using this software,
18* you agree to the additional terms and conditions found by accessing the
19* following link:
20* http://www.renesas.com/disclaimer
21* Copyright (C) 2012 - 2014 Renesas Electronics Corporation. All rights reserved.
22*******************************************************************************/
23/*******************************************************************************
24* File Name : rspi_iobitmask.h
25* $Rev: 1114 $
26* $Date:: 2014-07-09 14:56:39 +0900#$
27* Description : Renesas Serial Peripheral Interface register define header
28*******************************************************************************/
29#ifndef RSPI_IOBITMASK_H
30#define RSPI_IOBITMASK_H
31
32
33/* ==== Mask values for IO registers ==== */
34#define RSPIn_SPCR_MODFEN (0x04u)
35#define RSPIn_SPCR_MSTR (0x08u)
36#define RSPIn_SPCR_SPEIE (0x10u)
37#define RSPIn_SPCR_SPTIE (0x20u)
38#define RSPIn_SPCR_SPE (0x40u)
39#define RSPIn_SPCR_SPRIE (0x80u)
40
41#define RSPIn_SSLP_SSL0P (0x01u)
42
43#define RSPIn_SPPCR_SPLP (0x01u)
44#define RSPIn_SPPCR_MOIFV (0x10u)
45#define RSPIn_SPPCR_MOIFE (0x20u)
46
47#define RSPIn_SPSR_OVRF (0x01u)
48#define RSPIn_SPSR_MODF (0x04u)
49#define RSPIn_SPSR_SPTEF (0x20u)
50#define RSPIn_SPSR_TEND (0x40u)
51#define RSPIn_SPSR_SPRF (0x80u)
52
53#define RSPIn_SPDR_UINT32 (0xFFFFFFFFuL)
54
55#define RSPIn_SPDR_UINT16 (0xFFFFu)
56
57#define RSPIn_SPDR_UINT8 (0xFFu)
58
59#define RSPIn_SPSCR_SPSLN (0x03u)
60
61#define RSPIn_SPSSR_SPCP (0x03u)
62
63#define RSPIn_SPBR_SPR (0xFFu)
64
65#define RSPIn_SPDCR_SPLW (0x60u)
66#define RSPIn_SPDCR_TXDMY (0x80u)
67
68#define RSPIn_SPCKD_SCKDL (0x07u)
69
70#define RSPIn_SSLND_SLNDL (0x07u)
71
72#define RSPIn_SPND_SPNDL (0x07u)
73
74#define RSPIn_SPCMD0_CPHA (0x0001u)
75#define RSPIn_SPCMD0_CPOL (0x0002u)
76#define RSPIn_SPCMD0_BRDV (0x000Cu)
77#define RSPIn_SPCMD0_SSLKP (0x0080u)
78#define RSPIn_SPCMD0_SPB (0x0F00u)
79#define RSPIn_SPCMD0_LSBF (0x1000u)
80#define RSPIn_SPCMD0_SPNDEN (0x2000u)
81#define RSPIn_SPCMD0_SLNDEN (0x4000u)
82#define RSPIn_SPCMD0_SCKDEN (0x8000u)
83
84#define RSPIn_SPCMD1_CPHA (0x0001u)
85#define RSPIn_SPCMD1_CPOL (0x0002u)
86#define RSPIn_SPCMD1_BRDV (0x000Cu)
87#define RSPIn_SPCMD1_SSLKP (0x0080u)
88#define RSPIn_SPCMD1_SPB (0x0F00u)
89#define RSPIn_SPCMD1_LSBF (0x1000u)
90#define RSPIn_SPCMD1_SPNDEN (0x2000u)
91#define RSPIn_SPCMD1_SLNDEN (0x4000u)
92#define RSPIn_SPCMD1_SCKDEN (0x8000u)
93
94#define RSPIn_SPCMD2_CPHA (0x0001u)
95#define RSPIn_SPCMD2_CPOL (0x0002u)
96#define RSPIn_SPCMD2_BRDV (0x000Cu)
97#define RSPIn_SPCMD2_SSLKP (0x0080u)
98#define RSPIn_SPCMD2_SPB (0x0F00u)
99#define RSPIn_SPCMD2_LSBF (0x1000u)
100#define RSPIn_SPCMD2_SPNDEN (0x2000u)
101#define RSPIn_SPCMD2_SLNDEN (0x4000u)
102#define RSPIn_SPCMD2_SCKDEN (0x8000u)
103
104#define RSPIn_SPCMD3_CPHA (0x0001u)
105#define RSPIn_SPCMD3_CPOL (0x0002u)
106#define RSPIn_SPCMD3_BRDV (0x000Cu)
107#define RSPIn_SPCMD3_SSLKP (0x0080u)
108#define RSPIn_SPCMD3_SPB (0x0F00u)
109#define RSPIn_SPCMD3_LSBF (0x1000u)
110#define RSPIn_SPCMD3_SPNDEN (0x2000u)
111#define RSPIn_SPCMD3_SLNDEN (0x4000u)
112#define RSPIn_SPCMD3_SCKDEN (0x8000u)
113
114#define RSPIn_SPBFCR_RXTRG (0x07u)
115#define RSPIn_SPBFCR_TXTRG (0x30u)
116#define RSPIn_SPBFCR_RXRST (0x40u)
117#define RSPIn_SPBFCR_TXRST (0x80u)
118
119#define RSPIn_SPBFDR_R (0x003Fu)
120#define RSPIn_SPBFDR_T (0x0F00u)
121
122
123/* ==== Shift values for IO registers ==== */
124#define RSPIn_SPCR_MODFEN_SHIFT (2u)
125#define RSPIn_SPCR_MSTR_SHIFT (3u)
126#define RSPIn_SPCR_SPEIE_SHIFT (4u)
127#define RSPIn_SPCR_SPTIE_SHIFT (5u)
128#define RSPIn_SPCR_SPE_SHIFT (6u)
129#define RSPIn_SPCR_SPRIE_SHIFT (7u)
130
131#define RSPIn_SSLP_SSL0P_SHIFT (0u)
132
133#define RSPIn_SPPCR_SPLP_SHIFT (0u)
134#define RSPIn_SPPCR_MOIFV_SHIFT (4u)
135#define RSPIn_SPPCR_MOIFE_SHIFT (5u)
136
137#define RSPIn_SPSR_OVRF_SHIFT (0u)
138#define RSPIn_SPSR_MODF_SHIFT (2u)
139#define RSPIn_SPSR_SPTEF_SHIFT (5u)
140#define RSPIn_SPSR_TEND_SHIFT (6u)
141#define RSPIn_SPSR_SPRF_SHIFT (7u)
142
143#define RSPIn_SPDR_UINT32_SHIFT (0u)
144
145#define RSPIn_SPDR_UINT16_SHIFT (0u)
146
147#define RSPIn_SPDR_UINT8_SHIFT (0u)
148
149#define RSPIn_SPSCR_SPSLN_SHIFT (0u)
150
151#define RSPIn_SPSSR_SPCP_SHIFT (0u)
152
153#define RSPIn_SPBR_SPR_SHIFT (0u)
154
155#define RSPIn_SPDCR_SPLW_SHIFT (5u)
156#define RSPIn_SPDCR_TXDMY_SHIFT (7u)
157
158#define RSPIn_SPCKD_SCKDL_SHIFT (0u)
159
160#define RSPIn_SSLND_SLNDL_SHIFT (0u)
161
162#define RSPIn_SPND_SPNDL_SHIFT (0u)
163
164#define RSPIn_SPCMD0_CPHA_SHIFT (0u)
165#define RSPIn_SPCMD0_CPOL_SHIFT (1u)
166#define RSPIn_SPCMD0_BRDV_SHIFT (2u)
167#define RSPIn_SPCMD0_SSLKP_SHIFT (7u)
168#define RSPIn_SPCMD0_SPB_SHIFT (8u)
169#define RSPIn_SPCMD0_LSBF_SHIFT (12u)
170#define RSPIn_SPCMD0_SPNDEN_SHIFT (13u)
171#define RSPIn_SPCMD0_SLNDEN_SHIFT (14u)
172#define RSPIn_SPCMD0_SCKDEN_SHIFT (15u)
173
174#define RSPIn_SPCMD1_CPHA_SHIFT (0u)
175#define RSPIn_SPCMD1_CPOL_SHIFT (1u)
176#define RSPIn_SPCMD1_BRDV_SHIFT (2u)
177#define RSPIn_SPCMD1_SSLKP_SHIFT (7u)
178#define RSPIn_SPCMD1_SPB_SHIFT (8u)
179#define RSPIn_SPCMD1_LSBF_SHIFT (12u)
180#define RSPIn_SPCMD1_SPNDEN_SHIFT (13u)
181#define RSPIn_SPCMD1_SLNDEN_SHIFT (14u)
182#define RSPIn_SPCMD1_SCKDEN_SHIFT (15u)
183
184#define RSPIn_SPCMD2_CPHA_SHIFT (0u)
185#define RSPIn_SPCMD2_CPOL_SHIFT (1u)
186#define RSPIn_SPCMD2_BRDV_SHIFT (2u)
187#define RSPIn_SPCMD2_SSLKP_SHIFT (7u)
188#define RSPIn_SPCMD2_SPB_SHIFT (8u)
189#define RSPIn_SPCMD2_LSBF_SHIFT (12u)
190#define RSPIn_SPCMD2_SPNDEN_SHIFT (13u)
191#define RSPIn_SPCMD2_SLNDEN_SHIFT (14u)
192#define RSPIn_SPCMD2_SCKDEN_SHIFT (15u)
193
194#define RSPIn_SPCMD3_CPHA_SHIFT (0u)
195#define RSPIn_SPCMD3_CPOL_SHIFT (1u)
196#define RSPIn_SPCMD3_BRDV_SHIFT (2u)
197#define RSPIn_SPCMD3_SSLKP_SHIFT (7u)
198#define RSPIn_SPCMD3_SPB_SHIFT (8u)
199#define RSPIn_SPCMD3_LSBF_SHIFT (12u)
200#define RSPIn_SPCMD3_SPNDEN_SHIFT (13u)
201#define RSPIn_SPCMD3_SLNDEN_SHIFT (14u)
202#define RSPIn_SPCMD3_SCKDEN_SHIFT (15u)
203
204#define RSPIn_SPBFCR_RXTRG_SHIFT (0u)
205#define RSPIn_SPBFCR_TXTRG_SHIFT (4u)
206#define RSPIn_SPBFCR_RXRST_SHIFT (6u)
207#define RSPIn_SPBFCR_TXRST_SHIFT (7u)
208
209#define RSPIn_SPBFDR_R_SHIFT (0u)
210#define RSPIn_SPBFDR_T_SHIFT (8u)
211
212
213#endif /* RSPI_IOBITMASK_H */
214
215/* End of File */
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