| 1 | /*******************************************************************************
|
|---|
| 2 | * DISCLAIMER
|
|---|
| 3 | * This software is supplied by Renesas Electronics Corporation and is only
|
|---|
| 4 | * intended for use with Renesas products. No other uses are authorized. This
|
|---|
| 5 | * software is owned by Renesas Electronics Corporation and is protected under
|
|---|
| 6 | * all applicable laws, including copyright laws.
|
|---|
| 7 | * THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
|
|---|
| 8 | * THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
|
|---|
| 9 | * LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
|
|---|
| 10 | * AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
|
|---|
| 11 | * TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
|
|---|
| 12 | * ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
|
|---|
| 13 | * FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
|
|---|
| 14 | * ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
|
|---|
| 15 | * BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
|
|---|
| 16 | * Renesas reserves the right, without notice, to make changes to this software
|
|---|
| 17 | * and to discontinue the availability of this software. By using this software,
|
|---|
| 18 | * you agree to the additional terms and conditions found by accessing the
|
|---|
| 19 | * following link:
|
|---|
| 20 | * http://www.renesas.com/disclaimer
|
|---|
| 21 | * Copyright (C) 2012 - 2014 Renesas Electronics Corporation. All rights reserved.
|
|---|
| 22 | *******************************************************************************/
|
|---|
| 23 | /*******************************************************************************
|
|---|
| 24 | * File Name : mtu2_iobitmask.h
|
|---|
| 25 | * $Rev: 1138 $
|
|---|
| 26 | * $Date:: 2014-08-08 11:03:56 +0900#$
|
|---|
| 27 | * Description : MTU2 register define header
|
|---|
| 28 | *******************************************************************************/
|
|---|
| 29 | #ifndef MTU2_IOBITMASK_H
|
|---|
| 30 | #define MTU2_IOBITMASK_H
|
|---|
| 31 |
|
|---|
| 32 |
|
|---|
| 33 | /* ==== Mask values for IO registers ==== */
|
|---|
| 34 | #define MTU2_TCR_n_TPSC (0x07u)
|
|---|
| 35 | #define MTU2_TCR_n_CKEG (0x18u)
|
|---|
| 36 | #define MTU2_TCR_n_CCLR (0xE0u)
|
|---|
| 37 |
|
|---|
| 38 | #define MTU2_TMDR_n_MD (0x0Fu)
|
|---|
| 39 |
|
|---|
| 40 | #define MTU2_TIOR_2_IOA (0x0Fu)
|
|---|
| 41 | #define MTU2_TIOR_2_IOB (0xF0u)
|
|---|
| 42 |
|
|---|
| 43 | #define MTU2_TIER_n_TGIEA (0x01u)
|
|---|
| 44 | #define MTU2_TIER_n_TGIEB (0x02u)
|
|---|
| 45 | #define MTU2_TIER_n_TCIEV (0x10u)
|
|---|
| 46 | #define MTU2_TIER_2_TCIEU (0x20u)
|
|---|
| 47 | #define MTU2_TIER_n_TTGE (0x80u)
|
|---|
| 48 |
|
|---|
| 49 | #define MTU2_TSR_n_TGFA (0x01u)
|
|---|
| 50 | #define MTU2_TSR_n_TGFB (0x02u)
|
|---|
| 51 | #define MTU2_TSR_n_TCFV (0x10u)
|
|---|
| 52 | #define MTU2_TSR_2_TCFU (0x20u)
|
|---|
| 53 | #define MTU2_TSR_2_TCFD (0x80u)
|
|---|
| 54 |
|
|---|
| 55 | #define MTU2_TCNT_n_D (0xFFFFu)
|
|---|
| 56 |
|
|---|
| 57 | #define MTU2_TGRA_n_D (0xFFFFu)
|
|---|
| 58 |
|
|---|
| 59 | #define MTU2_TGRB_n_D (0xFFFFu)
|
|---|
| 60 |
|
|---|
| 61 | #define MTU2_TMDR_3_BFA (0x10u)
|
|---|
| 62 | #define MTU2_TMDR_3_BFB (0x20u)
|
|---|
| 63 |
|
|---|
| 64 | #define MTU2_TMDR_4_BFA (0x10u)
|
|---|
| 65 | #define MTU2_TMDR_4_BFB (0x20u)
|
|---|
| 66 |
|
|---|
| 67 | #define MTU2_TIORH_3_IOA (0x0Fu)
|
|---|
| 68 | #define MTU2_TIORH_3_IOB (0xF0u)
|
|---|
| 69 |
|
|---|
| 70 | #define MTU2_TIORL_3_IOC (0x0Fu)
|
|---|
| 71 | #define MTU2_TIORL_3_IOD (0xF0u)
|
|---|
| 72 |
|
|---|
| 73 | #define MTU2_TIORH_4_IOA (0x0Fu)
|
|---|
| 74 | #define MTU2_TIORH_4_IOB (0xF0u)
|
|---|
| 75 |
|
|---|
| 76 | #define MTU2_TIORL_4_IOC (0x0Fu)
|
|---|
| 77 | #define MTU2_TIORL_4_IOD (0xF0u)
|
|---|
| 78 |
|
|---|
| 79 | #define MTU2_TIER_3_TGIEC (0x04u)
|
|---|
| 80 | #define MTU2_TIER_3_TGIED (0x08u)
|
|---|
| 81 |
|
|---|
| 82 | #define MTU2_TIER_4_TGIEC (0x04u)
|
|---|
| 83 | #define MTU2_TIER_4_TGIED (0x08u)
|
|---|
| 84 | #define MTU2_TIER_4_TTGE2 (0x40u)
|
|---|
| 85 |
|
|---|
| 86 | #define MTU2_TOER_OE3B (0x01u)
|
|---|
| 87 | #define MTU2_TOER_OE4A (0x02u)
|
|---|
| 88 | #define MTU2_TOER_OE4B (0x04u)
|
|---|
| 89 | #define MTU2_TOER_OE3D (0x08u)
|
|---|
| 90 | #define MTU2_TOER_OE4C (0x10u)
|
|---|
| 91 | #define MTU2_TOER_OE4D (0x20u)
|
|---|
| 92 |
|
|---|
| 93 | #define MTU2_TGCR_UF (0x01u)
|
|---|
| 94 | #define MTU2_TGCR_VF (0x02u)
|
|---|
| 95 | #define MTU2_TGCR_WF (0x04u)
|
|---|
| 96 | #define MTU2_TGCR_FB (0x08u)
|
|---|
| 97 | #define MTU2_TGCR_P (0x10u)
|
|---|
| 98 | #define MTU2_TGCR_N (0x20u)
|
|---|
| 99 | #define MTU2_TGCR_BDC (0x40u)
|
|---|
| 100 |
|
|---|
| 101 | #define MTU2_TOCR1_OLSP (0x01u)
|
|---|
| 102 | #define MTU2_TOCR1_OLSN (0x02u)
|
|---|
| 103 | #define MTU2_TOCR1_TOCS (0x04u)
|
|---|
| 104 | #define MTU2_TOCR1_TOCL (0x08u)
|
|---|
| 105 | #define MTU2_TOCR1_PSYE (0x40u)
|
|---|
| 106 |
|
|---|
| 107 | #define MTU2_TOCR2_OLS1P (0x01u)
|
|---|
| 108 | #define MTU2_TOCR2_OLS1N (0x02u)
|
|---|
| 109 | #define MTU2_TOCR2_OLS2P (0x04u)
|
|---|
| 110 | #define MTU2_TOCR2_OLS2N (0x08u)
|
|---|
| 111 | #define MTU2_TOCR2_OLS3P (0x10u)
|
|---|
| 112 | #define MTU2_TOCR2_OLS3N (0x20u)
|
|---|
| 113 | #define MTU2_TOCR2_BF (0xC0u)
|
|---|
| 114 |
|
|---|
| 115 | #define MTU2_TCDR_D (0xFFFFu)
|
|---|
| 116 |
|
|---|
| 117 | #define MTU2_TDDR_D (0xFFFFu)
|
|---|
| 118 |
|
|---|
| 119 | #define MTU2_TCNTS_D (0xFFFFu)
|
|---|
| 120 |
|
|---|
| 121 | #define MTU2_TCBR_D (0xFFFFu)
|
|---|
| 122 |
|
|---|
| 123 | #define MTU2_TGRC_3_D (0xFFFFu)
|
|---|
| 124 |
|
|---|
| 125 | #define MTU2_TGRD_3_D (0xFFFFu)
|
|---|
| 126 |
|
|---|
| 127 | #define MTU2_TGRC_4_D (0xFFFFu)
|
|---|
| 128 |
|
|---|
| 129 | #define MTU2_TGRD_4_D (0xFFFFu)
|
|---|
| 130 |
|
|---|
| 131 | #define MTU2_TSR_3_TGFC (0x04u)
|
|---|
| 132 | #define MTU2_TSR_3_TGFD (0x08u)
|
|---|
| 133 | #define MTU2_TSR_3_TCFD (0x80u)
|
|---|
| 134 |
|
|---|
| 135 | #define MTU2_TSR_4_TGFC (0x04u)
|
|---|
| 136 | #define MTU2_TSR_4_TGFD (0x08u)
|
|---|
| 137 | #define MTU2_TSR_4_TCFD (0x80u)
|
|---|
| 138 |
|
|---|
| 139 | #define MTU2_TITCR_4VCOR (0x07u)
|
|---|
| 140 | #define MTU2_TITCR_T4VEN (0x08u)
|
|---|
| 141 | #define MTU2_TITCR_3ACOR (0x70u)
|
|---|
| 142 | #define MTU2_TITCR_T3AEN (0x80u)
|
|---|
| 143 |
|
|---|
| 144 | #define MTU2_TITCNT_4VCNT (0x07u)
|
|---|
| 145 | #define MTU2_TITCNT_3ACNT (0x70u)
|
|---|
| 146 |
|
|---|
| 147 | #define MTU2_TBTER_BTE (0x03u)
|
|---|
| 148 |
|
|---|
| 149 | #define MTU2_TDER_TDER (0x01u)
|
|---|
| 150 |
|
|---|
| 151 | #define MTU2_TOLBR_OLS1P (0x01u)
|
|---|
| 152 | #define MTU2_TOLBR_OLS1N (0x02u)
|
|---|
| 153 | #define MTU2_TOLBR_OLS2P (0x04u)
|
|---|
| 154 | #define MTU2_TOLBR_OLS2N (0x08u)
|
|---|
| 155 | #define MTU2_TOLBR_OLS3P (0x10u)
|
|---|
| 156 | #define MTU2_TOLBR_OLS3N (0x20u)
|
|---|
| 157 |
|
|---|
| 158 | #define MTU2_TBTM_3_TTSA (0x01u)
|
|---|
| 159 | #define MTU2_TBTM_3_TTSB (0x02u)
|
|---|
| 160 |
|
|---|
| 161 | #define MTU2_TBTM_4_TTSA (0x01u)
|
|---|
| 162 | #define MTU2_TBTM_4_TTSB (0x02u)
|
|---|
| 163 |
|
|---|
| 164 | #define MTU2_TADCR_ITB4VE (0x0001u)
|
|---|
| 165 | #define MTU2_TADCR_ITB3AE (0x0002u)
|
|---|
| 166 | #define MTU2_TADCR_ITA4VE (0x0004u)
|
|---|
| 167 | #define MTU2_TADCR_ITA3AE (0x0008u)
|
|---|
| 168 | #define MTU2_TADCR_DT4BE (0x0010u)
|
|---|
| 169 | #define MTU2_TADCR_UT4BE (0x0020u)
|
|---|
| 170 | #define MTU2_TADCR_DT4AE (0x0040u)
|
|---|
| 171 | #define MTU2_TADCR_UT4AE (0x0080u)
|
|---|
| 172 | #define MTU2_TADCR_BF (0xC000u)
|
|---|
| 173 |
|
|---|
| 174 | #define MTU2_TADCORA_4_D (0xFFFFu)
|
|---|
| 175 |
|
|---|
| 176 | #define MTU2_TADCORB_4_D (0xFFFFu)
|
|---|
| 177 |
|
|---|
| 178 | #define MTU2_TADCOBRA_4_D (0xFFFFu)
|
|---|
| 179 |
|
|---|
| 180 | #define MTU2_TADCOBRB_4_D (0xFFFFu)
|
|---|
| 181 |
|
|---|
| 182 | #define MTU2_TWCR_WRE (0x01u)
|
|---|
| 183 | #define MTU2_TWCR_CCE (0x80u)
|
|---|
| 184 |
|
|---|
| 185 | #define MTU2_TSTR_CST0 (0x01u)
|
|---|
| 186 | #define MTU2_TSTR_CST1 (0x02u)
|
|---|
| 187 | #define MTU2_TSTR_CST2 (0x04u)
|
|---|
| 188 | #define MTU2_TSTR_CST3 (0x40u)
|
|---|
| 189 | #define MTU2_TSTR_CST4 (0x80u)
|
|---|
| 190 |
|
|---|
| 191 | #define MTU2_TSYR_SYNC0 (0x01u)
|
|---|
| 192 | #define MTU2_TSYR_SYNC1 (0x02u)
|
|---|
| 193 | #define MTU2_TSYR_SYNC2 (0x04u)
|
|---|
| 194 | #define MTU2_TSYR_SYNC3 (0x40u)
|
|---|
| 195 | #define MTU2_TSYR_SYNC4 (0x80u)
|
|---|
| 196 |
|
|---|
| 197 | #define MTU2_TRWER_RWE (0x01u)
|
|---|
| 198 |
|
|---|
| 199 | #define MTU2_TMDR_0_BFA (0x10u)
|
|---|
| 200 | #define MTU2_TMDR_0_BFB (0x20u)
|
|---|
| 201 | #define MTU2_TMDR_0_BFE (0x40u)
|
|---|
| 202 |
|
|---|
| 203 | #define MTU2_TIORH_0_IOA (0x0Fu)
|
|---|
| 204 | #define MTU2_TIORH_0_IOB (0xF0u)
|
|---|
| 205 |
|
|---|
| 206 | #define MTU2_TIORL_0_IOC (0x0Fu)
|
|---|
| 207 | #define MTU2_TIORL_0_IOD (0xF0u)
|
|---|
| 208 |
|
|---|
| 209 | #define MTU2_TIER_0_TGIEC (0x04u)
|
|---|
| 210 | #define MTU2_TIER_0_TGIED (0x08u)
|
|---|
| 211 |
|
|---|
| 212 | #define MTU2_TSR_0_TGFC (0x04u)
|
|---|
| 213 | #define MTU2_TSR_0_TGFD (0x08u)
|
|---|
| 214 |
|
|---|
| 215 | #define MTU2_TGRC_0_D (0xFFFFu)
|
|---|
| 216 |
|
|---|
| 217 | #define MTU2_TGRD_0_D (0xFFFFu)
|
|---|
| 218 |
|
|---|
| 219 | #define MTU2_TGRE_0_D (0xFFFFu)
|
|---|
| 220 |
|
|---|
| 221 | #define MTU2_TGRF_0_D (0xFFFFu)
|
|---|
| 222 |
|
|---|
| 223 | #define MTU2_TIER2_0_TGIEE (0x01u)
|
|---|
| 224 | #define MTU2_TIER2_0_TGIEF (0x02u)
|
|---|
| 225 |
|
|---|
| 226 | #define MTU2_TSR2_0_TGFE (0x01u)
|
|---|
| 227 | #define MTU2_TSR2_0_TGFF (0x02u)
|
|---|
| 228 |
|
|---|
| 229 | #define MTU2_TBTM_0_TTSA (0x01u)
|
|---|
| 230 | #define MTU2_TBTM_0_TTSB (0x02u)
|
|---|
| 231 | #define MTU2_TBTM_0_TTSE (0x04u)
|
|---|
| 232 |
|
|---|
| 233 | #define MTU2_TIOR_1_IOA (0x0Fu)
|
|---|
| 234 | #define MTU2_TIOR_1_IOB (0xF0u)
|
|---|
| 235 |
|
|---|
| 236 | #define MTU2_TIER_1_TCIEU (0x20u)
|
|---|
| 237 |
|
|---|
| 238 | #define MTU2_TSR_1_TCFU (0x20u)
|
|---|
| 239 | #define MTU2_TSR_1_TCFD (0x80u)
|
|---|
| 240 |
|
|---|
| 241 | #define MTU2_TICCR_I1AE (0x01u)
|
|---|
| 242 | #define MTU2_TICCR_I1BE (0x02u)
|
|---|
| 243 | #define MTU2_TICCR_I2AE (0x04u)
|
|---|
| 244 | #define MTU2_TICCR_I2BE (0x08u)
|
|---|
| 245 |
|
|---|
| 246 |
|
|---|
| 247 | /* ==== Shift values for IO registers ==== */
|
|---|
| 248 | #define MTU2_TCR_n_TPSC_SHIFT (0u)
|
|---|
| 249 | #define MTU2_TCR_n_CKEG_SHIFT (3u)
|
|---|
| 250 | #define MTU2_TCR_n_CCLR_SHIFT (5u)
|
|---|
| 251 |
|
|---|
| 252 | #define MTU2_TMDR_n_MD_SHIFT (0u)
|
|---|
| 253 |
|
|---|
| 254 | #define MTU2_TIOR_2_IOA_SHIFT (0u)
|
|---|
| 255 | #define MTU2_TIOR_2_IOB_SHIFT (4u)
|
|---|
| 256 |
|
|---|
| 257 | #define MTU2_TIER_n_TGIEA_SHIFT (0u)
|
|---|
| 258 | #define MTU2_TIER_n_TGIEB_SHIFT (1u)
|
|---|
| 259 | #define MTU2_TIER_n_TCIEV_SHIFT (4u)
|
|---|
| 260 | #define MTU2_TIER_2_TCIEU_SHIFT (5u)
|
|---|
| 261 | #define MTU2_TIER_n_TTGE_SHIFT (7u)
|
|---|
| 262 |
|
|---|
| 263 | #define MTU2_TSR_n_TGFA_SHIFT (0u)
|
|---|
| 264 | #define MTU2_TSR_n_TGFB_SHIFT (1u)
|
|---|
| 265 | #define MTU2_TSR_n_TCFV_SHIFT (4u)
|
|---|
| 266 | #define MTU2_TSR_2_TCFU_SHIFT (5u)
|
|---|
| 267 | #define MTU2_TSR_2_TCFD_SHIFT (7u)
|
|---|
| 268 |
|
|---|
| 269 | #define MTU2_TCNT_n_D_SHIFT (0u)
|
|---|
| 270 |
|
|---|
| 271 | #define MTU2_TGRA_n_D_SHIFT (0u)
|
|---|
| 272 |
|
|---|
| 273 | #define MTU2_TGRB_n_D_SHIFT (0u)
|
|---|
| 274 |
|
|---|
| 275 | #define MTU2_TMDR_3_BFA_SHIFT (4u)
|
|---|
| 276 | #define MTU2_TMDR_3_BFB_SHIFT (5u)
|
|---|
| 277 |
|
|---|
| 278 | #define MTU2_TMDR_4_BFA_SHIFT (4u)
|
|---|
| 279 | #define MTU2_TMDR_4_BFB_SHIFT (5u)
|
|---|
| 280 |
|
|---|
| 281 | #define MTU2_TIORH_3_IOA_SHIFT (0u)
|
|---|
| 282 | #define MTU2_TIORH_3_IOB_SHIFT (4u)
|
|---|
| 283 |
|
|---|
| 284 | #define MTU2_TIORL_3_IOC_SHIFT (0u)
|
|---|
| 285 | #define MTU2_TIORL_3_IOD_SHIFT (4u)
|
|---|
| 286 |
|
|---|
| 287 | #define MTU2_TIORH_4_IOA_SHIFT (0u)
|
|---|
| 288 | #define MTU2_TIORH_4_IOB_SHIFT (4u)
|
|---|
| 289 |
|
|---|
| 290 | #define MTU2_TIORL_4_IOC_SHIFT (0u)
|
|---|
| 291 | #define MTU2_TIORL_4_IOD_SHIFT (4u)
|
|---|
| 292 |
|
|---|
| 293 | #define MTU2_TIER_3_TGIEC_SHIFT (2u)
|
|---|
| 294 | #define MTU2_TIER_3_TGIED_SHIFT (3u)
|
|---|
| 295 |
|
|---|
| 296 | #define MTU2_TIER_4_TGIEC_SHIFT (2u)
|
|---|
| 297 | #define MTU2_TIER_4_TGIED_SHIFT (3u)
|
|---|
| 298 | #define MTU2_TIER_4_TTGE2_SHIFT (6u)
|
|---|
| 299 |
|
|---|
| 300 | #define MTU2_TOER_OE3B_SHIFT (0u)
|
|---|
| 301 | #define MTU2_TOER_OE4A_SHIFT (1u)
|
|---|
| 302 | #define MTU2_TOER_OE4B_SHIFT (2u)
|
|---|
| 303 | #define MTU2_TOER_OE3D_SHIFT (3u)
|
|---|
| 304 | #define MTU2_TOER_OE4C_SHIFT (4u)
|
|---|
| 305 | #define MTU2_TOER_OE4D_SHIFT (5u)
|
|---|
| 306 |
|
|---|
| 307 | #define MTU2_TGCR_UF_SHIFT (0u)
|
|---|
| 308 | #define MTU2_TGCR_VF_SHIFT (1u)
|
|---|
| 309 | #define MTU2_TGCR_WF_SHIFT (2u)
|
|---|
| 310 | #define MTU2_TGCR_FB_SHIFT (3u)
|
|---|
| 311 | #define MTU2_TGCR_P_SHIFT (4u)
|
|---|
| 312 | #define MTU2_TGCR_N_SHIFT (5u)
|
|---|
| 313 | #define MTU2_TGCR_BDC_SHIFT (6u)
|
|---|
| 314 |
|
|---|
| 315 | #define MTU2_TOCR1_OLSP_SHIFT (0u)
|
|---|
| 316 | #define MTU2_TOCR1_OLSN_SHIFT (1u)
|
|---|
| 317 | #define MTU2_TOCR1_TOCS_SHIFT (2u)
|
|---|
| 318 | #define MTU2_TOCR1_TOCL_SHIFT (3u)
|
|---|
| 319 | #define MTU2_TOCR1_PSYE_SHIFT (6u)
|
|---|
| 320 |
|
|---|
| 321 | #define MTU2_TOCR2_OLS1P_SHIFT (0u)
|
|---|
| 322 | #define MTU2_TOCR2_OLS1N_SHIFT (1u)
|
|---|
| 323 | #define MTU2_TOCR2_OLS2P_SHIFT (2u)
|
|---|
| 324 | #define MTU2_TOCR2_OLS2N_SHIFT (3u)
|
|---|
| 325 | #define MTU2_TOCR2_OLS3P_SHIFT (4u)
|
|---|
| 326 | #define MTU2_TOCR2_OLS3N_SHIFT (5u)
|
|---|
| 327 | #define MTU2_TOCR2_BF_SHIFT (6u)
|
|---|
| 328 |
|
|---|
| 329 | #define MTU2_TCDR_D_SHIFT (0u)
|
|---|
| 330 |
|
|---|
| 331 | #define MTU2_TDDR_D_SHIFT (0u)
|
|---|
| 332 |
|
|---|
| 333 | #define MTU2_TCNTS_D_SHIFT (0u)
|
|---|
| 334 |
|
|---|
| 335 | #define MTU2_TCBR_D_SHIFT (0u)
|
|---|
| 336 |
|
|---|
| 337 | #define MTU2_TGRC_3_D_SHIFT (0u)
|
|---|
| 338 |
|
|---|
| 339 | #define MTU2_TGRD_3_D_SHIFT (0u)
|
|---|
| 340 |
|
|---|
| 341 | #define MTU2_TGRC_4_D_SHIFT (0u)
|
|---|
| 342 |
|
|---|
| 343 | #define MTU2_TGRD_4_D_SHIFT (0u)
|
|---|
| 344 |
|
|---|
| 345 | #define MTU2_TSR_3_TGFC_SHIFT (2u)
|
|---|
| 346 | #define MTU2_TSR_3_TGFD_SHIFT (3u)
|
|---|
| 347 | #define MTU2_TSR_3_TCFD_SHIFT (7u)
|
|---|
| 348 |
|
|---|
| 349 | #define MTU2_TSR_4_TGFC_SHIFT (2u)
|
|---|
| 350 | #define MTU2_TSR_4_TGFD_SHIFT (3u)
|
|---|
| 351 | #define MTU2_TSR_4_TCFD_SHIFT (7u)
|
|---|
| 352 |
|
|---|
| 353 | #define MTU2_TITCR_4VCOR_SHIFT (0u)
|
|---|
| 354 | #define MTU2_TITCR_T4VEN_SHIFT (3u)
|
|---|
| 355 | #define MTU2_TITCR_3ACOR_SHIFT (4u)
|
|---|
| 356 | #define MTU2_TITCR_T3AEN_SHIFT (7u)
|
|---|
| 357 |
|
|---|
| 358 | #define MTU2_TITCNT_4VCNT_SHIFT (0u)
|
|---|
| 359 | #define MTU2_TITCNT_3ACNT_SHIFT (4u)
|
|---|
| 360 |
|
|---|
| 361 | #define MTU2_TBTER_BTE_SHIFT (0u)
|
|---|
| 362 |
|
|---|
| 363 | #define MTU2_TDER_TDER_SHIFT (0u)
|
|---|
| 364 |
|
|---|
| 365 | #define MTU2_TOLBR_OLS1P_SHIFT (0u)
|
|---|
| 366 | #define MTU2_TOLBR_OLS1N_SHIFT (1u)
|
|---|
| 367 | #define MTU2_TOLBR_OLS2P_SHIFT (2u)
|
|---|
| 368 | #define MTU2_TOLBR_OLS2N_SHIFT (3u)
|
|---|
| 369 | #define MTU2_TOLBR_OLS3P_SHIFT (4u)
|
|---|
| 370 | #define MTU2_TOLBR_OLS3N_SHIFT (5u)
|
|---|
| 371 |
|
|---|
| 372 | #define MTU2_TBTM_3_TTSA_SHIFT (0u)
|
|---|
| 373 | #define MTU2_TBTM_3_TTSB_SHIFT (1u)
|
|---|
| 374 |
|
|---|
| 375 | #define MTU2_TBTM_4_TTSA_SHIFT (0u)
|
|---|
| 376 | #define MTU2_TBTM_4_TTSB_SHIFT (1u)
|
|---|
| 377 |
|
|---|
| 378 | #define MTU2_TADCR_ITB4VE_SHIFT (0u)
|
|---|
| 379 | #define MTU2_TADCR_ITB3AE_SHIFT (1u)
|
|---|
| 380 | #define MTU2_TADCR_ITA4VE_SHIFT (2u)
|
|---|
| 381 | #define MTU2_TADCR_ITA3AE_SHIFT (3u)
|
|---|
| 382 | #define MTU2_TADCR_DT4BE_SHIFT (4u)
|
|---|
| 383 | #define MTU2_TADCR_UT4BE_SHIFT (5u)
|
|---|
| 384 | #define MTU2_TADCR_DT4AE_SHIFT (6u)
|
|---|
| 385 | #define MTU2_TADCR_UT4AE_SHIFT (7u)
|
|---|
| 386 | #define MTU2_TADCR_BF_SHIFT (14u)
|
|---|
| 387 |
|
|---|
| 388 | #define MTU2_TADCORA_4_D_SHIFT (0u)
|
|---|
| 389 |
|
|---|
| 390 | #define MTU2_TADCORB_4_D_SHIFT (0u)
|
|---|
| 391 |
|
|---|
| 392 | #define MTU2_TADCOBRA_4_D_SHIFT (0u)
|
|---|
| 393 |
|
|---|
| 394 | #define MTU2_TADCOBRB_4_D_SHIFT (0u)
|
|---|
| 395 |
|
|---|
| 396 | #define MTU2_TWCR_WRE_SHIFT (0u)
|
|---|
| 397 | #define MTU2_TWCR_CCE_SHIFT (7u)
|
|---|
| 398 |
|
|---|
| 399 | #define MTU2_TSTR_CST0_SHIFT (0u)
|
|---|
| 400 | #define MTU2_TSTR_CST1_SHIFT (1u)
|
|---|
| 401 | #define MTU2_TSTR_CST2_SHIFT (2u)
|
|---|
| 402 | #define MTU2_TSTR_CST3_SHIFT (6u)
|
|---|
| 403 | #define MTU2_TSTR_CST4_SHIFT (7u)
|
|---|
| 404 |
|
|---|
| 405 | #define MTU2_TSYR_SYNC0_SHIFT (0u)
|
|---|
| 406 | #define MTU2_TSYR_SYNC1_SHIFT (1u)
|
|---|
| 407 | #define MTU2_TSYR_SYNC2_SHIFT (2u)
|
|---|
| 408 | #define MTU2_TSYR_SYNC3_SHIFT (6u)
|
|---|
| 409 | #define MTU2_TSYR_SYNC4_SHIFT (7u)
|
|---|
| 410 |
|
|---|
| 411 | #define MTU2_TRWER_RWE_SHIFT (0u)
|
|---|
| 412 |
|
|---|
| 413 | #define MTU2_TMDR_0_BFA_SHIFT (4u)
|
|---|
| 414 | #define MTU2_TMDR_0_BFB_SHIFT (5u)
|
|---|
| 415 | #define MTU2_TMDR_0_BFE_SHIFT (6u)
|
|---|
| 416 |
|
|---|
| 417 | #define MTU2_TIORH_0_IOA_SHIFT (0u)
|
|---|
| 418 | #define MTU2_TIORH_0_IOB_SHIFT (4u)
|
|---|
| 419 |
|
|---|
| 420 | #define MTU2_TIORL_0_IOC_SHIFT (0u)
|
|---|
| 421 | #define MTU2_TIORL_0_IOD_SHIFT (4u)
|
|---|
| 422 |
|
|---|
| 423 | #define MTU2_TIER_0_TGIEC_SHIFT (2u)
|
|---|
| 424 | #define MTU2_TIER_0_TGIED_SHIFT (3u)
|
|---|
| 425 |
|
|---|
| 426 | #define MTU2_TSR_0_TGFC_SHIFT (2u)
|
|---|
| 427 | #define MTU2_TSR_0_TGFD_SHIFT (3u)
|
|---|
| 428 |
|
|---|
| 429 | #define MTU2_TGRC_0_D_SHIFT (0u)
|
|---|
| 430 |
|
|---|
| 431 | #define MTU2_TGRD_0_D_SHIFT (0u)
|
|---|
| 432 |
|
|---|
| 433 | #define MTU2_TGRE_0_D_SHIFT (0u)
|
|---|
| 434 |
|
|---|
| 435 | #define MTU2_TGRF_0_D_SHIFT (0u)
|
|---|
| 436 |
|
|---|
| 437 | #define MTU2_TIER2_0_TGIEE_SHIFT (0u)
|
|---|
| 438 | #define MTU2_TIER2_0_TGIEF_SHIFT (1u)
|
|---|
| 439 |
|
|---|
| 440 | #define MTU2_TSR2_0_TGFE_SHIFT (0u)
|
|---|
| 441 | #define MTU2_TSR2_0_TGFF_SHIFT (1u)
|
|---|
| 442 |
|
|---|
| 443 | #define MTU2_TBTM_0_TTSA_SHIFT (0u)
|
|---|
| 444 | #define MTU2_TBTM_0_TTSB_SHIFT (1u)
|
|---|
| 445 | #define MTU2_TBTM_0_TTSE_SHIFT (2u)
|
|---|
| 446 |
|
|---|
| 447 | #define MTU2_TIOR_1_IOA_SHIFT (0u)
|
|---|
| 448 | #define MTU2_TIOR_1_IOB_SHIFT (4u)
|
|---|
| 449 |
|
|---|
| 450 | #define MTU2_TIER_1_TCIEU_SHIFT (5u)
|
|---|
| 451 |
|
|---|
| 452 | #define MTU2_TSR_1_TCFU_SHIFT (5u)
|
|---|
| 453 | #define MTU2_TSR_1_TCFD_SHIFT (7u)
|
|---|
| 454 |
|
|---|
| 455 | #define MTU2_TICCR_I1AE_SHIFT (0u)
|
|---|
| 456 | #define MTU2_TICCR_I1BE_SHIFT (1u)
|
|---|
| 457 | #define MTU2_TICCR_I2AE_SHIFT (2u)
|
|---|
| 458 | #define MTU2_TICCR_I2BE_SHIFT (3u)
|
|---|
| 459 |
|
|---|
| 460 |
|
|---|
| 461 | #endif /* MTU2_IOBITMASK_H */
|
|---|
| 462 | /* End of File */
|
|---|
![(please configure the [header_logo] section in trac.ini)](/trac_user/contrib/chrome/site/your_project_logo.png){kind=logo}
