[352] | 1 | /**************************************************************************//**
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| 2 | * @file gic.h
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| 3 | * @brief Implementation of GIC functions declared in CMSIS Cortex-A9 Core Peripheral Access Layer Header File
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| 4 | * @version
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| 5 | * @date 29 August 2013
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| 6 | *
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| 7 | * @note
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| 8 | *
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| 9 | ******************************************************************************/
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| 10 | /* Copyright (c) 2011 - 2013 ARM LIMITED
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| 11 |
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| 12 | All rights reserved.
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| 13 | Redistribution and use in source and binary forms, with or without
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| 14 | modification, are permitted provided that the following conditions are met:
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| 15 | - Redistributions of source code must retain the above copyright
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| 16 | notice, this list of conditions and the following disclaimer.
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| 17 | - Redistributions in binary form must reproduce the above copyright
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| 18 | notice, this list of conditions and the following disclaimer in the
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| 19 | documentation and/or other materials provided with the distribution.
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| 20 | - Neither the name of ARM nor the names of its contributors may be used
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| 21 | to endorse or promote products derived from this software without
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| 22 | specific prior written permission.
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| 23 | *
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| 24 | THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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| 25 | AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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| 26 | IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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| 27 | ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
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| 28 | LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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| 29 | CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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| 30 | SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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| 31 | INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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| 32 | CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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| 33 | ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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| 34 | POSSIBILITY OF SUCH DAMAGE.
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| 35 | ---------------------------------------------------------------------------*/
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| 36 |
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| 37 | #ifndef GIC_H_
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| 38 | #define GIC_H_
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| 39 |
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| 40 | /* IO definitions (access restrictions to peripheral registers) */
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| 41 | /**
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| 42 | */
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| 43 | #ifdef __cplusplus
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| 44 | #define __I volatile /*!< Defines 'read only' permissions */
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| 45 | #else
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| 46 | #define __I volatile const /*!< Defines 'read only' permissions */
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| 47 | #endif
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| 48 | #define __O volatile /*!< Defines 'write only' permissions */
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| 49 | #define __IO volatile /*!< Defines 'read / write' permissions */
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| 50 |
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| 51 | /** \brief Structure type to access the Generic Interrupt Controller Distributor (GICD)
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| 52 | */
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| 53 | typedef struct
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| 54 | {
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| 55 | __IO uint32_t ICDDCR;
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| 56 | __I uint32_t ICDICTR;
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| 57 | __I uint32_t ICDIIDR;
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| 58 | uint32_t RESERVED0[29];
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| 59 | __IO uint32_t ICDISR[32];
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| 60 | __IO uint32_t ICDISER[32];
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| 61 | __IO uint32_t ICDICER[32];
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| 62 | __IO uint32_t ICDISPR[32];
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| 63 | __IO uint32_t ICDICPR[32];
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| 64 | __I uint32_t ICDABR[32];
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| 65 | uint32_t RESERVED1[32];
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| 66 | __IO uint32_t ICDIPR[256];
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| 67 | __IO uint32_t ICDIPTR[256];
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| 68 | __IO uint32_t ICDICFR[64];
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| 69 | uint32_t RESERVED2[128];
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| 70 | __IO uint32_t ICDSGIR;
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| 71 | } GICDistributor_Type;
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| 72 |
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| 73 | /** \brief Structure type to access the Controller Interface (GICC)
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| 74 | */
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| 75 | typedef struct
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| 76 | {
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| 77 | __IO uint32_t ICCICR; // +0x000 - RW - CPU Interface Control Register
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| 78 | __IO uint32_t ICCPMR; // +0x004 - RW - Interrupt Priority Mask Register
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| 79 | __IO uint32_t ICCBPR; // +0x008 - RW - Binary Point Register
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| 80 | __I uint32_t ICCIAR; // +0x00C - RO - Interrupt Acknowledge Register
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| 81 | __IO uint32_t ICCEOIR; // +0x010 - WO - End of Interrupt Register
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| 82 | __I uint32_t ICCRPR; // +0x014 - RO - Running Priority Register
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| 83 | __I uint32_t ICCHPIR; // +0x018 - RO - Highest Pending Interrupt Register
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| 84 | __IO uint32_t ICCABPR; // +0x01C - RW - Aliased Binary Point Register
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| 85 |
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| 86 | uint32_t RESERVED[55];
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| 87 |
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| 88 | __I uint32_t ICCIIDR; // +0x0FC - RO - CPU Interface Identification Register
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| 89 | } GICInterface_Type;
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| 90 |
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| 91 | /*@} end of GICD */
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| 92 |
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| 93 | /* ########################## GIC functions #################################### */
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| 94 | /** \brief Functions that manage interrupts via the GIC.
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| 95 | @{
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| 96 | */
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| 97 |
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| 98 | /** \brief Enable DistributorGICInterface->ICCICR |= 1; //enable interface
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| 99 |
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| 100 | Enables the forwarding of pending interrupts to the CPU interfaces.
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| 101 |
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| 102 | */
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| 103 | void GIC_EnableDistributor(void);
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| 104 |
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| 105 | /** \brief Disable Distributor
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| 106 |
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| 107 | Disables the forwarding of pending interrupts to the CPU interfaces.
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| 108 |
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| 109 | */
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| 110 | void GIC_DisableDistributor(void);
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| 111 |
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| 112 | /** \brief Provides information about the configuration of the GIC.
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| 113 | Provides information about the configuration of the GIC.
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| 114 | - whether the GIC implements the Security Extensions
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| 115 | - the maximum number of interrupt IDs that the GIC supports
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| 116 | - the number of CPU interfaces implemented
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| 117 | - if the GIC implements the Security Extensions, the maximum number of implemented Lockable Shared Peripheral Interrupts (LSPIs).
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| 118 |
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| 119 | \return Distributor Information.
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| 120 | */
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| 121 | uint32_t GIC_DistributorInfo(void);
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| 122 |
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| 123 | /** \brief Distributor Implementer Identification Register.
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| 124 |
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| 125 | Distributor Implementer Identification Register
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| 126 |
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| 127 | \return Implementer Information.
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| 128 | */
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| 129 | uint32_t GIC_DistributorImplementer(void);
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| 130 |
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| 131 | /** \brief Set list of processors that the interrupt is sent to if it is asserted.
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| 132 |
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| 133 | The ICDIPTRs provide an 8-bit CPU targets field for each interrupt supported by the GIC.
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| 134 | This field stores the list of processors that the interrupt is sent to if it is asserted.
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| 135 |
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| 136 | \param [in] IRQn Interrupt number.
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| 137 | \param [in] target CPU target
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| 138 | */
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| 139 | void GIC_SetTarget(IRQn_Type IRQn, uint32_t cpu_target);
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| 140 |
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| 141 | /** \brief Get list of processors that the interrupt is sent to if it is asserted.
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| 142 |
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| 143 | The ICDIPTRs provide an 8-bit CPU targets field for each interrupt supported by the GIC.
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| 144 | This field stores the list of processors that the interrupt is sent to if it is asserted.
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| 145 |
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| 146 | \param [in] IRQn Interrupt number.
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| 147 | \param [in] target CPU target
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| 148 | */
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| 149 | uint32_t GIC_GetTarget(IRQn_Type IRQn);
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| 150 |
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| 151 | /** \brief Enable Interface
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| 152 |
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| 153 | Enables the signalling of interrupts to the target processors.
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| 154 |
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| 155 | */
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| 156 | void GIC_EnableInterface(void);
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| 157 |
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| 158 | /** \brief Disable Interface
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| 159 |
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| 160 | Disables the signalling of interrupts to the target processors.
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| 161 |
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| 162 | */
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| 163 | void GIC_DisableInterface(void);
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| 164 |
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| 165 | /** \brief Acknowledge Interrupt
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| 166 |
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| 167 | The function acknowledges the highest priority pending interrupt and returns its IRQ number.
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| 168 |
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| 169 | \return Interrupt number
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| 170 | */
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| 171 | IRQn_Type GIC_AcknowledgePending(void);
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| 172 |
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| 173 | /** \brief End Interrupt
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| 174 |
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| 175 | The function writes the end of interrupt register, indicating that handling of the interrupt is complete.
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| 176 |
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| 177 | \param [in] IRQn Interrupt number.
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| 178 | */
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| 179 | void GIC_EndInterrupt(IRQn_Type IRQn);
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| 180 |
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| 181 |
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| 182 | /** \brief Enable Interrupt
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| 183 |
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| 184 | Set-enable bit for each interrupt supported by the GIC.
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| 185 |
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| 186 | \param [in] IRQn External interrupt number.
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| 187 | */
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| 188 | void GIC_EnableIRQ(IRQn_Type IRQn);
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| 189 |
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| 190 | /** \brief Disable Interrupt
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| 191 |
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| 192 | Clear-enable bit for each interrupt supported by the GIC.
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| 193 |
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| 194 | \param [in] IRQn Number of the external interrupt to disable
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| 195 | */
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| 196 | void GIC_DisableIRQ(IRQn_Type IRQn);
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| 197 |
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| 198 | /** \brief Set Pending Interrupt
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| 199 |
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| 200 | Set-pending bit for each interrupt supported by the GIC.
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| 201 |
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| 202 | \param [in] IRQn Interrupt number.
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| 203 | */
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| 204 | void GIC_SetPendingIRQ(IRQn_Type IRQn);
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| 205 |
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| 206 | /** \brief Clear Pending Interrupt
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| 207 |
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| 208 | Clear-pending bit for each interrupt supported by the GIC
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| 209 |
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| 210 | \param [in] IRQn Number of the interrupt for clear pending
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| 211 | */
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| 212 | void GIC_ClearPendingIRQ(IRQn_Type IRQn);
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| 213 |
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| 214 | /** \brief Int_config field for each interrupt supported by the GIC.
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| 215 |
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| 216 | This field identifies whether the corresponding interrupt is:
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| 217 | (1) edge-triggered or (0) level-sensitive
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| 218 | (1) 1-N model or (0) N-N model
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| 219 |
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| 220 | \param [in] IRQn Interrupt number.
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| 221 | \param [in] edge_level (1) edge-triggered or (0) level-sensitive
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| 222 | \param [in] model (1) 1-N model or (0) N-N model
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| 223 | */
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| 224 | void GIC_SetLevelModel(IRQn_Type IRQn, int8_t edge_level, int8_t model);
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| 225 |
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| 226 |
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| 227 | /** \brief Set Interrupt Priority
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| 228 |
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| 229 | The function sets the priority of an interrupt.
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| 230 |
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| 231 | \param [in] IRQn Interrupt number.
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| 232 | \param [in] priority Priority to set.
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| 233 | */
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| 234 | void GIC_SetPriority(IRQn_Type IRQn, uint32_t priority);
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| 235 |
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| 236 | /** \brief Get Interrupt Priority
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| 237 |
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| 238 | The function reads the priority of an interrupt.
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| 239 |
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| 240 | \param [in] IRQn Interrupt number.
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| 241 | \return Interrupt Priority.
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| 242 | */
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| 243 | uint32_t GIC_GetPriority(IRQn_Type IRQn);
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| 244 |
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| 245 | /** \brief CPU Interface Priority Mask Register
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| 246 |
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| 247 | The priority mask level for the CPU interface. If the priority of an interrupt is higher than the
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| 248 | value indicated by this field, the interface signals the interrupt to the processor.
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| 249 |
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| 250 | \param [in] Mask.
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| 251 | */
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| 252 | void GIC_InterfacePriorityMask(uint32_t priority);
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| 253 |
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| 254 | /** \brief Set the binary point.
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| 255 |
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| 256 | Set the point at which the priority value fields split into two parts, the group priority field and the subpriority field.
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| 257 |
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| 258 | \param [in] Mask.
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| 259 | */
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| 260 | void GIC_SetBinaryPoint(uint32_t binary_point);
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| 261 |
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| 262 | /** \brief Get the binary point.
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| 263 |
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| 264 | Get the point at which the priority value fields split into two parts, the group priority field and the subpriority field.
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| 265 |
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| 266 | \return Binary point.
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| 267 | */
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| 268 | uint32_t GIC_GetBinaryPoint(uint32_t binary_point);
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| 269 |
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| 270 | /** \brief Get Interrupt state.
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| 271 |
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| 272 | Get the interrupt state, whether pending and/or active
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| 273 |
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| 274 | \return 0 - inactive, 1 - pending, 2 - active, 3 - pending and active
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| 275 | */
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| 276 | uint32_t GIC_GetIRQStatus(IRQn_Type IRQn);
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| 277 |
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| 278 | /** \brief Send Software Generated interrupt
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| 279 |
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| 280 | Provides an interrupt priority filter. Only interrupts with higher priority than the value in this register can be signalled to the processor.
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| 281 | GIC_InterfacePriorityMask
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| 282 | \param [in] IRQn The Interrupt ID of the SGI.
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| 283 | \param [in] target_list CPUTargetList
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| 284 | \param [in] filter_list TargetListFilter
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| 285 | */
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| 286 | void GIC_SendSGI(IRQn_Type IRQn, uint32_t target_list, uint32_t filter_list);
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| 287 |
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| 288 | /** \brief API call to initialise the interrupt distributor
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| 289 |
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| 290 | API call to initialise the interrupt distributor
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| 291 |
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| 292 | */
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| 293 | void GIC_DistInit(void);
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| 294 |
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| 295 | /** \brief API call to initialise the CPU interface
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| 296 |
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| 297 | API call to initialise the CPU interface
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| 298 |
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| 299 | */
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| 300 | void GIC_CPUInterfaceInit(void);
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| 301 |
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| 302 | /** \brief API call to set the Interrupt Configuration Registers
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| 303 |
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| 304 | API call to initialise the Interrupt Configuration Registers
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| 305 |
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| 306 | */
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| 307 | void GIC_SetICDICFR (const uint32_t *ICDICFRn);
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| 308 |
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| 309 | /** \brief API call to Enable the GIC
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| 310 |
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| 311 | API call to Enable the GIC
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| 312 |
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| 313 | */
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| 314 | void GIC_Enable(void);
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| 315 |
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| 316 | #endif /* GIC_H_ */
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