source: asp3_tinet_ecnl_arm/trunk/asp3_dcre/mbed/targets/TARGET_RENESAS/TARGET_RZA1XX/us_ticker.c@ 374

Last change on this file since 374 was 374, checked in by coas-nagasima, 5 years ago

mbed関連を更新
シリアルドライバをmbedのHALを使うよう変更
ファイルディスクリプタの処理を更新

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File size: 2.4 KB
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1/* mbed Microcontroller Library
2 * Copyright (c) 2006-2013 ARM Limited
3 *
4 * Licensed under the Apache License, Version 2.0 (the "License");
5 * you may not use this file except in compliance with the License.
6 * You may obtain a copy of the License at
7 *
8 * http://www.apache.org/licenses/LICENSE-2.0
9 *
10 * Unless required by applicable law or agreed to in writing, software
11 * distributed under the License is distributed on an "AS IS" BASIS,
12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
13 * See the License for the specific language governing permissions and
14 * limitations under the License.
15 */
16#include "us_ticker_api.h"
17#include "mbed_drv_cfg.h"
18
19#define SHIFT_NUM 5 /* P0/32 */
20
21static int us_ticker_inited = 0;
22
23void us_ticker_init(void)
24{
25 GIC_DisableIRQ(OSTMI1TINT_IRQn);
26 GIC_ClearPendingIRQ(OSTMI1TINT_IRQn);
27
28 /* Power Control for Peripherals */
29 CPGSTBCR5 &= ~(CPG_STBCR5_BIT_MSTP50); /* enable OSTM1 clock */
30
31 if (us_ticker_inited) return;
32 us_ticker_inited = 1;
33
34 // timer settings
35 OSTM1TT = 0x01; /* Stop the counter and clears the OSTM1TE bit. */
36 OSTM1CTL = 0x02; /* Free running timer mode. Interrupt disabled when star counter */
37
38 OSTM1TS = 0x1; /* Start the counter and sets the OSTM0TE bit. */
39
40 // INTC settings
41 InterruptHandlerRegister(OSTMI1TINT_IRQn, (void (*)(uint32_t))us_ticker_irq_handler);
42 GIC_SetPriority(OSTMI1TINT_IRQn, 5);
43 GIC_SetConfiguration(OSTMI1TINT_IRQn, 3);
44}
45
46void us_ticker_free(void)
47{
48 GIC_DisableIRQ(OSTMI1TINT_IRQn);
49 GIC_ClearPendingIRQ(OSTMI1TINT_IRQn);
50
51 /* Power Control for Peripherals */
52 CPGSTBCR5 |= (CPG_STBCR5_BIT_MSTP50); /* disable OSTM1 clock */
53}
54
55uint32_t us_ticker_read()
56{
57 return (uint32_t)(OSTM1CNT >> SHIFT_NUM);
58}
59
60void us_ticker_set_interrupt(timestamp_t timestamp)
61{
62 OSTM1CMP = (uint32_t)(timestamp << SHIFT_NUM);
63 GIC_EnableIRQ(OSTMI1TINT_IRQn);
64}
65
66void us_ticker_fire_interrupt(void)
67{
68 GIC_SetPendingIRQ(OSTMI1TINT_IRQn);
69 GIC_EnableIRQ(OSTMI1TINT_IRQn);
70}
71
72void us_ticker_disable_interrupt(void)
73{
74 GIC_DisableIRQ(OSTMI1TINT_IRQn);
75}
76
77void us_ticker_clear_interrupt(void)
78{
79 GIC_ClearPendingIRQ(OSTMI1TINT_IRQn);
80}
81
82const ticker_info_t* us_ticker_get_info()
83{
84 static const ticker_info_t info = {
85 (uint32_t)((float)RENESAS_RZ_A1_P0_CLK / (float)(1 << SHIFT_NUM) + 0.5f),
86 (32 - SHIFT_NUM)
87 };
88 return &info;
89}
90
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