source: asp3_tinet_ecnl_arm/trunk/asp3_dcre/mbed/targets/TARGET_RENESAS/TARGET_RZA1XX/i2c_api.c@ 374

Last change on this file since 374 was 374, checked in by coas-nagasima, 5 years ago

mbed関連を更新
シリアルドライバをmbedのHALを使うよう変更
ファイルディスクリプタの処理を更新
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1/* mbed Microcontroller Library
2 * Copyright (c) 2006-2013 ARM Limited
3 *
4 * Licensed under the Apache License, Version 2.0 (the "License");
5 * you may not use this file except in compliance with the License.
6 * You may obtain a copy of the License at
7 *
8 * http://www.apache.org/licenses/LICENSE-2.0
9 *
10 * Unless required by applicable law or agreed to in writing, software
11 * distributed under the License is distributed on an "AS IS" BASIS,
12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
13 * See the License for the specific language governing permissions and
14 * limitations under the License.
15 */
16#include "mbed_assert.h"
17#include "dma_api.h"
18#include "i2c_api.h"
19#include "cmsis.h"
20#include "PeripheralPins.h"
21#include "r_typedefs.h"
22
23#include "iodefine.h"
24#include "RZ_A1_Init.h"
25
26volatile struct st_riic *RIIC[] = RIIC_ADDRESS_LIST;
27
28#define REG(N) \
29 RIIC[obj->i2c.i2c]->RIICn##N
30
31/* RIICnCR1 */
32#define CR1_RST (1 << 6)
33#define CR1_ICE (1 << 7)
34
35/* RIICnCR2 */
36#define CR2_ST (1 << 1)
37#define CR2_RS (1 << 2)
38#define CR2_SP (1 << 3)
39#define CR2_TRS (1 << 5)
40#define CR2_BBSY (1 << 7)
41
42/* RIICnMR3 */
43#define MR3_ACKBT (1 << 3)
44#define MR3_ACKWP (1 << 4)
45#define MR3_WAIT (1 << 6)
46
47/* RIICnSER */
48#define SER_SAR0E (1 << 0)
49
50/* RIICnSR1 */
51#define SR1_AAS0 (1 << 0)
52
53/* RIICnSR2 */
54#define SR2_START (1 << 2)
55#define SR2_STOP (1 << 3)
56#define SR2_NACKF (1 << 4)
57#define SR2_RDRF (1 << 5)
58#define SR2_TEND (1 << 6)
59#define SR2_TDRE (1 << 7)
60
61#define WAIT_TIMEOUT (3600000) /* Loop counter : Time-out is about 1s. By 3600000 loops, measured value is 969ms. */
62
63static inline int i2c_status(i2c_t *obj) {
64 return REG(SR2.UINT8[0]);
65}
66
67static void i2c_reg_reset(i2c_t *obj) {
68 /* full reset */
69 REG(CR1.UINT8[0]) &= ~CR1_ICE; // CR1.ICE off
70 REG(CR1.UINT8[0]) |= CR1_RST; // CR1.IICRST on
71 REG(CR1.UINT8[0]) |= CR1_ICE; // CR1.ICE on
72
73 REG(MR1.UINT8[0]) = 0x08; // P_phi /x 9bit (including Ack)
74 REG(SER.UINT8[0]) = 0x00; // no slave addr enabled
75
76 /* set frequency */
77 REG(MR1.UINT8[0]) |= obj->i2c.pclk_bit;
78 REG(BRL.UINT8[0]) = obj->i2c.width_low;
79 REG(BRH.UINT8[0]) = obj->i2c.width_hi;
80
81 REG(MR2.UINT8[0]) = 0x07;
82 REG(MR3.UINT8[0]) = 0x00;
83
84 REG(FER.UINT8[0]) = 0x72; // SCLE, NFE enabled, TMOT
85 REG(IER.UINT8[0]) = 0x00; // no interrupt
86
87 REG(CR1.UINT32) &= ~CR1_RST; // CR1.IICRST negate reset
88}
89
90static inline int i2c_wait_RDRF(i2c_t *obj) {
91 int timeout = 0;
92
93 /* There is no timeout, but the upper limit value is set to avoid an infinite loop. */
94 while ((i2c_status(obj) & SR2_RDRF) == 0) {
95 timeout ++;
96 if (timeout >= WAIT_TIMEOUT) {
97 return -1;
98 }
99 }
100
101 return 0;
102}
103
104static int i2c_wait_TDRE(i2c_t *obj) {
105 int timeout = 0;
106
107 /* There is no timeout, but the upper limit value is set to avoid an infinite loop. */
108 while ((i2c_status(obj) & SR2_TDRE) == 0) {
109 timeout ++;
110 if (timeout >= WAIT_TIMEOUT) {
111 return -1;
112 }
113 }
114
115 return 0;
116}
117
118static int i2c_wait_TEND(i2c_t *obj) {
119 int timeout = 0;
120
121 /* There is no timeout, but the upper limit value is set to avoid an infinite loop. */
122 while ((i2c_status(obj) & SR2_TEND) == 0) {
123 timeout ++;
124 if (timeout >= WAIT_TIMEOUT) {
125 return -1;
126 }
127 }
128
129 return 0;
130}
131
132
133static int i2c_wait_START(i2c_t *obj) {
134 int timeout = 0;
135
136 /* There is no timeout, but the upper limit value is set to avoid an infinite loop. */
137 while ((i2c_status(obj) & SR2_START) == 0) {
138 timeout ++;
139 if (timeout >= WAIT_TIMEOUT) {
140 return -1;
141 }
142 }
143
144 return 0;
145}
146
147static int i2c_wait_STOP(i2c_t *obj) {
148 int timeout = 0;
149
150 /* There is no timeout, but the upper limit value is set to avoid an infinite loop. */
151 while ((i2c_status(obj) & SR2_STOP) == 0) {
152 timeout ++;
153 if (timeout >= WAIT_TIMEOUT) {
154 return -1;
155 }
156 }
157
158 return 0;
159}
160
161static int i2c_set_STOP(i2c_t *obj) {
162 /* SR2.STOP = 0 */
163 REG(SR2.UINT32) &= ~SR2_STOP;
164 /* Stop condition */
165 REG(CR2.UINT32) |= CR2_SP;
166
167 return 0;
168}
169
170static void i2c_set_SR2_NACKF_STOP(i2c_t *obj) {
171 /* SR2.NACKF = 0 */
172 REG(SR2.UINT32) &= ~SR2_NACKF;
173 /* SR2.STOP = 0 */
174 REG(SR2.UINT32) &= ~SR2_STOP;
175}
176
177static void i2c_set_MR3_NACK(i2c_t *obj) {
178 /* send a NOT ACK */
179 REG(MR3.UINT32) |= MR3_ACKWP;
180 REG(MR3.UINT32) |= MR3_ACKBT;
181 REG(MR3.UINT32) &= ~MR3_ACKWP;
182}
183
184static void i2c_set_MR3_ACK(i2c_t *obj) {
185 /* send a ACK */
186 REG(MR3.UINT32) |= MR3_ACKWP;
187 REG(MR3.UINT32) &= ~MR3_ACKBT;
188 REG(MR3.UINT32) &= ~MR3_ACKWP;
189}
190
191static inline void i2c_power_enable(i2c_t *obj) {
192 volatile uint8_t dummy;
193 switch ((int)obj->i2c.i2c) {
194 case I2C_0:
195 CPGSTBCR9 &= ~(0x80);
196 break;
197 case I2C_1:
198 CPGSTBCR9 &= ~(0x40);
199 break;
200 case I2C_2:
201 CPGSTBCR9 &= ~(0x20);
202 break;
203 case I2C_3:
204 CPGSTBCR9 &= ~(0x10);
205 break;
206 }
207 dummy = CPGSTBCR9;
208 (void)dummy;
209}
210
211void i2c_init(i2c_t *obj, PinName sda, PinName scl) {
212 /* determine the I2C to use */
213 I2CName i2c_sda = (I2CName)pinmap_peripheral(sda, PinMap_I2C_SDA);
214 I2CName i2c_scl = (I2CName)pinmap_peripheral(scl, PinMap_I2C_SCL);
215 obj->i2c.i2c = pinmap_merge(i2c_sda, i2c_scl);
216 MBED_ASSERT((int)obj->i2c.i2c != NC);
217
218 /* enable power */
219 i2c_power_enable(obj);
220
221 /* set default frequency at 100k */
222 i2c_frequency(obj, 100000);
223
224 pinmap_pinout(sda, PinMap_I2C_SDA);
225 pinmap_pinout(scl, PinMap_I2C_SCL);
226
227 obj->i2c.last_stop_flag = 1;
228}
229
230inline int i2c_start(i2c_t *obj) {
231 int timeout = 0;
232
233 while ((REG(CR2.UINT32) & CR2_BBSY) != 0) {
234 timeout ++;
235 if (timeout >= obj->i2c.bbsy_wait_cnt) {
236 break;
237 }
238 }
239 /* Start Condition */
240 REG(CR2.UINT8[0]) |= CR2_ST;
241
242 return 0;
243}
244
245static inline int i2c_restart(i2c_t *obj) {
246 /* SR2.START = 0 */
247 REG(SR2.UINT32) &= ~SR2_START;
248 /* ReStart condition */
249 REG(CR2.UINT32) |= CR2_RS;
250
251 return 0;
252}
253
254inline int i2c_stop(i2c_t *obj) {
255 (void)i2c_set_STOP(obj);
256 (void)i2c_wait_STOP(obj);
257 i2c_set_SR2_NACKF_STOP(obj);
258
259 return 0;
260}
261
262static void i2c_set_err_noslave(i2c_t *obj) {
263 (void)i2c_set_STOP(obj);
264 (void)i2c_wait_STOP(obj);
265 i2c_set_SR2_NACKF_STOP(obj);
266 obj->i2c.last_stop_flag = 1;
267}
268
269static inline int i2c_do_write(i2c_t *obj, int value) {
270 int timeout = 0;
271
272 /* There is no timeout, but the upper limit value is set to avoid an infinite loop. */
273 while ((i2c_status(obj) & SR2_TDRE) == 0) {
274 timeout ++;
275 if (timeout >= WAIT_TIMEOUT) {
276 return -1;
277 }
278 }
279 /* write the data */
280 REG(DRT.UINT32) = value;
281
282 return 0;
283}
284
285static inline int i2c_read_address_write(i2c_t *obj, int value) {
286 int status;
287
288 status = i2c_wait_TDRE(obj);
289 if (status == 0) {
290 /* write the data */
291 REG(DRT.UINT32) = value;
292 }
293
294 return status;
295
296}
297
298static inline int i2c_do_read(i2c_t *obj, int last) {
299 if (last == 2) {
300 /* this time is befor last byte read */
301 /* Set MR3 WAIT bit is 1 */;
302 REG(MR3.UINT32) |= MR3_WAIT;
303 } else if (last == 1) {
304 i2c_set_MR3_NACK(obj);
305 } else {
306 i2c_set_MR3_ACK(obj);
307 }
308
309 /* return the data */
310 return (REG(DRR.UINT32) & 0xFF);
311}
312
313void i2c_frequency(i2c_t *obj, int hz) {
314 float64_t pclk_val;
315 float64_t wait_utime;
316 volatile float64_t bps;
317 volatile float64_t L_time; /* H Width period */
318 volatile float64_t H_time; /* L Width period */
319 uint32_t tmp_L_width;
320 uint32_t tmp_H_width;
321 uint32_t remainder;
322 uint32_t wk_cks = 0;
323
324 /* set PCLK */
325 if (false == RZ_A1_IsClockMode0()) {
326 pclk_val = (float64_t)CM1_RENESAS_RZ_A1_P0_CLK;
327 } else {
328 pclk_val = (float64_t)CM0_RENESAS_RZ_A1_P0_CLK;
329 }
330
331 /* Min 10kHz, Max 400kHz */
332 if (hz < 10000) {
333 bps = 10000;
334 } else if (hz > 400000) {
335 bps = 400000;
336 } else {
337 bps = (float64_t)hz;
338 }
339
340 /* Calculation L width time */
341 L_time = (1 / (2 * bps)); /* Harf period of frequency */
342 H_time = L_time;
343
344 /* Check I2C mode of Speed */
345 if (bps > 100000) {
346 /* Fast-mode */
347 L_time -= 102E-9; /* Falling time of SCL clock. */
348 H_time -= 138E-9; /* Rising time of SCL clock. */
349 /* Check L wideth */
350 if (L_time < 1.3E-6) {
351 /* Wnen L width less than 1.3us */
352 /* Subtract Rise up and down time for SCL from H/L width */
353 L_time = 1.3E-6;
354 H_time = (1 / bps) - L_time - 138E-9 - 102E-9;
355 }
356 }
357
358 tmp_L_width = (uint32_t)(L_time * pclk_val * 10);
359 tmp_L_width >>= 1;
360 wk_cks++;
361 while (tmp_L_width >= 341) {
362 tmp_L_width >>= 1;
363 wk_cks++;
364 }
365 remainder = tmp_L_width % 10;
366 tmp_L_width = ((tmp_L_width + 9) / 10) - 3; /* carry */
367
368 tmp_H_width = (uint32_t)(H_time * pclk_val * 10);
369 tmp_H_width >>= wk_cks;
370 if (remainder == 0) {
371 tmp_H_width = ((tmp_H_width + 9) / 10) - 3; /* carry */
372 } else {
373 remainder += tmp_H_width % 10;
374 tmp_H_width = (tmp_H_width / 10) - 3;
375 if (remainder > 10) {
376 tmp_H_width += 1; /* fine adjustment */
377 }
378 }
379 /* timeout of BBSY bit is minimum low width by frequency */
380 /* so timeout calculates "(low width) * 2" by frequency */
381 wait_utime = (L_time * 2) * 1000000;
382 /* 1 wait of BBSY bit is about 0.3us. if it's below 0.3us, wait count is set as 1. */
383 if (wait_utime <= 0.3) {
384 obj->i2c.bbsy_wait_cnt = 1;
385 } else {
386 obj->i2c.bbsy_wait_cnt = (int)(wait_utime / 0.3);
387 }
388
389
390 /* I2C Rate */
391 obj->i2c.pclk_bit = (uint8_t)(0x10 * wk_cks); /* P_phi / xx */
392 obj->i2c.width_low = (uint8_t)(tmp_L_width | 0x000000E0);
393 obj->i2c.width_hi = (uint8_t)(tmp_H_width | 0x000000E0);
394
395 /* full reset */
396 i2c_reg_reset(obj);
397}
398
399int i2c_read(i2c_t *obj, int address, char *data, int length, int stop) {
400 int count = 0;
401 int status;
402 int value;
403
404 i2c_set_MR3_ACK(obj);
405 /* There is a STOP condition for last processing */
406 if (obj->i2c.last_stop_flag != 0) {
407 status = i2c_start(obj);
408 if (status != 0) {
409 i2c_set_err_noslave(obj);
410 return I2C_ERROR_BUS_BUSY;
411 }
412 }
413 obj->i2c.last_stop_flag = stop;
414 /* Send Slave address */
415 status = i2c_read_address_write(obj, (address | 0x01));
416 if (status != 0) {
417 i2c_set_err_noslave(obj);
418 return I2C_ERROR_NO_SLAVE;
419 }
420 /* wait RDRF */
421 status = i2c_wait_RDRF(obj);
422 /* check ACK/NACK */
423 if ((status != 0) || ((REG(SR2.UINT32) & SR2_NACKF) != 0)) {
424 /* Slave sends NACK */
425 (void)i2c_set_STOP(obj);
426 /* dummy read */
427 value = REG(DRR.UINT32);
428 (void)i2c_wait_STOP(obj);
429 i2c_set_SR2_NACKF_STOP(obj);
430 obj->i2c.last_stop_flag = 1;
431 return I2C_ERROR_NO_SLAVE;
432 }
433 if (length != 0) {
434 /* Read in all except last byte */
435 if (length > 2) {
436 /* dummy read */
437 value = REG(DRR.UINT32);
438 for (count = 0; count < (length - 1); count++) {
439 /* wait for it to arrive */
440 status = i2c_wait_RDRF(obj);
441 if (status != 0) {
442 i2c_set_err_noslave(obj);
443 return I2C_ERROR_NO_SLAVE;
444 }
445 /* Recieve the data */
446 if (count == (length - 2)) {
447 value = i2c_do_read(obj, 1);
448 } else if ((length >= 3) && (count == (length - 3))) {
449 value = i2c_do_read(obj, 2);
450 } else {
451 value = i2c_do_read(obj, 0);
452 }
453 data[count] = (char)value;
454 }
455 } else if (length == 2) {
456 /* Set MR3 WAIT bit is 1 */
457 REG(MR3.UINT32) |= MR3_WAIT;
458 /* dummy read */
459 value = REG(DRR.UINT32);
460 /* wait for it to arrive */
461 status = i2c_wait_RDRF(obj);
462 if (status != 0) {
463 i2c_set_err_noslave(obj);
464 return I2C_ERROR_NO_SLAVE;
465 }
466 i2c_set_MR3_NACK(obj);
467 data[count] = (char)REG(DRR.UINT32);
468 count++;
469 } else {
470 /* length == 1 */
471 /* Set MR3 WAIT bit is 1 */;
472 REG(MR3.UINT32) |= MR3_WAIT;
473 i2c_set_MR3_NACK(obj);
474 /* dummy read */
475 value = REG(DRR.UINT32);
476 }
477 /* wait for it to arrive */
478 status = i2c_wait_RDRF(obj);
479 if (status != 0) {
480 i2c_set_err_noslave(obj);
481 return I2C_ERROR_NO_SLAVE;
482 }
483
484 /* If not repeated start, send stop. */
485 if (stop) {
486 (void)i2c_set_STOP(obj);
487 /* RIICnDRR read */
488 value = (REG(DRR.UINT32) & 0xFF);
489 data[count] = (char)value;
490 /* RIICnMR3.WAIT = 0 */
491 REG(MR3.UINT32) &= ~MR3_WAIT;
492 (void)i2c_wait_STOP(obj);
493 i2c_set_SR2_NACKF_STOP(obj);
494 } else {
495 (void)i2c_restart(obj);
496 /* RIICnDRR read */
497 value = (REG(DRR.UINT32) & 0xFF);
498 data[count] = (char)value;
499 /* RIICnMR3.WAIT = 0 */
500 REG(MR3.UINT32) &= ~MR3_WAIT;
501 (void)i2c_wait_START(obj);
502 /* SR2.START = 0 */
503 REG(SR2.UINT32) &= ~SR2_START;
504 }
505 } else {
506 /* If not repeated start, send stop. */
507 if (stop) {
508 (void)i2c_set_STOP(obj);
509 (void)i2c_wait_STOP(obj);
510 i2c_set_SR2_NACKF_STOP(obj);
511 } else {
512 (void)i2c_restart(obj);
513 (void)i2c_wait_START(obj);
514 /* SR2.START = 0 */
515 REG(SR2.UINT32) &= ~SR2_START;
516 }
517 }
518
519 return length;
520}
521
522int i2c_write(i2c_t *obj, int address, const char *data, int length, int stop) {
523 int cnt;
524 int status;
525
526 /* There is a STOP condition for last processing */
527 if (obj->i2c.last_stop_flag != 0) {
528 status = i2c_start(obj);
529 if (status != 0) {
530 i2c_set_err_noslave(obj);
531 return I2C_ERROR_BUS_BUSY;
532 }
533 }
534 obj->i2c.last_stop_flag = stop;
535 /* Send Slave address */
536 status = i2c_do_write(obj, address);
537 if (status != 0) {
538 i2c_set_err_noslave(obj);
539 return I2C_ERROR_NO_SLAVE;
540 }
541 /* Wait send end */
542 status = i2c_wait_TEND(obj);
543 if ((status != 0) || ((REG(SR2.UINT32) & SR2_NACKF) != 0)) {
544 /* Slave sends NACK */
545 i2c_set_err_noslave(obj);
546 return I2C_ERROR_NO_SLAVE;
547 }
548 /* Send Write data */
549 for (cnt=0; cnt<length; cnt++) {
550 status = i2c_do_write(obj, data[cnt]);
551 if(status != 0) {
552 i2c_set_err_noslave(obj);
553 return cnt;
554 } else {
555 /* Wait send end */
556 status = i2c_wait_TEND(obj);
557 if ((status != 0) || ((REG(SR2.UINT32) & SR2_NACKF) != 0)) {
558 /* Slave sends NACK */
559 i2c_set_err_noslave(obj);
560 return I2C_ERROR_NO_SLAVE;
561 }
562 }
563 }
564 /* If not repeated start, send stop. */
565 if (stop) {
566 (void)i2c_set_STOP(obj);
567 (void)i2c_wait_STOP(obj);
568 i2c_set_SR2_NACKF_STOP(obj);
569 } else {
570 (void)i2c_restart(obj);
571 (void)i2c_wait_START(obj);
572 /* SR2.START = 0 */
573 REG(SR2.UINT32) &= ~SR2_START;
574
575 }
576
577 return length;
578}
579
580void i2c_reset(i2c_t *obj) {
581 (void)i2c_set_STOP(obj);
582 (void)i2c_wait_STOP(obj);
583 i2c_set_SR2_NACKF_STOP(obj);
584}
585
586int i2c_byte_read(i2c_t *obj, int last) {
587 int status;
588 int data;
589
590 data = i2c_do_read(obj, last);
591 /* wait for it to arrive */
592 status = i2c_wait_RDRF(obj);
593 if (status != 0) {
594 i2c_set_SR2_NACKF_STOP(obj);
595 return I2C_ERROR_NO_SLAVE;
596 }
597
598 return data;
599}
600
601int i2c_byte_write(i2c_t *obj, int data) {
602 int ack = 0;
603 int status;
604 int timeout = 0;
605
606 status = i2c_do_write(obj, (data & 0xFF));
607 if (status != 0) {
608 i2c_set_SR2_NACKF_STOP(obj);
609 } else {
610 while (((i2c_status(obj) & SR2_RDRF) == 0) && ((i2c_status(obj) & SR2_TEND) == 0)) {
611 timeout++;
612 if (timeout >= WAIT_TIMEOUT) {
613 return ack;
614 }
615 }
616 /* check ACK/NACK */
617 if ((REG(SR2.UINT32) & SR2_NACKF) != 0) {
618 /* NACK */
619 i2c_set_SR2_NACKF_STOP(obj);
620 } else {
621 ack = 1;
622 }
623 }
624
625 return ack;
626}
627
628void i2c_slave_mode(i2c_t *obj, int enable_slave) {
629 if (enable_slave != 0) {
630 REG(SER.UINT32) |= SER_SAR0E; // only slave addr 0 is enabled
631 } else {
632 REG(SER.UINT32) &= ~SER_SAR0E; // no slave addr enabled
633 }
634}
635
636int i2c_slave_receive(i2c_t *obj) {
637 int status;
638 int retval;
639
640 status = (REG(SR1.UINT8[0]) & SR1_AAS0);
641 status |= (REG(CR2.UINT8[0]) & CR2_TRS) >> 4;
642
643 switch(status) {
644 case 0x01:
645 /* the master is writing to this slave */
646 retval = 3;
647 break;
648 case 0x02:
649 /* the master is writing to all slave */
650 retval = 2;
651 break;
652 case 0x03:
653 /* the master has requested a read from this slave */
654 retval = 1;
655 break;
656 default :
657 /* no data */
658 retval = 0;
659 break;
660 }
661
662 return retval;
663}
664
665int i2c_slave_read(i2c_t *obj, char *data, int length) {
666 int timeout = 0;
667 int count;
668 int break_flg = 0;
669
670 if(length <= 0) {
671 return 0;
672 }
673 for (count = 0; ((count < (length + 1)) && (break_flg == 0)); count++) {
674 /* There is no timeout, but the upper limit value is set to avoid an infinite loop. */
675 while (((i2c_status(obj) & SR2_STOP) != 0) || ((i2c_status(obj) & SR2_RDRF) == 0)) {
676 if ((i2c_status(obj) & SR2_STOP) != 0) {
677 break_flg = 1;
678 break;
679 }
680 timeout ++;
681 if (timeout >= WAIT_TIMEOUT) {
682 return -1;
683 }
684 }
685 if (break_flg == 0) {
686 if (count == 0) {
687 /* dummy read */
688 (void)REG(DRR.UINT32);
689 } else {
690 data[count - 1] = (char)(REG(DRR.UINT32) & 0xFF);
691 }
692 }
693 }
694 if (break_flg == 0) {
695 (void)i2c_wait_STOP(obj);
696 } else {
697 if ((i2c_status(obj) & SR2_RDRF) != 0) {
698 if (count <= 1) {
699 /* fail safe */
700 /* dummy read */
701 (void)REG(DRR.UINT32);
702 } else {
703 data[count - 2] = (char)(REG(DRR.UINT32) & 0xFF);
704 }
705 }
706 }
707 /* SR2.STOP = 0 */
708 REG(SR2.UINT32) &= ~SR2_STOP;
709
710 return (count - 1);
711}
712
713int i2c_slave_write(i2c_t *obj, const char *data, int length) {
714 int count = 0;
715 int status = 0;
716
717 if(length <= 0) {
718 return 0;
719 }
720
721 while ((count < length) && (status == 0)) {
722 status = i2c_do_write(obj, data[count]);
723 if(status == 0) {
724 /* Wait send end */
725 status = i2c_wait_TEND(obj);
726 if ((status != 0) || ((count < (length - 1)) && ((REG(SR2.UINT32) & SR2_NACKF) != 0))) {
727 /* NACK */
728 break;
729 }
730 }
731 count++;
732 }
733 /* dummy read */
734 (void)REG(DRR.UINT32);
735 (void)i2c_wait_STOP(obj);
736 i2c_set_SR2_NACKF_STOP(obj);
737
738 return count;
739}
740
741void i2c_slave_address(i2c_t *obj, int idx, uint32_t address, uint32_t mask) {
742 REG(SAR0.UINT32) = (address & 0xfffffffe);
743}
744
745#if DEVICE_I2C_ASYNCH
746
747#define IRQ_NUM 4
748#define IRQ_TX 0
749#define IRQ_RX 1
750#define IRQ_ERR1 2
751#define IRQ_ERR2 3
752
753static void i2c_irqs_set(i2c_t *obj, uint32_t enable);
754
755static void i2c0_tx_irq(void);
756static void i2c1_tx_irq(void);
757static void i2c2_tx_irq(void);
758static void i2c3_tx_irq(void);
759static void i2c0_rx_irq(void);
760static void i2c1_rx_irq(void);
761static void i2c2_rx_irq(void);
762static void i2c3_rx_irq(void);
763static void i2c0_al_irq(void);
764static void i2c1_al_irq(void);
765static void i2c2_al_irq(void);
766static void i2c3_al_irq(void);
767static void i2c0_to_irq(void);
768static void i2c1_to_irq(void);
769static void i2c2_to_irq(void);
770static void i2c3_to_irq(void);
771
772static const IRQn_Type irq_set_tbl[RIIC_COUNT][IRQ_NUM] = {
773 {INTIICTEI0_IRQn, INTIICRI0_IRQn, INTIICALI0_IRQn, INTIICTMOI0_IRQn},
774 {INTIICTEI1_IRQn, INTIICRI1_IRQn, INTIICALI1_IRQn, INTIICTMOI1_IRQn},
775 {INTIICTEI2_IRQn, INTIICRI2_IRQn, INTIICALI2_IRQn, INTIICTMOI2_IRQn},
776 {INTIICTEI3_IRQn, INTIICRI3_IRQn, INTIICALI3_IRQn, INTIICTMOI3_IRQn},
777};
778
779static const IRQHandler hander_set_tbl[RIIC_COUNT][IRQ_NUM] = {
780 {i2c0_tx_irq, i2c0_rx_irq, i2c0_al_irq, i2c0_to_irq},
781 {i2c1_tx_irq, i2c1_rx_irq, i2c1_al_irq, i2c1_to_irq},
782 {i2c2_tx_irq, i2c2_rx_irq, i2c2_al_irq, i2c2_to_irq},
783 {i2c3_tx_irq, i2c3_rx_irq, i2c3_al_irq, i2c3_to_irq},
784};
785
786struct i2c_global_data_s {
787 i2c_t *async_obj;
788 uint32_t async_callback, event, shouldStop, address;
789};
790
791static struct i2c_global_data_s i2c_data[RIIC_COUNT];
792
793static void i2c_transfer_finished(i2c_t *obj)
794{
795 i2c_irqs_set(obj, 0);
796 uint32_t index = obj->i2c.i2c;
797 i2c_data[index].event = I2C_EVENT_TRANSFER_COMPLETE;
798 i2c_data[index].async_obj = NULL;
799 ((void (*)())i2c_data[index].async_callback)();
800}
801
802static void i2c_tx_irq(IRQn_Type irq_num, uint32_t index)
803{
804 i2c_t *obj = i2c_data[index].async_obj;
805 if ((REG(SR2.UINT32) & SR2_NACKF)) {
806 /* Slave sends NACK */
807 i2c_set_err_noslave(obj);
808 i2c_data[index].event = I2C_EVENT_ERROR | I2C_EVENT_TRANSFER_EARLY_NACK;
809 i2c_abort_asynch(obj);
810 ((void (*)())i2c_data[index].async_callback)();
811 return;
812 }
813 if (obj->tx_buff.pos == obj->tx_buff.length) {
814 /* All datas have tranferred */
815
816 /* Clear TEND */
817 REG(SR2.UINT32) &= ~(SR2_TEND);
818
819 /* If not repeated start, send stop. */
820 if (i2c_data[index].shouldStop && obj->rx_buff.length == 0) {
821 (void)i2c_set_STOP(obj);
822 (void)i2c_wait_STOP(obj);
823 i2c_set_SR2_NACKF_STOP(obj);
824 i2c_transfer_finished(obj);
825 } else {
826 (void)i2c_restart(obj);
827 (void)i2c_wait_START(obj);
828 /* SR2.START = 0 */
829 REG(SR2.UINT32) &= ~SR2_START;
830 if (obj->rx_buff.length) {
831 /* Ready to read */
832 i2c_set_MR3_ACK(obj);
833
834 /* Disable INTRIICTEI */
835 REG(IER.UINT8[0]) &= ~(1 << 6);
836
837 /* Send Slave address */
838 if (i2c_read_address_write(obj, (i2c_data[index].address | 0x01)) != 0) {
839 i2c_set_err_noslave(obj);
840 i2c_data[index].event = I2C_EVENT_ERROR | I2C_EVENT_ERROR_NO_SLAVE;
841 i2c_abort_asynch(obj);
842 ((void (*)())i2c_data[index].async_callback)();
843 return;
844 }
845 } else {
846 i2c_transfer_finished(obj);
847 }
848 }
849 } else {
850 /* Send next 1 byte */
851 if (i2c_do_write(obj, *(uint8_t *)obj->tx_buff.buffer) != 0) {
852 i2c_set_err_noslave(obj);
853 i2c_data[index].event = I2C_EVENT_ERROR | I2C_EVENT_ERROR_NO_SLAVE;
854 i2c_abort_asynch(obj);
855 ((void (*)())i2c_data[index].async_callback)();
856 return;
857 }
858 obj->tx_buff.buffer = (uint8_t *)obj->tx_buff.buffer + 1;
859 ++obj->tx_buff.pos;
860 }
861}
862
863static void i2c_rx_irq(IRQn_Type irq_num, uint32_t index)
864{
865 i2c_t *obj = i2c_data[index].async_obj;
866 if (obj->rx_buff.pos == SIZE_MAX) {
867 if ((REG(SR2.UINT32) & SR2_NACKF) != 0) {
868 /* Slave sends NACK */
869 (void)i2c_set_STOP(obj);
870 /* dummy read */
871 if (REG(DRR.UINT32)) {}
872 (void)i2c_wait_STOP(obj);
873 i2c_set_SR2_NACKF_STOP(obj);
874 obj->i2c.last_stop_flag = 1;
875
876 i2c_data[index].event = I2C_EVENT_ERROR | I2C_EVENT_TRANSFER_EARLY_NACK;
877 i2c_abort_asynch(obj);
878 ((void (*)())i2c_data[index].async_callback)();
879 return;
880 }
881 if (obj->rx_buff.length == 1) {
882 /* length == 1 */
883 /* Set MR3 WAIT bit is 1 */;
884 REG(MR3.UINT32) |= MR3_WAIT;
885 i2c_set_MR3_NACK(obj);
886 } else if (obj->rx_buff.length == 2) {
887 /* Set MR3 WAIT bit is 1 */
888 REG(MR3.UINT32) |= MR3_WAIT;
889 }
890 /* dummy read */
891 if (REG(DRR.UINT32)) {}
892 obj->rx_buff.pos = 0;
893 return;
894 }
895 if ((REG(SR2.UINT32) & SR2_NACKF) != 0) {
896 /* Slave sends NACK */
897 i2c_set_err_noslave(obj);
898 i2c_data[index].event = I2C_EVENT_ERROR | I2C_EVENT_TRANSFER_EARLY_NACK;
899 i2c_abort_asynch(obj);
900 ((void (*)())i2c_data[index].async_callback)();
901 return;
902 } else {
903 switch (obj->rx_buff.length - obj->rx_buff.pos) {
904 case 1:
905 /* Finished */
906 /* If not repeated start, send stop. */
907 if (i2c_data[index].shouldStop) {
908 (void)i2c_set_STOP(obj);
909 /* RIICnDRR read */
910 *(uint8_t *)obj->rx_buff.buffer = REG(DRR.UINT32) & 0xFF;
911 /* RIICnMR3.WAIT = 0 */
912 REG(MR3.UINT32) &= ~MR3_WAIT;
913 (void)i2c_wait_STOP(obj);
914 i2c_set_SR2_NACKF_STOP(obj);
915 } else {
916 (void)i2c_restart(obj);
917 /* RIICnDRR read */
918 *(uint8_t *)obj->rx_buff.buffer = REG(DRR.UINT32) & 0xFF;
919 /* RIICnMR3.WAIT = 0 */
920 REG(MR3.UINT32) &= ~MR3_WAIT;
921 (void)i2c_wait_START(obj);
922 /* SR2.START = 0 */
923 REG(SR2.UINT32) &= ~SR2_START;
924 }
925
926 i2c_transfer_finished(obj);
927 return;
928
929 case 2:
930 i2c_set_MR3_NACK(obj);
931 break;
932
933 case 3:
934 /* this time is befor last byte read */
935 /* Set MR3 WAIT bit is 1 */
936 REG(MR3.UINT32) |= MR3_WAIT;
937 break;
938
939 default:
940 i2c_set_MR3_ACK(obj);
941 break;
942 }
943 *(uint8_t *)obj->rx_buff.buffer = REG(DRR.UINT32) & 0xFF;
944 obj->rx_buff.buffer = (uint8_t *)obj->rx_buff.buffer + 1;
945 ++obj->rx_buff.pos;
946 }
947}
948
949static void i2c_err_irq(IRQn_Type irq_num, uint32_t index)
950{
951 i2c_t *obj = i2c_data[index].async_obj;
952 i2c_abort_asynch(obj);
953 i2c_data[index].event = I2C_EVENT_ERROR;
954 ((void (*)())i2c_data[index].async_callback)();
955}
956
957/* TX handler */
958static void i2c0_tx_irq(void)
959{
960 i2c_tx_irq(INTIICTEI0_IRQn, 0);
961}
962
963static void i2c1_tx_irq(void)
964{
965 i2c_tx_irq(INTIICTEI1_IRQn, 1);
966}
967
968static void i2c2_tx_irq(void)
969{
970 i2c_tx_irq(INTIICTEI2_IRQn, 2);
971}
972
973static void i2c3_tx_irq(void)
974{
975 i2c_tx_irq(INTIICTEI3_IRQn, 3);
976}
977
978/* RX handler */
979static void i2c0_rx_irq(void)
980{
981 i2c_rx_irq(INTIICRI0_IRQn, 0);
982}
983
984static void i2c1_rx_irq(void)
985{
986 i2c_rx_irq(INTIICRI1_IRQn, 1);
987}
988
989static void i2c2_rx_irq(void)
990{
991 i2c_rx_irq(INTIICRI2_IRQn, 2);
992}
993
994static void i2c3_rx_irq(void)
995{
996 i2c_rx_irq(INTIICRI3_IRQn, 3);
997}
998
999/* Arbitration Lost handler */
1000static void i2c0_al_irq(void)
1001{
1002 i2c_err_irq(INTIICALI0_IRQn, 0);
1003}
1004
1005static void i2c1_al_irq(void)
1006{
1007 i2c_err_irq(INTIICALI1_IRQn, 1);
1008}
1009
1010static void i2c2_al_irq(void)
1011{
1012 i2c_err_irq(INTIICALI2_IRQn, 2);
1013}
1014
1015static void i2c3_al_irq(void)
1016{
1017 i2c_err_irq(INTIICALI3_IRQn, 3);
1018}
1019
1020/* Timeout handler */
1021static void i2c0_to_irq(void)
1022{
1023 i2c_err_irq(INTIICTMOI0_IRQn, 0);
1024}
1025
1026static void i2c1_to_irq(void)
1027{
1028 i2c_err_irq(INTIICTMOI1_IRQn, 1);
1029}
1030
1031static void i2c2_to_irq(void)
1032{
1033 i2c_err_irq(INTIICTMOI2_IRQn, 2);
1034}
1035
1036static void i2c3_to_irq(void)
1037{
1038 i2c_err_irq(INTIICTMOI3_IRQn, 3);
1039}
1040
1041static void i2c_irqs_set(i2c_t *obj, uint32_t enable)
1042{
1043 int i;
1044 const IRQn_Type *irqTable = irq_set_tbl[obj->i2c.i2c];
1045 const IRQHandler *handlerTable = hander_set_tbl[obj->i2c.i2c];
1046 for (i = 0; i < IRQ_NUM; ++i) {
1047 if (enable) {
1048 InterruptHandlerRegister(irqTable[i], handlerTable[i]);
1049 GIC_SetPriority(irqTable[i], 5);
1050 if (i == 1) {
1051 GIC_SetConfiguration(irqTable[i], 3);
1052 } else {
1053 GIC_SetConfiguration(irqTable[i], 1);
1054 }
1055 GIC_EnableIRQ(irqTable[i]);
1056 } else {
1057 GIC_DisableIRQ(irqTable[i]);
1058 }
1059 }
1060 REG(IER.UINT8[0]) = enable ? 0x63 : 0x00;
1061}
1062
1063/******************************************************************************
1064 * ASYNCHRONOUS HAL
1065 ******************************************************************************/
1066
1067void i2c_transfer_asynch(i2c_t *obj, const void *tx, size_t tx_length, void *rx, size_t rx_length, uint32_t address, uint32_t stop, uint32_t handler, uint32_t event, DMAUsage hint)
1068{
1069 MBED_ASSERT(obj);
1070 MBED_ASSERT(tx ? tx_length : 1);
1071 MBED_ASSERT(rx ? rx_length : 1);
1072 MBED_ASSERT((REG(SER.UINT32) & SER_SAR0E) == 0); /* Slave mode */
1073
1074 obj->tx_buff.buffer = (void *)tx;
1075 obj->tx_buff.length = tx_length;
1076 obj->tx_buff.pos = 0;
1077 obj->tx_buff.width = 8;
1078 obj->rx_buff.buffer = rx;
1079 obj->rx_buff.length = rx_length;
1080 obj->rx_buff.pos = SIZE_MAX;
1081 obj->rx_buff.width = 8;
1082 i2c_data[obj->i2c.i2c].async_obj = obj;
1083 i2c_data[obj->i2c.i2c].async_callback = handler;
1084 i2c_data[obj->i2c.i2c].event = 0;
1085 i2c_data[obj->i2c.i2c].shouldStop = stop;
1086 i2c_data[obj->i2c.i2c].address = address;
1087 i2c_irqs_set(obj, 1);
1088
1089 /* There is a STOP condition for last processing */
1090 if (obj->i2c.last_stop_flag != 0) {
1091 if (i2c_start(obj) != 0) {
1092 i2c_set_err_noslave(obj);
1093 i2c_data[obj->i2c.i2c].event = I2C_EVENT_ERROR | I2C_EVENT_ERROR_NO_SLAVE;
1094 i2c_abort_asynch(obj);
1095 ((void (*)())handler)();
1096 return;
1097 }
1098 }
1099 obj->i2c.last_stop_flag = stop;
1100
1101 if (rx_length && tx_length == 0) {
1102 /* Ready to read */
1103 i2c_set_MR3_ACK(obj);
1104
1105 /* Disable INTRIICTEI */
1106 REG(IER.UINT8[0]) &= ~(1 << 6);
1107
1108 address |= 0x01;
1109 }
1110 /* Send Slave address */
1111 if (i2c_do_write(obj, address) != 0) {
1112 i2c_set_err_noslave(obj);
1113 i2c_data[obj->i2c.i2c].event = I2C_EVENT_ERROR | I2C_EVENT_ERROR_NO_SLAVE;
1114 i2c_abort_asynch(obj);
1115 ((void (*)())handler)();
1116 return;
1117 }
1118}
1119
1120uint32_t i2c_irq_handler_asynch(i2c_t *obj)
1121{
1122 return i2c_data[obj->i2c.i2c].event;
1123}
1124
1125uint8_t i2c_active(i2c_t *obj)
1126{
1127 return i2c_data[obj->i2c.i2c].async_obj != NULL;
1128}
1129
1130void i2c_abort_asynch(i2c_t *obj)
1131{
1132 i2c_data[obj->i2c.i2c].async_obj = NULL;
1133 i2c_irqs_set(obj, 0);
1134 i2c_reg_reset(obj);
1135}
1136
1137#endif
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