source: asp3_tinet_ecnl_arm/trunk/asp3_dcre/mbed/targets/TARGET_RENESAS/TARGET_RZA1XX/gpio_irq_api.c@ 374

Last change on this file since 374 was 374, checked in by coas-nagasima, 5 years ago

mbed関連を更新
シリアルドライバをmbedのHALを使うよう変更
ファイルディスクリプタの処理を更新

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File size: 4.8 KB
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1/* mbed Microcontroller Library
2 * Copyright (c) 2006-2013 ARM Limited
3 *
4 * Licensed under the Apache License, Version 2.0 (the "License");
5 * you may not use this file except in compliance with the License.
6 * You may obtain a copy of the License at
7 *
8 * http://www.apache.org/licenses/LICENSE-2.0
9 *
10 * Unless required by applicable law or agreed to in writing, software
11 * distributed under the License is distributed on an "AS IS" BASIS,
12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
13 * See the License for the specific language governing permissions and
14 * limitations under the License.
15 */
16#include <stddef.h>
17
18#include "gpio_irq_api.h"
19#include "iodefine.h"
20#include "PeripheralPins.h"
21#include "cmsis.h"
22#include "gpio_addrdefine.h"
23
24#define CHANNEL_NUM 8
25
26static void gpio_irq0(void);
27static void gpio_irq1(void);
28static void gpio_irq2(void);
29static void gpio_irq3(void);
30static void gpio_irq4(void);
31static void gpio_irq5(void);
32static void gpio_irq6(void);
33static void gpio_irq7(void);
34
35static gpio_irq_t *channel_obj[CHANNEL_NUM] = {NULL};
36static gpio_irq_handler irq_handler;
37static const int nIRQn_h = 32;
38extern PinName gpio_multi_guard;
39
40static const IRQHandler irq_tbl[CHANNEL_NUM] = {
41 &gpio_irq0,
42 &gpio_irq1,
43 &gpio_irq2,
44 &gpio_irq3,
45 &gpio_irq4,
46 &gpio_irq5,
47 &gpio_irq6,
48 &gpio_irq7,
49};
50
51static void handle_interrupt_in(int irq_num) {
52 uint16_t irqs;
53 uint16_t edge_req;
54 gpio_irq_t *obj;
55 gpio_irq_event irq_event;
56
57 irqs = INTCIRQRR;
58 if (irqs & (1 << irq_num)) {
59 obj = channel_obj[irq_num];
60 if (obj != NULL) {
61 edge_req = ((INTCICR1 >> (obj->ch * 2)) & 3);
62 if (edge_req == 1) {
63 irq_event = IRQ_FALL;
64 } else if (edge_req == 2) {
65 irq_event = IRQ_RISE;
66 } else {
67 uint32_t mask = (1 << (obj->pin & 0x0F));
68 __I uint32_t *reg_in = (volatile uint32_t *) PPR((int)PINGROUP(obj->pin));
69
70 if ((*reg_in & mask) == 0) {
71 irq_event = IRQ_FALL;
72 } else {
73 irq_event = IRQ_RISE;
74 }
75 }
76 irq_handler(obj->port, irq_event);
77 }
78 INTCIRQRR &= ~(1 << irq_num);
79 }
80}
81
82static void gpio_irq0(void) {
83 handle_interrupt_in(0);
84}
85
86static void gpio_irq1(void) {
87 handle_interrupt_in(1);
88}
89
90static void gpio_irq2(void) {
91 handle_interrupt_in(2);
92}
93
94static void gpio_irq3(void) {
95 handle_interrupt_in(3);
96}
97
98static void gpio_irq4(void) {
99 handle_interrupt_in(4);
100}
101
102static void gpio_irq5(void) {
103 handle_interrupt_in(5);
104}
105
106static void gpio_irq6(void) {
107 handle_interrupt_in(6);
108}
109
110static void gpio_irq7(void) {
111 handle_interrupt_in(7);
112}
113
114int gpio_irq_init(gpio_irq_t *obj, PinName pin, gpio_irq_handler handler, uint32_t id) {
115 int shift;
116 if (pin == NC) return -1;
117
118 obj->ch = pinmap_peripheral(pin, PinMap_IRQ);
119 obj->pin = (int)pin ;
120 obj->port = (int)id ;
121
122 shift = obj->ch*2;
123 channel_obj[obj->ch] = obj;
124 irq_handler = handler;
125
126 pinmap_pinout(pin, PinMap_IRQ);
127 gpio_multi_guard = pin; /* Set multi guard */
128
129 // INTC settings
130 InterruptHandlerRegister((IRQn_Type)(nIRQn_h+obj->ch), (void (*)(uint32_t))irq_tbl[obj->ch]);
131 INTCICR1 &= ~(0x3 << shift);
132 GIC_SetPriority((IRQn_Type)(nIRQn_h+obj->ch), 5);
133 GIC_SetConfiguration((IRQn_Type)(nIRQn_h + obj->ch), 1);
134 obj->int_enable = 1;
135 __enable_irq();
136
137 return 0;
138}
139
140void gpio_irq_free(gpio_irq_t *obj) {
141 channel_obj[obj->ch] = NULL;
142}
143
144void gpio_irq_set(gpio_irq_t *obj, gpio_irq_event event, uint32_t enable) {
145 int shift = obj->ch*2;
146 uint16_t val = event == IRQ_RISE ? 2 :
147 event == IRQ_FALL ? 1 : 0;
148 uint16_t work_icr_val;
149
150 /* check edge interrupt setting */
151 work_icr_val = INTCICR1;
152 if (enable == 1) {
153 /* Set interrupt serect */
154 work_icr_val |= (val << shift);
155 } else {
156 /* Clear interrupt serect */
157 work_icr_val &= ~(val << shift);
158 }
159
160 if ((work_icr_val & (3 << shift)) == 0) {
161 /* No edge interrupt setting */
162 GIC_DisableIRQ((IRQn_Type)(nIRQn_h+obj->ch));
163 /* Clear Interrupt flags */
164 INTCIRQRR &= ~(1 << obj->ch);
165 INTCICR1 = work_icr_val;
166 } else if (obj->int_enable == 1) {
167 INTCICR1 = work_icr_val;
168 GIC_EnableIRQ((IRQn_Type)(nIRQn_h + obj->ch));
169 } else {
170 INTCICR1 = work_icr_val;
171 }
172}
173
174void gpio_irq_enable(gpio_irq_t *obj) {
175 int shift = obj->ch*2;
176 uint16_t work_icr_val = INTCICR1;
177
178 /* check edge interrupt setting */
179 if ((work_icr_val & (3 << shift)) != 0) {
180 GIC_EnableIRQ((IRQn_Type)(nIRQn_h + obj->ch));
181 }
182 obj->int_enable = 1;
183}
184
185void gpio_irq_disable(gpio_irq_t *obj) {
186 GIC_DisableIRQ((IRQn_Type)(nIRQn_h + obj->ch));
187 obj->int_enable = 0;
188}
189
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