source: asp3_tinet_ecnl_arm/trunk/asp3_dcre/mbed/targets/TARGET_RENESAS/TARGET_RZA1XX/TARGET_RZ_A1H/device/inc/iodefines/ssif_iodefine.h@ 374

Last change on this file since 374 was 374, checked in by coas-nagasima, 5 years ago

mbed関連を更新
シリアルドライバをmbedのHALを使うよう変更
ファイルディスクリプタの処理を更新
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File size: 6.1 KB
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1/*******************************************************************************
2* DISCLAIMER
3* This software is supplied by Renesas Electronics Corporation and is only
4* intended for use with Renesas products. No other uses are authorized. This
5* software is owned by Renesas Electronics Corporation and is protected under
6* all applicable laws, including copyright laws.
7* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
8* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
9* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
10* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
11* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
12* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
13* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
14* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
15* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
16* Renesas reserves the right, without notice, to make changes to this software
17* and to discontinue the availability of this software. By using this software,
18* you agree to the additional terms and conditions found by accessing the
19* following link:
20* http://www.renesas.com/disclaimer*
21* Copyright (C) 2013-2015 Renesas Electronics Corporation. All rights reserved.
22*******************************************************************************/
23/*******************************************************************************
24* File Name : ssif_iodefine.h
25* $Rev: $
26* $Date:: $
27* Description : Definition of I/O Register for RZ/A1H,M (V2.00h)
28******************************************************************************/
29#ifndef SSIF_IODEFINE_H
30#define SSIF_IODEFINE_H
31/* ->QAC 0639 : Over 127 members (C90) */
32/* ->QAC 0857 : Over 1024 #define (C90) */
33/* ->MISRA 18.4 : Pack unpack union */ /* ->SEC M1.6.2 */
34/* ->SEC M1.10.1 : Not magic number */
35
36#define SSIF0 (*(struct st_ssif *)0xE820B000uL) /* SSIF0 */
37#define SSIF1 (*(struct st_ssif *)0xE820B800uL) /* SSIF1 */
38#define SSIF2 (*(struct st_ssif *)0xE820C000uL) /* SSIF2 */
39#define SSIF3 (*(struct st_ssif *)0xE820C800uL) /* SSIF3 */
40#define SSIF4 (*(struct st_ssif *)0xE820D000uL) /* SSIF4 */
41#define SSIF5 (*(struct st_ssif *)0xE820D800uL) /* SSIF5 */
42
43
44/* Start of channel array defines of SSIF */
45
46/* Channel array defines of SSIF */
47/*(Sample) value = SSIF[ channel ]->SSICR; */
48#define SSIF_COUNT (6)
49#define SSIF_ADDRESS_LIST \
50{ /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \
51 &SSIF0, &SSIF1, &SSIF2, &SSIF3, &SSIF4, &SSIF5 \
52} /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */
53
54/* End of channel array defines of SSIF */
55
56
57#define SSICR_0 (SSIF0.SSICR)
58#define SSISR_0 (SSIF0.SSISR)
59#define SSIFCR_0 (SSIF0.SSIFCR)
60#define SSIFSR_0 (SSIF0.SSIFSR)
61#define SSIFTDR_0 (SSIF0.SSIFTDR)
62#define SSIFRDR_0 (SSIF0.SSIFRDR)
63#define SSITDMR_0 (SSIF0.SSITDMR)
64#define SSIFCCR_0 (SSIF0.SSIFCCR)
65#define SSIFCMR_0 (SSIF0.SSIFCMR)
66#define SSIFCSR_0 (SSIF0.SSIFCSR)
67#define SSICR_1 (SSIF1.SSICR)
68#define SSISR_1 (SSIF1.SSISR)
69#define SSIFCR_1 (SSIF1.SSIFCR)
70#define SSIFSR_1 (SSIF1.SSIFSR)
71#define SSIFTDR_1 (SSIF1.SSIFTDR)
72#define SSIFRDR_1 (SSIF1.SSIFRDR)
73#define SSITDMR_1 (SSIF1.SSITDMR)
74#define SSIFCCR_1 (SSIF1.SSIFCCR)
75#define SSIFCMR_1 (SSIF1.SSIFCMR)
76#define SSIFCSR_1 (SSIF1.SSIFCSR)
77#define SSICR_2 (SSIF2.SSICR)
78#define SSISR_2 (SSIF2.SSISR)
79#define SSIFCR_2 (SSIF2.SSIFCR)
80#define SSIFSR_2 (SSIF2.SSIFSR)
81#define SSIFTDR_2 (SSIF2.SSIFTDR)
82#define SSIFRDR_2 (SSIF2.SSIFRDR)
83#define SSITDMR_2 (SSIF2.SSITDMR)
84#define SSIFCCR_2 (SSIF2.SSIFCCR)
85#define SSIFCMR_2 (SSIF2.SSIFCMR)
86#define SSIFCSR_2 (SSIF2.SSIFCSR)
87#define SSICR_3 (SSIF3.SSICR)
88#define SSISR_3 (SSIF3.SSISR)
89#define SSIFCR_3 (SSIF3.SSIFCR)
90#define SSIFSR_3 (SSIF3.SSIFSR)
91#define SSIFTDR_3 (SSIF3.SSIFTDR)
92#define SSIFRDR_3 (SSIF3.SSIFRDR)
93#define SSITDMR_3 (SSIF3.SSITDMR)
94#define SSIFCCR_3 (SSIF3.SSIFCCR)
95#define SSIFCMR_3 (SSIF3.SSIFCMR)
96#define SSIFCSR_3 (SSIF3.SSIFCSR)
97#define SSICR_4 (SSIF4.SSICR)
98#define SSISR_4 (SSIF4.SSISR)
99#define SSIFCR_4 (SSIF4.SSIFCR)
100#define SSIFSR_4 (SSIF4.SSIFSR)
101#define SSIFTDR_4 (SSIF4.SSIFTDR)
102#define SSIFRDR_4 (SSIF4.SSIFRDR)
103#define SSITDMR_4 (SSIF4.SSITDMR)
104#define SSIFCCR_4 (SSIF4.SSIFCCR)
105#define SSIFCMR_4 (SSIF4.SSIFCMR)
106#define SSIFCSR_4 (SSIF4.SSIFCSR)
107#define SSICR_5 (SSIF5.SSICR)
108#define SSISR_5 (SSIF5.SSISR)
109#define SSIFCR_5 (SSIF5.SSIFCR)
110#define SSIFSR_5 (SSIF5.SSIFSR)
111#define SSIFTDR_5 (SSIF5.SSIFTDR)
112#define SSIFRDR_5 (SSIF5.SSIFRDR)
113#define SSITDMR_5 (SSIF5.SSITDMR)
114#define SSIFCCR_5 (SSIF5.SSIFCCR)
115#define SSIFCMR_5 (SSIF5.SSIFCMR)
116#define SSIFCSR_5 (SSIF5.SSIFCSR)
117
118
119typedef struct st_ssif
120{
121 /* SSIF */
122 volatile uint32_t SSICR; /* SSICR */
123 volatile uint32_t SSISR; /* SSISR */
124 volatile uint8_t dummy1[8]; /* */
125 volatile uint32_t SSIFCR; /* SSIFCR */
126 volatile uint32_t SSIFSR; /* SSIFSR */
127 volatile uint32_t SSIFTDR; /* SSIFTDR */
128 volatile uint32_t SSIFRDR; /* SSIFRDR */
129 volatile uint32_t SSITDMR; /* SSITDMR */
130 volatile uint32_t SSIFCCR; /* SSIFCCR */
131 volatile uint32_t SSIFCMR; /* SSIFCMR */
132 volatile uint32_t SSIFCSR; /* SSIFCSR */
133} r_io_ssif_t;
134
135
136/* Channel array defines of SSIF (2)*/
137#ifdef DECLARE_SSIF_CHANNELS
138volatile struct st_ssif* SSIF[ SSIF_COUNT ] =
139 /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */
140 SSIF_ADDRESS_LIST;
141 /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */
142#endif /* DECLARE_SSIF_CHANNELS */
143/* End of channel array defines of SSIF (2)*/
144
145
146/* <-SEC M1.10.1 */
147/* <-MISRA 18.4 */ /* <-SEC M1.6.2 */
148/* <-QAC 0857 */
149/* <-QAC 0639 */
150#endif
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