[352] | 1 | /*******************************************************************************
|
---|
| 2 | * DISCLAIMER
|
---|
| 3 | * This software is supplied by Renesas Electronics Corporation and is only
|
---|
| 4 | * intended for use with Renesas products. No other uses are authorized. This
|
---|
| 5 | * software is owned by Renesas Electronics Corporation and is protected under
|
---|
| 6 | * all applicable laws, including copyright laws.
|
---|
| 7 | * THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
|
---|
| 8 | * THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
|
---|
| 9 | * LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
|
---|
| 10 | * AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
|
---|
| 11 | * TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
|
---|
| 12 | * ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
|
---|
| 13 | * FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
|
---|
| 14 | * ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
|
---|
| 15 | * BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
|
---|
| 16 | * Renesas reserves the right, without notice, to make changes to this software
|
---|
| 17 | * and to discontinue the availability of this software. By using this software,
|
---|
| 18 | * you agree to the additional terms and conditions found by accessing the
|
---|
| 19 | * following link:
|
---|
| 20 | * http://www.renesas.com/disclaimer*
|
---|
[374] | 21 | * Copyright (C) 2013-2015 Renesas Electronics Corporation. All rights reserved.
|
---|
[352] | 22 | *******************************************************************************/
|
---|
| 23 | /*******************************************************************************
|
---|
| 24 | * File Name : spibsc_iodefine.h
|
---|
| 25 | * $Rev: $
|
---|
| 26 | * $Date:: $
|
---|
[374] | 27 | * Description : Definition of I/O Register for RZ/A1H,M (V2.00h)
|
---|
[352] | 28 | ******************************************************************************/
|
---|
| 29 | #ifndef SPIBSC_IODEFINE_H
|
---|
| 30 | #define SPIBSC_IODEFINE_H
|
---|
[374] | 31 | /* ->QAC 0639 : Over 127 members (C90) */
|
---|
| 32 | /* ->QAC 0857 : Over 1024 #define (C90) */
|
---|
| 33 | /* ->MISRA 18.4 : Pack unpack union */ /* ->SEC M1.6.2 */
|
---|
[352] | 34 | /* ->SEC M1.10.1 : Not magic number */
|
---|
| 35 |
|
---|
[374] | 36 | #define SPIBSC0 (*(struct st_spibsc *)0x3FEFA000uL) /* SPIBSC0 */
|
---|
| 37 | #define SPIBSC1 (*(struct st_spibsc *)0x3FEFB000uL) /* SPIBSC1 */
|
---|
| 38 |
|
---|
| 39 |
|
---|
| 40 | /* Start of channel array defines of SPIBSC */
|
---|
| 41 |
|
---|
| 42 | /* Channel array defines of SPIBSC */
|
---|
| 43 | /*(Sample) value = SPIBSC[ channel ]->CMNCR; */
|
---|
| 44 | #define SPIBSC_COUNT (2)
|
---|
| 45 | #define SPIBSC_ADDRESS_LIST \
|
---|
| 46 | { /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \
|
---|
| 47 | &SPIBSC0, &SPIBSC1 \
|
---|
| 48 | } /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */
|
---|
| 49 |
|
---|
| 50 | /* End of channel array defines of SPIBSC */
|
---|
| 51 |
|
---|
| 52 |
|
---|
| 53 | #define CMNCR_0 (SPIBSC0.CMNCR)
|
---|
| 54 | #define SSLDR_0 (SPIBSC0.SSLDR)
|
---|
| 55 | #define SPBCR_0 (SPIBSC0.SPBCR)
|
---|
| 56 | #define DRCR_0 (SPIBSC0.DRCR)
|
---|
| 57 | #define DRCMR_0 (SPIBSC0.DRCMR)
|
---|
| 58 | #define DREAR_0 (SPIBSC0.DREAR)
|
---|
| 59 | #define DROPR_0 (SPIBSC0.DROPR)
|
---|
| 60 | #define DRENR_0 (SPIBSC0.DRENR)
|
---|
| 61 | #define SMCR_0 (SPIBSC0.SMCR)
|
---|
| 62 | #define SMCMR_0 (SPIBSC0.SMCMR)
|
---|
| 63 | #define SMADR_0 (SPIBSC0.SMADR)
|
---|
| 64 | #define SMOPR_0 (SPIBSC0.SMOPR)
|
---|
| 65 | #define SMENR_0 (SPIBSC0.SMENR)
|
---|
| 66 | #define SMRDR0_0 (SPIBSC0.SMRDR0.UINT32)
|
---|
| 67 | #define SMRDR0_0L (SPIBSC0.SMRDR0.UINT16[R_IO_L])
|
---|
| 68 | #define SMRDR0_0H (SPIBSC0.SMRDR0.UINT16[R_IO_H])
|
---|
| 69 | #define SMRDR0_0LL (SPIBSC0.SMRDR0.UINT8[R_IO_LL])
|
---|
| 70 | #define SMRDR0_0LH (SPIBSC0.SMRDR0.UINT8[R_IO_LH])
|
---|
| 71 | #define SMRDR0_0HL (SPIBSC0.SMRDR0.UINT8[R_IO_HL])
|
---|
| 72 | #define SMRDR0_0HH (SPIBSC0.SMRDR0.UINT8[R_IO_HH])
|
---|
| 73 | #define SMRDR1_0 (SPIBSC0.SMRDR1.UINT32)
|
---|
| 74 | #define SMRDR1_0L (SPIBSC0.SMRDR1.UINT16[R_IO_L])
|
---|
| 75 | #define SMRDR1_0H (SPIBSC0.SMRDR1.UINT16[R_IO_H])
|
---|
| 76 | #define SMRDR1_0LL (SPIBSC0.SMRDR1.UINT8[R_IO_LL])
|
---|
| 77 | #define SMRDR1_0LH (SPIBSC0.SMRDR1.UINT8[R_IO_LH])
|
---|
| 78 | #define SMRDR1_0HL (SPIBSC0.SMRDR1.UINT8[R_IO_HL])
|
---|
| 79 | #define SMRDR1_0HH (SPIBSC0.SMRDR1.UINT8[R_IO_HH])
|
---|
| 80 | #define SMWDR0_0 (SPIBSC0.SMWDR0.UINT32)
|
---|
| 81 | #define SMWDR0_0L (SPIBSC0.SMWDR0.UINT16[R_IO_L])
|
---|
| 82 | #define SMWDR0_0H (SPIBSC0.SMWDR0.UINT16[R_IO_H])
|
---|
| 83 | #define SMWDR0_0LL (SPIBSC0.SMWDR0.UINT8[R_IO_LL])
|
---|
| 84 | #define SMWDR0_0LH (SPIBSC0.SMWDR0.UINT8[R_IO_LH])
|
---|
| 85 | #define SMWDR0_0HL (SPIBSC0.SMWDR0.UINT8[R_IO_HL])
|
---|
| 86 | #define SMWDR0_0HH (SPIBSC0.SMWDR0.UINT8[R_IO_HH])
|
---|
| 87 | #define SMWDR1_0 (SPIBSC0.SMWDR1.UINT32)
|
---|
| 88 | #define SMWDR1_0L (SPIBSC0.SMWDR1.UINT16[R_IO_L])
|
---|
| 89 | #define SMWDR1_0H (SPIBSC0.SMWDR1.UINT16[R_IO_H])
|
---|
| 90 | #define SMWDR1_0LL (SPIBSC0.SMWDR1.UINT8[R_IO_LL])
|
---|
| 91 | #define SMWDR1_0LH (SPIBSC0.SMWDR1.UINT8[R_IO_LH])
|
---|
| 92 | #define SMWDR1_0HL (SPIBSC0.SMWDR1.UINT8[R_IO_HL])
|
---|
| 93 | #define SMWDR1_0HH (SPIBSC0.SMWDR1.UINT8[R_IO_HH])
|
---|
| 94 | #define CMNSR_0 (SPIBSC0.CMNSR)
|
---|
| 95 | #define CKDLY_0 (SPIBSC0.CKDLY)
|
---|
| 96 | #define DRDMCR_0 (SPIBSC0.DRDMCR)
|
---|
| 97 | #define DRDRENR_0 (SPIBSC0.DRDRENR)
|
---|
| 98 | #define SMDMCR_0 (SPIBSC0.SMDMCR)
|
---|
| 99 | #define SMDRENR_0 (SPIBSC0.SMDRENR)
|
---|
| 100 | #define SPODLY_0 (SPIBSC0.SPODLY)
|
---|
| 101 | #define CMNCR_1 (SPIBSC1.CMNCR)
|
---|
| 102 | #define SSLDR_1 (SPIBSC1.SSLDR)
|
---|
| 103 | #define SPBCR_1 (SPIBSC1.SPBCR)
|
---|
| 104 | #define DRCR_1 (SPIBSC1.DRCR)
|
---|
| 105 | #define DRCMR_1 (SPIBSC1.DRCMR)
|
---|
| 106 | #define DREAR_1 (SPIBSC1.DREAR)
|
---|
| 107 | #define DROPR_1 (SPIBSC1.DROPR)
|
---|
| 108 | #define DRENR_1 (SPIBSC1.DRENR)
|
---|
| 109 | #define SMCR_1 (SPIBSC1.SMCR)
|
---|
| 110 | #define SMCMR_1 (SPIBSC1.SMCMR)
|
---|
| 111 | #define SMADR_1 (SPIBSC1.SMADR)
|
---|
| 112 | #define SMOPR_1 (SPIBSC1.SMOPR)
|
---|
| 113 | #define SMENR_1 (SPIBSC1.SMENR)
|
---|
| 114 | #define SMRDR0_1 (SPIBSC1.SMRDR0.UINT32)
|
---|
| 115 | #define SMRDR0_1L (SPIBSC1.SMRDR0.UINT16[R_IO_L])
|
---|
| 116 | #define SMRDR0_1H (SPIBSC1.SMRDR0.UINT16[R_IO_H])
|
---|
| 117 | #define SMRDR0_1LL (SPIBSC1.SMRDR0.UINT8[R_IO_LL])
|
---|
| 118 | #define SMRDR0_1LH (SPIBSC1.SMRDR0.UINT8[R_IO_LH])
|
---|
| 119 | #define SMRDR0_1HL (SPIBSC1.SMRDR0.UINT8[R_IO_HL])
|
---|
| 120 | #define SMRDR0_1HH (SPIBSC1.SMRDR0.UINT8[R_IO_HH])
|
---|
| 121 | #define SMRDR1_1 (SPIBSC1.SMRDR1.UINT32)
|
---|
| 122 | #define SMRDR1_1L (SPIBSC1.SMRDR1.UINT16[R_IO_L])
|
---|
| 123 | #define SMRDR1_1H (SPIBSC1.SMRDR1.UINT16[R_IO_H])
|
---|
| 124 | #define SMRDR1_1LL (SPIBSC1.SMRDR1.UINT8[R_IO_LL])
|
---|
| 125 | #define SMRDR1_1LH (SPIBSC1.SMRDR1.UINT8[R_IO_LH])
|
---|
| 126 | #define SMRDR1_1HL (SPIBSC1.SMRDR1.UINT8[R_IO_HL])
|
---|
| 127 | #define SMRDR1_1HH (SPIBSC1.SMRDR1.UINT8[R_IO_HH])
|
---|
| 128 | #define SMWDR0_1 (SPIBSC1.SMWDR0.UINT32)
|
---|
| 129 | #define SMWDR0_1L (SPIBSC1.SMWDR0.UINT16[R_IO_L])
|
---|
| 130 | #define SMWDR0_1H (SPIBSC1.SMWDR0.UINT16[R_IO_H])
|
---|
| 131 | #define SMWDR0_1LL (SPIBSC1.SMWDR0.UINT8[R_IO_LL])
|
---|
| 132 | #define SMWDR0_1LH (SPIBSC1.SMWDR0.UINT8[R_IO_LH])
|
---|
| 133 | #define SMWDR0_1HL (SPIBSC1.SMWDR0.UINT8[R_IO_HL])
|
---|
| 134 | #define SMWDR0_1HH (SPIBSC1.SMWDR0.UINT8[R_IO_HH])
|
---|
| 135 | #define SMWDR1_1 (SPIBSC1.SMWDR1.UINT32)
|
---|
| 136 | #define SMWDR1_1L (SPIBSC1.SMWDR1.UINT16[R_IO_L])
|
---|
| 137 | #define SMWDR1_1H (SPIBSC1.SMWDR1.UINT16[R_IO_H])
|
---|
| 138 | #define SMWDR1_1LL (SPIBSC1.SMWDR1.UINT8[R_IO_LL])
|
---|
| 139 | #define SMWDR1_1LH (SPIBSC1.SMWDR1.UINT8[R_IO_LH])
|
---|
| 140 | #define SMWDR1_1HL (SPIBSC1.SMWDR1.UINT8[R_IO_HL])
|
---|
| 141 | #define SMWDR1_1HH (SPIBSC1.SMWDR1.UINT8[R_IO_HH])
|
---|
| 142 | #define CMNSR_1 (SPIBSC1.CMNSR)
|
---|
| 143 | #define CKDLY_1 (SPIBSC1.CKDLY)
|
---|
| 144 | #define DRDMCR_1 (SPIBSC1.DRDMCR)
|
---|
| 145 | #define DRDRENR_1 (SPIBSC1.DRDRENR)
|
---|
| 146 | #define SMDMCR_1 (SPIBSC1.SMDMCR)
|
---|
| 147 | #define SMDRENR_1 (SPIBSC1.SMDRENR)
|
---|
| 148 | #define SPODLY_1 (SPIBSC1.SPODLY)
|
---|
| 149 |
|
---|
| 150 |
|
---|
| 151 | typedef struct st_spibsc
|
---|
| 152 | {
|
---|
| 153 | /* SPIBSC */
|
---|
[352] | 154 | volatile uint32_t CMNCR; /* CMNCR */
|
---|
| 155 | volatile uint32_t SSLDR; /* SSLDR */
|
---|
| 156 | volatile uint32_t SPBCR; /* SPBCR */
|
---|
| 157 | volatile uint32_t DRCR; /* DRCR */
|
---|
| 158 | volatile uint32_t DRCMR; /* DRCMR */
|
---|
| 159 | volatile uint32_t DREAR; /* DREAR */
|
---|
| 160 | volatile uint32_t DROPR; /* DROPR */
|
---|
| 161 | volatile uint32_t DRENR; /* DRENR */
|
---|
| 162 | volatile uint32_t SMCR; /* SMCR */
|
---|
| 163 | volatile uint32_t SMCMR; /* SMCMR */
|
---|
| 164 | volatile uint32_t SMADR; /* SMADR */
|
---|
| 165 | volatile uint32_t SMOPR; /* SMOPR */
|
---|
| 166 | volatile uint32_t SMENR; /* SMENR */
|
---|
| 167 | volatile uint8_t dummy1[4]; /* */
|
---|
| 168 | union iodefine_reg32_t SMRDR0; /* SMRDR0 */
|
---|
| 169 | union iodefine_reg32_t SMRDR1; /* SMRDR1 */
|
---|
| 170 | union iodefine_reg32_t SMWDR0; /* SMWDR0 */
|
---|
| 171 | union iodefine_reg32_t SMWDR1; /* SMWDR1 */
|
---|
| 172 |
|
---|
| 173 | volatile uint32_t CMNSR; /* CMNSR */
|
---|
[374] | 174 | volatile uint8_t dummy2[4]; /* */
|
---|
| 175 | volatile uint32_t CKDLY; /* CKDLY */
|
---|
| 176 | volatile uint8_t dummy3[4]; /* */
|
---|
[352] | 177 | volatile uint32_t DRDMCR; /* DRDMCR */
|
---|
| 178 | volatile uint32_t DRDRENR; /* DRDRENR */
|
---|
| 179 | volatile uint32_t SMDMCR; /* SMDMCR */
|
---|
| 180 | volatile uint32_t SMDRENR; /* SMDRENR */
|
---|
[374] | 181 | volatile uint32_t SPODLY; /* SPODLY */
|
---|
| 182 | } r_io_spibsc_t;
|
---|
[352] | 183 |
|
---|
| 184 |
|
---|
[374] | 185 | /* Channel array defines of SPIBSC (2)*/
|
---|
| 186 | #ifdef DECLARE_SPIBSC_CHANNELS
|
---|
| 187 | volatile struct st_spibsc* SPIBSC[ SPIBSC_COUNT ] =
|
---|
| 188 | /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */
|
---|
| 189 | SPIBSC_ADDRESS_LIST;
|
---|
| 190 | /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */
|
---|
| 191 | #endif /* DECLARE_SPIBSC_CHANNELS */
|
---|
| 192 | /* End of channel array defines of SPIBSC (2)*/
|
---|
[352] | 193 |
|
---|
| 194 |
|
---|
| 195 | /* <-SEC M1.10.1 */
|
---|
[374] | 196 | /* <-MISRA 18.4 */ /* <-SEC M1.6.2 */
|
---|
| 197 | /* <-QAC 0857 */
|
---|
| 198 | /* <-QAC 0639 */
|
---|
[352] | 199 | #endif
|
---|