source: asp3_tinet_ecnl_arm/trunk/asp3_dcre/mbed/targets/TARGET_RENESAS/TARGET_RZA1XX/TARGET_RZ_A1H/device/inc/iodefines/scif_iodefine.h@ 374

Last change on this file since 374 was 374, checked in by coas-nagasima, 5 years ago

mbed関連を更新
シリアルドライバをmbedのHALを使うよう変更
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1/*******************************************************************************
2* DISCLAIMER
3* This software is supplied by Renesas Electronics Corporation and is only
4* intended for use with Renesas products. No other uses are authorized. This
5* software is owned by Renesas Electronics Corporation and is protected under
6* all applicable laws, including copyright laws.
7* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
8* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
9* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
10* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
11* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
12* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
13* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
14* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
15* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
16* Renesas reserves the right, without notice, to make changes to this software
17* and to discontinue the availability of this software. By using this software,
18* you agree to the additional terms and conditions found by accessing the
19* following link:
20* http://www.renesas.com/disclaimer*
21* Copyright (C) 2013-2015 Renesas Electronics Corporation. All rights reserved.
22*******************************************************************************/
23/*******************************************************************************
24* File Name : scif_iodefine.h
25* $Rev: $
26* $Date:: $
27* Description : Definition of I/O Register for RZ/A1H,M (V2.00h)
28******************************************************************************/
29#ifndef SCIF_IODEFINE_H
30#define SCIF_IODEFINE_H
31/* ->QAC 0639 : Over 127 members (C90) */
32/* ->QAC 0857 : Over 1024 #define (C90) */
33/* ->MISRA 18.4 : Pack unpack union */ /* ->SEC M1.6.2 */
34/* ->SEC M1.10.1 : Not magic number */
35
36#define SCIF0 (*(struct st_scif *)0xE8007000uL) /* SCIF0 */
37#define SCIF1 (*(struct st_scif *)0xE8007800uL) /* SCIF1 */
38#define SCIF2 (*(struct st_scif *)0xE8008000uL) /* SCIF2 */
39#define SCIF3 (*(struct st_scif *)0xE8008800uL) /* SCIF3 */
40#define SCIF4 (*(struct st_scif *)0xE8009000uL) /* SCIF4 */
41#define SCIF5 (*(struct st_scif *)0xE8009800uL) /* SCIF5 */
42#define SCIF6 (*(struct st_scif *)0xE800A000uL) /* SCIF6 */
43#define SCIF7 (*(struct st_scif *)0xE800A800uL) /* SCIF7 */
44
45
46/* Start of channel array defines of SCIF */
47
48/* Channel array defines of SCIF */
49/*(Sample) value = SCIF[ channel ]->SCSMR; */
50#define SCIF_COUNT (8)
51#define SCIF_ADDRESS_LIST \
52{ /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \
53 &SCIF0, &SCIF1, &SCIF2, &SCIF3, &SCIF4, &SCIF5, &SCIF6, &SCIF7 \
54} /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */
55
56/* End of channel array defines of SCIF */
57
58
59#define SCSMR_0 (SCIF0.SCSMR)
60#define SCBRR_0 (SCIF0.SCBRR)
61#define SCSCR_0 (SCIF0.SCSCR)
62#define SCFTDR_0 (SCIF0.SCFTDR)
63#define SCFSR_0 (SCIF0.SCFSR)
64#define SCFRDR_0 (SCIF0.SCFRDR)
65#define SCFCR_0 (SCIF0.SCFCR)
66#define SCFDR_0 (SCIF0.SCFDR)
67#define SCSPTR_0 (SCIF0.SCSPTR)
68#define SCLSR_0 (SCIF0.SCLSR)
69#define SCEMR_0 (SCIF0.SCEMR)
70#define SCSMR_1 (SCIF1.SCSMR)
71#define SCBRR_1 (SCIF1.SCBRR)
72#define SCSCR_1 (SCIF1.SCSCR)
73#define SCFTDR_1 (SCIF1.SCFTDR)
74#define SCFSR_1 (SCIF1.SCFSR)
75#define SCFRDR_1 (SCIF1.SCFRDR)
76#define SCFCR_1 (SCIF1.SCFCR)
77#define SCFDR_1 (SCIF1.SCFDR)
78#define SCSPTR_1 (SCIF1.SCSPTR)
79#define SCLSR_1 (SCIF1.SCLSR)
80#define SCEMR_1 (SCIF1.SCEMR)
81#define SCSMR_2 (SCIF2.SCSMR)
82#define SCBRR_2 (SCIF2.SCBRR)
83#define SCSCR_2 (SCIF2.SCSCR)
84#define SCFTDR_2 (SCIF2.SCFTDR)
85#define SCFSR_2 (SCIF2.SCFSR)
86#define SCFRDR_2 (SCIF2.SCFRDR)
87#define SCFCR_2 (SCIF2.SCFCR)
88#define SCFDR_2 (SCIF2.SCFDR)
89#define SCSPTR_2 (SCIF2.SCSPTR)
90#define SCLSR_2 (SCIF2.SCLSR)
91#define SCEMR_2 (SCIF2.SCEMR)
92#define SCSMR_3 (SCIF3.SCSMR)
93#define SCBRR_3 (SCIF3.SCBRR)
94#define SCSCR_3 (SCIF3.SCSCR)
95#define SCFTDR_3 (SCIF3.SCFTDR)
96#define SCFSR_3 (SCIF3.SCFSR)
97#define SCFRDR_3 (SCIF3.SCFRDR)
98#define SCFCR_3 (SCIF3.SCFCR)
99#define SCFDR_3 (SCIF3.SCFDR)
100#define SCSPTR_3 (SCIF3.SCSPTR)
101#define SCLSR_3 (SCIF3.SCLSR)
102#define SCEMR_3 (SCIF3.SCEMR)
103#define SCSMR_4 (SCIF4.SCSMR)
104#define SCBRR_4 (SCIF4.SCBRR)
105#define SCSCR_4 (SCIF4.SCSCR)
106#define SCFTDR_4 (SCIF4.SCFTDR)
107#define SCFSR_4 (SCIF4.SCFSR)
108#define SCFRDR_4 (SCIF4.SCFRDR)
109#define SCFCR_4 (SCIF4.SCFCR)
110#define SCFDR_4 (SCIF4.SCFDR)
111#define SCSPTR_4 (SCIF4.SCSPTR)
112#define SCLSR_4 (SCIF4.SCLSR)
113#define SCEMR_4 (SCIF4.SCEMR)
114#define SCSMR_5 (SCIF5.SCSMR)
115#define SCBRR_5 (SCIF5.SCBRR)
116#define SCSCR_5 (SCIF5.SCSCR)
117#define SCFTDR_5 (SCIF5.SCFTDR)
118#define SCFSR_5 (SCIF5.SCFSR)
119#define SCFRDR_5 (SCIF5.SCFRDR)
120#define SCFCR_5 (SCIF5.SCFCR)
121#define SCFDR_5 (SCIF5.SCFDR)
122#define SCSPTR_5 (SCIF5.SCSPTR)
123#define SCLSR_5 (SCIF5.SCLSR)
124#define SCEMR_5 (SCIF5.SCEMR)
125#define SCSMR_6 (SCIF6.SCSMR)
126#define SCBRR_6 (SCIF6.SCBRR)
127#define SCSCR_6 (SCIF6.SCSCR)
128#define SCFTDR_6 (SCIF6.SCFTDR)
129#define SCFSR_6 (SCIF6.SCFSR)
130#define SCFRDR_6 (SCIF6.SCFRDR)
131#define SCFCR_6 (SCIF6.SCFCR)
132#define SCFDR_6 (SCIF6.SCFDR)
133#define SCSPTR_6 (SCIF6.SCSPTR)
134#define SCLSR_6 (SCIF6.SCLSR)
135#define SCEMR_6 (SCIF6.SCEMR)
136#define SCSMR_7 (SCIF7.SCSMR)
137#define SCBRR_7 (SCIF7.SCBRR)
138#define SCSCR_7 (SCIF7.SCSCR)
139#define SCFTDR_7 (SCIF7.SCFTDR)
140#define SCFSR_7 (SCIF7.SCFSR)
141#define SCFRDR_7 (SCIF7.SCFRDR)
142#define SCFCR_7 (SCIF7.SCFCR)
143#define SCFDR_7 (SCIF7.SCFDR)
144#define SCSPTR_7 (SCIF7.SCSPTR)
145#define SCLSR_7 (SCIF7.SCLSR)
146#define SCEMR_7 (SCIF7.SCEMR)
147
148
149typedef struct st_scif
150{
151 /* SCIF */
152 volatile uint16_t SCSMR; /* SCSMR */
153 volatile uint8_t dummy1[2]; /* */
154 volatile uint8_t SCBRR; /* SCBRR */
155 volatile uint8_t dummy2[3]; /* */
156 volatile uint16_t SCSCR; /* SCSCR */
157 volatile uint8_t dummy3[2]; /* */
158 volatile uint8_t SCFTDR; /* SCFTDR */
159 volatile uint8_t dummy4[3]; /* */
160 volatile uint16_t SCFSR; /* SCFSR */
161 volatile uint8_t dummy5[2]; /* */
162 volatile uint8_t SCFRDR; /* SCFRDR */
163 volatile uint8_t dummy6[3]; /* */
164 volatile uint16_t SCFCR; /* SCFCR */
165 volatile uint8_t dummy7[2]; /* */
166 volatile uint16_t SCFDR; /* SCFDR */
167 volatile uint8_t dummy8[2]; /* */
168 volatile uint16_t SCSPTR; /* SCSPTR */
169 volatile uint8_t dummy9[2]; /* */
170 volatile uint16_t SCLSR; /* SCLSR */
171 volatile uint8_t dummy10[2]; /* */
172 volatile uint16_t SCEMR; /* SCEMR */
173} r_io_scif_t;
174
175
176/* Channel array defines of SCIF (2)*/
177#ifdef DECLARE_SCIF_CHANNELS
178volatile struct st_scif* SCIF[ SCIF_COUNT ] =
179 /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */
180 SCIF_ADDRESS_LIST;
181 /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */
182#endif /* DECLARE_SCIF_CHANNELS */
183/* End of channel array defines of SCIF (2)*/
184
185
186/* <-SEC M1.10.1 */
187/* <-MISRA 18.4 */ /* <-SEC M1.6.2 */
188/* <-QAC 0857 */
189/* <-QAC 0639 */
190#endif
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