1 | /*******************************************************************************
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2 | * DISCLAIMER
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3 | * This software is supplied by Renesas Electronics Corporation and is only
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4 | * intended for use with Renesas products. No other uses are authorized. This
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5 | * software is owned by Renesas Electronics Corporation and is protected under
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6 | * all applicable laws, including copyright laws.
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7 | * THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
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8 | * THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
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9 | * LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
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10 | * AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
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11 | * TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
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12 | * ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
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13 | * FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
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14 | * ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
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15 | * BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
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16 | * Renesas reserves the right, without notice, to make changes to this software
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17 | * and to discontinue the availability of this software. By using this software,
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18 | * you agree to the additional terms and conditions found by accessing the
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19 | * following link:
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20 | * http://www.renesas.com/disclaimer*
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21 | * Copyright (C) 2013-2015 Renesas Electronics Corporation. All rights reserved.
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22 | *******************************************************************************/
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23 | /*******************************************************************************
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24 | * File Name : scif_iodefine.h
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25 | * $Rev: $
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26 | * $Date:: $
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27 | * Description : Definition of I/O Register for RZ/A1H,M (V2.00h)
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28 | ******************************************************************************/
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29 | #ifndef SCIF_IODEFINE_H
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30 | #define SCIF_IODEFINE_H
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31 | /* ->QAC 0639 : Over 127 members (C90) */
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32 | /* ->QAC 0857 : Over 1024 #define (C90) */
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33 | /* ->MISRA 18.4 : Pack unpack union */ /* ->SEC M1.6.2 */
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34 | /* ->SEC M1.10.1 : Not magic number */
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35 |
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36 | #define SCIF0 (*(struct st_scif *)0xE8007000uL) /* SCIF0 */
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37 | #define SCIF1 (*(struct st_scif *)0xE8007800uL) /* SCIF1 */
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38 | #define SCIF2 (*(struct st_scif *)0xE8008000uL) /* SCIF2 */
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39 | #define SCIF3 (*(struct st_scif *)0xE8008800uL) /* SCIF3 */
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40 | #define SCIF4 (*(struct st_scif *)0xE8009000uL) /* SCIF4 */
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41 | #define SCIF5 (*(struct st_scif *)0xE8009800uL) /* SCIF5 */
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42 | #define SCIF6 (*(struct st_scif *)0xE800A000uL) /* SCIF6 */
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43 | #define SCIF7 (*(struct st_scif *)0xE800A800uL) /* SCIF7 */
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44 |
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45 |
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46 | /* Start of channel array defines of SCIF */
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47 |
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48 | /* Channel array defines of SCIF */
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49 | /*(Sample) value = SCIF[ channel ]->SCSMR; */
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50 | #define SCIF_COUNT (8)
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51 | #define SCIF_ADDRESS_LIST \
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52 | { /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \
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53 | &SCIF0, &SCIF1, &SCIF2, &SCIF3, &SCIF4, &SCIF5, &SCIF6, &SCIF7 \
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54 | } /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */
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55 |
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56 | /* End of channel array defines of SCIF */
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57 |
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58 |
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59 | #define SCSMR_0 (SCIF0.SCSMR)
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60 | #define SCBRR_0 (SCIF0.SCBRR)
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61 | #define SCSCR_0 (SCIF0.SCSCR)
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62 | #define SCFTDR_0 (SCIF0.SCFTDR)
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63 | #define SCFSR_0 (SCIF0.SCFSR)
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64 | #define SCFRDR_0 (SCIF0.SCFRDR)
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65 | #define SCFCR_0 (SCIF0.SCFCR)
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66 | #define SCFDR_0 (SCIF0.SCFDR)
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67 | #define SCSPTR_0 (SCIF0.SCSPTR)
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68 | #define SCLSR_0 (SCIF0.SCLSR)
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69 | #define SCEMR_0 (SCIF0.SCEMR)
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70 | #define SCSMR_1 (SCIF1.SCSMR)
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71 | #define SCBRR_1 (SCIF1.SCBRR)
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72 | #define SCSCR_1 (SCIF1.SCSCR)
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73 | #define SCFTDR_1 (SCIF1.SCFTDR)
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74 | #define SCFSR_1 (SCIF1.SCFSR)
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75 | #define SCFRDR_1 (SCIF1.SCFRDR)
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76 | #define SCFCR_1 (SCIF1.SCFCR)
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77 | #define SCFDR_1 (SCIF1.SCFDR)
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78 | #define SCSPTR_1 (SCIF1.SCSPTR)
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79 | #define SCLSR_1 (SCIF1.SCLSR)
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80 | #define SCEMR_1 (SCIF1.SCEMR)
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81 | #define SCSMR_2 (SCIF2.SCSMR)
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82 | #define SCBRR_2 (SCIF2.SCBRR)
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83 | #define SCSCR_2 (SCIF2.SCSCR)
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84 | #define SCFTDR_2 (SCIF2.SCFTDR)
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85 | #define SCFSR_2 (SCIF2.SCFSR)
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86 | #define SCFRDR_2 (SCIF2.SCFRDR)
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87 | #define SCFCR_2 (SCIF2.SCFCR)
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88 | #define SCFDR_2 (SCIF2.SCFDR)
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89 | #define SCSPTR_2 (SCIF2.SCSPTR)
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90 | #define SCLSR_2 (SCIF2.SCLSR)
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91 | #define SCEMR_2 (SCIF2.SCEMR)
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92 | #define SCSMR_3 (SCIF3.SCSMR)
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93 | #define SCBRR_3 (SCIF3.SCBRR)
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94 | #define SCSCR_3 (SCIF3.SCSCR)
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95 | #define SCFTDR_3 (SCIF3.SCFTDR)
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96 | #define SCFSR_3 (SCIF3.SCFSR)
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97 | #define SCFRDR_3 (SCIF3.SCFRDR)
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98 | #define SCFCR_3 (SCIF3.SCFCR)
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99 | #define SCFDR_3 (SCIF3.SCFDR)
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100 | #define SCSPTR_3 (SCIF3.SCSPTR)
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101 | #define SCLSR_3 (SCIF3.SCLSR)
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102 | #define SCEMR_3 (SCIF3.SCEMR)
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103 | #define SCSMR_4 (SCIF4.SCSMR)
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104 | #define SCBRR_4 (SCIF4.SCBRR)
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105 | #define SCSCR_4 (SCIF4.SCSCR)
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106 | #define SCFTDR_4 (SCIF4.SCFTDR)
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107 | #define SCFSR_4 (SCIF4.SCFSR)
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108 | #define SCFRDR_4 (SCIF4.SCFRDR)
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109 | #define SCFCR_4 (SCIF4.SCFCR)
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110 | #define SCFDR_4 (SCIF4.SCFDR)
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111 | #define SCSPTR_4 (SCIF4.SCSPTR)
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112 | #define SCLSR_4 (SCIF4.SCLSR)
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113 | #define SCEMR_4 (SCIF4.SCEMR)
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114 | #define SCSMR_5 (SCIF5.SCSMR)
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115 | #define SCBRR_5 (SCIF5.SCBRR)
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116 | #define SCSCR_5 (SCIF5.SCSCR)
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117 | #define SCFTDR_5 (SCIF5.SCFTDR)
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118 | #define SCFSR_5 (SCIF5.SCFSR)
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119 | #define SCFRDR_5 (SCIF5.SCFRDR)
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120 | #define SCFCR_5 (SCIF5.SCFCR)
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121 | #define SCFDR_5 (SCIF5.SCFDR)
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122 | #define SCSPTR_5 (SCIF5.SCSPTR)
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123 | #define SCLSR_5 (SCIF5.SCLSR)
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124 | #define SCEMR_5 (SCIF5.SCEMR)
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125 | #define SCSMR_6 (SCIF6.SCSMR)
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126 | #define SCBRR_6 (SCIF6.SCBRR)
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127 | #define SCSCR_6 (SCIF6.SCSCR)
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128 | #define SCFTDR_6 (SCIF6.SCFTDR)
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129 | #define SCFSR_6 (SCIF6.SCFSR)
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130 | #define SCFRDR_6 (SCIF6.SCFRDR)
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131 | #define SCFCR_6 (SCIF6.SCFCR)
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132 | #define SCFDR_6 (SCIF6.SCFDR)
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133 | #define SCSPTR_6 (SCIF6.SCSPTR)
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134 | #define SCLSR_6 (SCIF6.SCLSR)
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135 | #define SCEMR_6 (SCIF6.SCEMR)
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136 | #define SCSMR_7 (SCIF7.SCSMR)
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137 | #define SCBRR_7 (SCIF7.SCBRR)
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138 | #define SCSCR_7 (SCIF7.SCSCR)
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139 | #define SCFTDR_7 (SCIF7.SCFTDR)
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140 | #define SCFSR_7 (SCIF7.SCFSR)
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141 | #define SCFRDR_7 (SCIF7.SCFRDR)
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142 | #define SCFCR_7 (SCIF7.SCFCR)
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143 | #define SCFDR_7 (SCIF7.SCFDR)
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144 | #define SCSPTR_7 (SCIF7.SCSPTR)
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145 | #define SCLSR_7 (SCIF7.SCLSR)
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146 | #define SCEMR_7 (SCIF7.SCEMR)
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147 |
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148 |
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149 | typedef struct st_scif
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150 | {
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151 | /* SCIF */
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152 | volatile uint16_t SCSMR; /* SCSMR */
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153 | volatile uint8_t dummy1[2]; /* */
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154 | volatile uint8_t SCBRR; /* SCBRR */
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155 | volatile uint8_t dummy2[3]; /* */
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156 | volatile uint16_t SCSCR; /* SCSCR */
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157 | volatile uint8_t dummy3[2]; /* */
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158 | volatile uint8_t SCFTDR; /* SCFTDR */
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159 | volatile uint8_t dummy4[3]; /* */
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160 | volatile uint16_t SCFSR; /* SCFSR */
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161 | volatile uint8_t dummy5[2]; /* */
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162 | volatile uint8_t SCFRDR; /* SCFRDR */
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163 | volatile uint8_t dummy6[3]; /* */
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164 | volatile uint16_t SCFCR; /* SCFCR */
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165 | volatile uint8_t dummy7[2]; /* */
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166 | volatile uint16_t SCFDR; /* SCFDR */
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167 | volatile uint8_t dummy8[2]; /* */
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168 | volatile uint16_t SCSPTR; /* SCSPTR */
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169 | volatile uint8_t dummy9[2]; /* */
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170 | volatile uint16_t SCLSR; /* SCLSR */
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171 | volatile uint8_t dummy10[2]; /* */
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172 | volatile uint16_t SCEMR; /* SCEMR */
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173 | } r_io_scif_t;
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174 |
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175 |
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176 | /* Channel array defines of SCIF (2)*/
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177 | #ifdef DECLARE_SCIF_CHANNELS
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178 | volatile struct st_scif* SCIF[ SCIF_COUNT ] =
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179 | /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */
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180 | SCIF_ADDRESS_LIST;
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181 | /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */
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182 | #endif /* DECLARE_SCIF_CHANNELS */
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183 | /* End of channel array defines of SCIF (2)*/
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184 |
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185 |
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186 | /* <-SEC M1.10.1 */
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187 | /* <-MISRA 18.4 */ /* <-SEC M1.6.2 */
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188 | /* <-QAC 0857 */
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189 | /* <-QAC 0639 */
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190 | #endif
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