source: asp3_tinet_ecnl_arm/trunk/asp3_dcre/mbed/targets/TARGET_RENESAS/TARGET_RZA1XX/TARGET_RZ_A1H/device/inc/iodefines/rtc_iodefine.h@ 374

Last change on this file since 374 was 374, checked in by coas-nagasima, 5 years ago

mbed関連を更新
シリアルドライバをmbedのHALを使うよう変更
ファイルディスクリプタの処理を更新
  • Property svn:eol-style set to native
  • Property svn:mime-type set to text/x-chdr;charset=UTF-8
File size: 6.1 KB
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1/*******************************************************************************
2* DISCLAIMER
3* This software is supplied by Renesas Electronics Corporation and is only
4* intended for use with Renesas products. No other uses are authorized. This
5* software is owned by Renesas Electronics Corporation and is protected under
6* all applicable laws, including copyright laws.
7* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
8* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
9* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
10* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
11* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
12* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
13* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
14* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
15* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
16* Renesas reserves the right, without notice, to make changes to this software
17* and to discontinue the availability of this software. By using this software,
18* you agree to the additional terms and conditions found by accessing the
19* following link:
20* http://www.renesas.com/disclaimer*
21* Copyright (C) 2013-2015 Renesas Electronics Corporation. All rights reserved.
22*******************************************************************************/
23/*******************************************************************************
24* File Name : rtc_iodefine.h
25* $Rev: $
26* $Date:: $
27* Description : Definition of I/O Register for RZ/A1H,M (V2.00h)
28******************************************************************************/
29#ifndef RTC_IODEFINE_H
30#define RTC_IODEFINE_H
31/* ->QAC 0639 : Over 127 members (C90) */
32/* ->QAC 0857 : Over 1024 #define (C90) */
33/* ->MISRA 18.4 : Pack unpack union */ /* ->SEC M1.6.2 */
34/* ->SEC M1.10.1 : Not magic number */
35
36#define RTC (*(struct st_rtc *)0xFCFF1000uL) /* RTC */
37
38
39#define RTCR64CNT (RTC.R64CNT)
40#define RTCRSECCNT (RTC.RSECCNT)
41#define RTCRMINCNT (RTC.RMINCNT)
42#define RTCRHRCNT (RTC.RHRCNT)
43#define RTCRWKCNT (RTC.RWKCNT)
44#define RTCRDAYCNT (RTC.RDAYCNT)
45#define RTCRMONCNT (RTC.RMONCNT)
46#define RTCRYRCNT (RTC.RYRCNT)
47#define RTCRSECAR (RTC.RSECAR)
48#define RTCRMINAR (RTC.RMINAR)
49#define RTCRHRAR (RTC.RHRAR)
50#define RTCRWKAR (RTC.RWKAR)
51#define RTCRDAYAR (RTC.RDAYAR)
52#define RTCRMONAR (RTC.RMONAR)
53#define RTCRCR1 (RTC.RCR1)
54#define RTCRCR2 (RTC.RCR2)
55#define RTCRYRAR (RTC.RYRAR)
56#define RTCRCR3 (RTC.RCR3)
57#define RTCRCR5 (RTC.RCR5)
58#define RTCRFRH (RTC.RFRH)
59#define RTCRFRL (RTC.RFRL)
60
61
62typedef struct st_rtc
63{
64 /* RTC */
65 volatile uint8_t R64CNT; /* R64CNT */
66 volatile uint8_t dummy537[1]; /* */
67 volatile uint8_t RSECCNT; /* RSECCNT */
68 volatile uint8_t dummy538[1]; /* */
69 volatile uint8_t RMINCNT; /* RMINCNT */
70 volatile uint8_t dummy539[1]; /* */
71 volatile uint8_t RHRCNT; /* RHRCNT */
72 volatile uint8_t dummy540[1]; /* */
73 volatile uint8_t RWKCNT; /* RWKCNT */
74 volatile uint8_t dummy541[1]; /* */
75 volatile uint8_t RDAYCNT; /* RDAYCNT */
76 volatile uint8_t dummy542[1]; /* */
77 volatile uint8_t RMONCNT; /* RMONCNT */
78 volatile uint8_t dummy543[1]; /* */
79 volatile uint16_t RYRCNT; /* RYRCNT */
80 volatile uint8_t RSECAR; /* RSECAR */
81 volatile uint8_t dummy544[1]; /* */
82 volatile uint8_t RMINAR; /* RMINAR */
83 volatile uint8_t dummy545[1]; /* */
84 volatile uint8_t RHRAR; /* RHRAR */
85 volatile uint8_t dummy546[1]; /* */
86 volatile uint8_t RWKAR; /* RWKAR */
87 volatile uint8_t dummy547[1]; /* */
88 volatile uint8_t RDAYAR; /* RDAYAR */
89 volatile uint8_t dummy548[1]; /* */
90 volatile uint8_t RMONAR; /* RMONAR */
91 volatile uint8_t dummy549[1]; /* */
92 volatile uint8_t RCR1; /* RCR1 */
93 volatile uint8_t dummy550[1]; /* */
94 volatile uint8_t RCR2; /* RCR2 */
95 volatile uint8_t dummy551[1]; /* */
96 volatile uint16_t RYRAR; /* RYRAR */
97 volatile uint8_t dummy552[2]; /* */
98 volatile uint8_t RCR3; /* RCR3 */
99 volatile uint8_t dummy553[1]; /* */
100 volatile uint8_t RCR5; /* RCR5 */
101 volatile uint8_t dummy554[3]; /* */
102 volatile uint16_t RFRH; /* RFRH */
103 volatile uint16_t RFRL; /* RFRL */
104} r_io_rtc_t;
105
106
107/* <-SEC M1.10.1 */
108/* <-MISRA 18.4 */ /* <-SEC M1.6.2 */
109/* <-QAC 0857 */
110/* <-QAC 0639 */
111#endif
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