source: asp3_tinet_ecnl_arm/trunk/asp3_dcre/mbed/targets/TARGET_RENESAS/TARGET_RZA1XX/TARGET_RZ_A1H/device/inc/iodefines/romdec_iodefine.h@ 374

Last change on this file since 374 was 374, checked in by coas-nagasima, 5 years ago

mbed関連を更新
シリアルドライバをmbedのHALを使うよう変更
ファイルディスクリプタの処理を更新
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  • Property svn:mime-type set to text/x-chdr;charset=UTF-8
File size: 10.1 KB
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1/*******************************************************************************
2* DISCLAIMER
3* This software is supplied by Renesas Electronics Corporation and is only
4* intended for use with Renesas products. No other uses are authorized. This
5* software is owned by Renesas Electronics Corporation and is protected under
6* all applicable laws, including copyright laws.
7* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
8* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
9* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
10* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
11* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
12* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
13* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
14* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
15* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
16* Renesas reserves the right, without notice, to make changes to this software
17* and to discontinue the availability of this software. By using this software,
18* you agree to the additional terms and conditions found by accessing the
19* following link:
20* http://www.renesas.com/disclaimer*
21* Copyright (C) 2013-2015 Renesas Electronics Corporation. All rights reserved.
22*******************************************************************************/
23/*******************************************************************************
24* File Name : romdec_iodefine.h
25* $Rev: $
26* $Date:: $
27* Description : Definition of I/O Register for RZ/A1H,M (V2.00h)
28******************************************************************************/
29#ifndef ROMDEC_IODEFINE_H
30#define ROMDEC_IODEFINE_H
31/* ->QAC 0639 : Over 127 members (C90) */
32/* ->QAC 0857 : Over 1024 #define (C90) */
33/* ->MISRA 18.4 : Pack unpack union */ /* ->SEC M1.6.2 */
34/* ->SEC M1.10.1 : Not magic number */
35
36#define ROMDEC (*(struct st_romdec *)0xE8005000uL) /* ROMDEC */
37
38
39#define ROMDECCROMEN (ROMDEC.CROMEN)
40#define ROMDECCROMSY0 (ROMDEC.CROMSY0)
41#define ROMDECCROMCTL0 (ROMDEC.CROMCTL0)
42#define ROMDECCROMCTL1 (ROMDEC.CROMCTL1)
43#define ROMDECCROMCTL3 (ROMDEC.CROMCTL3)
44#define ROMDECCROMCTL4 (ROMDEC.CROMCTL4)
45#define ROMDECCROMCTL5 (ROMDEC.CROMCTL5)
46#define ROMDECCROMST0 (ROMDEC.CROMST0)
47#define ROMDECCROMST1 (ROMDEC.CROMST1)
48#define ROMDECCROMST3 (ROMDEC.CROMST3)
49#define ROMDECCROMST4 (ROMDEC.CROMST4)
50#define ROMDECCROMST5 (ROMDEC.CROMST5)
51#define ROMDECCROMST6 (ROMDEC.CROMST6)
52#define ROMDECCBUFST0 (ROMDEC.CBUFST0)
53#define ROMDECCBUFST1 (ROMDEC.CBUFST1)
54#define ROMDECCBUFST2 (ROMDEC.CBUFST2)
55#define ROMDECHEAD00 (ROMDEC.HEAD00)
56#define ROMDECHEAD01 (ROMDEC.HEAD01)
57#define ROMDECHEAD02 (ROMDEC.HEAD02)
58#define ROMDECHEAD03 (ROMDEC.HEAD03)
59#define ROMDECSHEAD00 (ROMDEC.SHEAD00)
60#define ROMDECSHEAD01 (ROMDEC.SHEAD01)
61#define ROMDECSHEAD02 (ROMDEC.SHEAD02)
62#define ROMDECSHEAD03 (ROMDEC.SHEAD03)
63#define ROMDECSHEAD04 (ROMDEC.SHEAD04)
64#define ROMDECSHEAD05 (ROMDEC.SHEAD05)
65#define ROMDECSHEAD06 (ROMDEC.SHEAD06)
66#define ROMDECSHEAD07 (ROMDEC.SHEAD07)
67#define ROMDECHEAD20 (ROMDEC.HEAD20)
68#define ROMDECHEAD21 (ROMDEC.HEAD21)
69#define ROMDECHEAD22 (ROMDEC.HEAD22)
70#define ROMDECHEAD23 (ROMDEC.HEAD23)
71#define ROMDECSHEAD20 (ROMDEC.SHEAD20)
72#define ROMDECSHEAD21 (ROMDEC.SHEAD21)
73#define ROMDECSHEAD22 (ROMDEC.SHEAD22)
74#define ROMDECSHEAD23 (ROMDEC.SHEAD23)
75#define ROMDECSHEAD24 (ROMDEC.SHEAD24)
76#define ROMDECSHEAD25 (ROMDEC.SHEAD25)
77#define ROMDECSHEAD26 (ROMDEC.SHEAD26)
78#define ROMDECSHEAD27 (ROMDEC.SHEAD27)
79#define ROMDECCBUFCTL0 (ROMDEC.CBUFCTL0)
80#define ROMDECCBUFCTL1 (ROMDEC.CBUFCTL1)
81#define ROMDECCBUFCTL2 (ROMDEC.CBUFCTL2)
82#define ROMDECCBUFCTL3 (ROMDEC.CBUFCTL3)
83#define ROMDECCROMST0M (ROMDEC.CROMST0M)
84#define ROMDECROMDECRST (ROMDEC.ROMDECRST)
85#define ROMDECRSTSTAT (ROMDEC.RSTSTAT)
86#define ROMDECSSI (ROMDEC.SSI)
87#define ROMDECINTHOLD (ROMDEC.INTHOLD)
88#define ROMDECINHINT (ROMDEC.INHINT)
89#define ROMDECSTRMDIN0 (ROMDEC.STRMDIN0)
90#define ROMDECSTRMDIN2 (ROMDEC.STRMDIN2)
91#define ROMDECSTRMDOUT0 (ROMDEC.STRMDOUT0)
92
93#define ROMDEC_CROMCTL0_COUNT (2)
94#define ROMDEC_CROMST0_COUNT (2)
95#define ROMDEC_CBUFST0_COUNT (3)
96#define ROMDEC_HEAD00_COUNT (4)
97#define ROMDEC_SHEAD00_COUNT (8)
98#define ROMDEC_HEAD20_COUNT (4)
99#define ROMDEC_SHEAD20_COUNT (8)
100#define ROMDEC_CBUFCTL0_COUNT (4)
101#define ROMDEC_STRMDIN0_COUNT (2)
102
103
104typedef struct st_romdec
105{
106 /* ROMDEC */
107 volatile uint8_t CROMEN; /* CROMEN */
108 volatile uint8_t CROMSY0; /* CROMSY0 */
109
110/* #define ROMDEC_CROMCTL0_COUNT (2) */
111 volatile uint8_t CROMCTL0; /* CROMCTL0 */
112 volatile uint8_t CROMCTL1; /* CROMCTL1 */
113 volatile uint8_t dummy23[1]; /* */
114 volatile uint8_t CROMCTL3; /* CROMCTL3 */
115 volatile uint8_t CROMCTL4; /* CROMCTL4 */
116 volatile uint8_t CROMCTL5; /* CROMCTL5 */
117
118/* #define ROMDEC_CROMST0_COUNT (2) */
119 volatile uint8_t CROMST0; /* CROMST0 */
120 volatile uint8_t CROMST1; /* CROMST1 */
121 volatile uint8_t dummy24[1]; /* */
122 volatile uint8_t CROMST3; /* CROMST3 */
123 volatile uint8_t CROMST4; /* CROMST4 */
124 volatile uint8_t CROMST5; /* CROMST5 */
125 volatile uint8_t CROMST6; /* CROMST6 */
126 volatile uint8_t dummy25[5]; /* */
127
128/* #define ROMDEC_CBUFST0_COUNT (3) */
129 volatile uint8_t CBUFST0; /* CBUFST0 */
130 volatile uint8_t CBUFST1; /* CBUFST1 */
131 volatile uint8_t CBUFST2; /* CBUFST2 */
132 volatile uint8_t dummy26[1]; /* */
133
134/* #define ROMDEC_HEAD00_COUNT (4) */
135 volatile uint8_t HEAD00; /* HEAD00 */
136 volatile uint8_t HEAD01; /* HEAD01 */
137 volatile uint8_t HEAD02; /* HEAD02 */
138 volatile uint8_t HEAD03; /* HEAD03 */
139
140/* #define ROMDEC_SHEAD00_COUNT (8) */
141 volatile uint8_t SHEAD00; /* SHEAD00 */
142 volatile uint8_t SHEAD01; /* SHEAD01 */
143 volatile uint8_t SHEAD02; /* SHEAD02 */
144 volatile uint8_t SHEAD03; /* SHEAD03 */
145 volatile uint8_t SHEAD04; /* SHEAD04 */
146 volatile uint8_t SHEAD05; /* SHEAD05 */
147 volatile uint8_t SHEAD06; /* SHEAD06 */
148 volatile uint8_t SHEAD07; /* SHEAD07 */
149
150/* #define ROMDEC_HEAD20_COUNT (4) */
151 volatile uint8_t HEAD20; /* HEAD20 */
152 volatile uint8_t HEAD21; /* HEAD21 */
153 volatile uint8_t HEAD22; /* HEAD22 */
154 volatile uint8_t HEAD23; /* HEAD23 */
155
156/* #define ROMDEC_SHEAD20_COUNT (8) */
157 volatile uint8_t SHEAD20; /* SHEAD20 */
158 volatile uint8_t SHEAD21; /* SHEAD21 */
159 volatile uint8_t SHEAD22; /* SHEAD22 */
160 volatile uint8_t SHEAD23; /* SHEAD23 */
161 volatile uint8_t SHEAD24; /* SHEAD24 */
162 volatile uint8_t SHEAD25; /* SHEAD25 */
163 volatile uint8_t SHEAD26; /* SHEAD26 */
164 volatile uint8_t SHEAD27; /* SHEAD27 */
165 volatile uint8_t dummy27[16]; /* */
166
167/* #define ROMDEC_CBUFCTL0_COUNT (4) */
168 volatile uint8_t CBUFCTL0; /* CBUFCTL0 */
169 volatile uint8_t CBUFCTL1; /* CBUFCTL1 */
170 volatile uint8_t CBUFCTL2; /* CBUFCTL2 */
171 volatile uint8_t CBUFCTL3; /* CBUFCTL3 */
172 volatile uint8_t dummy28[1]; /* */
173 volatile uint8_t CROMST0M; /* CROMST0M */
174 volatile uint8_t dummy29[186]; /* */
175 volatile uint8_t ROMDECRST; /* ROMDECRST */
176 volatile uint8_t RSTSTAT; /* RSTSTAT */
177 volatile uint8_t SSI; /* SSI */
178 volatile uint8_t dummy30[5]; /* */
179 volatile uint8_t INTHOLD; /* INTHOLD */
180 volatile uint8_t INHINT; /* INHINT */
181 volatile uint8_t dummy31[246]; /* */
182
183/* #define ROMDEC_STRMDIN0_COUNT (2) */
184 volatile uint16_t STRMDIN0; /* STRMDIN0 */
185 volatile uint16_t STRMDIN2; /* STRMDIN2 */
186 volatile uint16_t STRMDOUT0; /* STRMDOUT0 */
187} r_io_romdec_t;
188
189
190/* <-SEC M1.10.1 */
191/* <-MISRA 18.4 */ /* <-SEC M1.6.2 */
192/* <-QAC 0857 */
193/* <-QAC 0639 */
194#endif
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