source: asp3_tinet_ecnl_arm/trunk/asp3_dcre/mbed/targets/TARGET_RENESAS/TARGET_RZA1XX/TARGET_RZ_A1H/device/inc/iodefines/pwm_iodefine.h@ 374

Last change on this file since 374 was 374, checked in by coas-nagasima, 5 years ago

mbed関連を更新
シリアルドライバをmbedのHALを使うよう変更
ファイルディスクリプタの処理を更新
  • Property svn:eol-style set to native
  • Property svn:mime-type set to text/x-chdr;charset=UTF-8
File size: 6.2 KB
Line 
1/*******************************************************************************
2* DISCLAIMER
3* This software is supplied by Renesas Electronics Corporation and is only
4* intended for use with Renesas products. No other uses are authorized. This
5* software is owned by Renesas Electronics Corporation and is protected under
6* all applicable laws, including copyright laws.
7* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
8* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
9* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
10* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
11* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
12* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
13* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
14* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
15* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
16* Renesas reserves the right, without notice, to make changes to this software
17* and to discontinue the availability of this software. By using this software,
18* you agree to the additional terms and conditions found by accessing the
19* following link:
20* http://www.renesas.com/disclaimer*
21* Copyright (C) 2013-2015 Renesas Electronics Corporation. All rights reserved.
22*******************************************************************************/
23/*******************************************************************************
24* File Name : pwm_iodefine.h
25* $Rev: $
26* $Date:: $
27* Description : Definition of I/O Register for RZ/A1H,M (V2.00h)
28******************************************************************************/
29#ifndef PWM_IODEFINE_H
30#define PWM_IODEFINE_H
31/* ->QAC 0639 : Over 127 members (C90) */
32/* ->QAC 0857 : Over 1024 #define (C90) */
33/* ->MISRA 18.4 : Pack unpack union */ /* ->SEC M1.6.2 */
34/* ->SEC M1.10.1 : Not magic number */
35
36#define PWM (*(struct st_pwm *)0xFCFF5004uL) /* PWM */
37
38
39/* Start of channel array defines of PWM */
40
41/* Channel array defines of PWMn */
42/*(Sample) value = PWMn[ channel ]->PWCR_1; */
43#define PWMn_COUNT (2)
44#define PWMn_ADDRESS_LIST \
45{ /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \
46 &PWM1, &PWM2 \
47} /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */
48#define PWM1 (*(struct st_pwm_common *)&PWM.PWCR_1) /* PWM1 */
49#define PWM2 (*(struct st_pwm_common *)&PWM.PWCR_2) /* PWM2 */
50
51/* End of channel array defines of PWM */
52
53
54#define PWMPWBTCR (PWM.PWBTCR)
55#define PWMPWCR_1 (PWM.PWCR_1)
56#define PWMPWPR_1 (PWM.PWPR_1)
57#define PWMPWCYR_1 (PWM.PWCYR_1)
58#define PWMPWBFR_1A (PWM.PWBFR_1A)
59#define PWMPWBFR_1C (PWM.PWBFR_1C)
60#define PWMPWBFR_1E (PWM.PWBFR_1E)
61#define PWMPWBFR_1G (PWM.PWBFR_1G)
62#define PWMPWCR_2 (PWM.PWCR_2)
63#define PWMPWPR_2 (PWM.PWPR_2)
64#define PWMPWCYR_2 (PWM.PWCYR_2)
65#define PWMPWBFR_2A (PWM.PWBFR_2A)
66#define PWMPWBFR_2C (PWM.PWBFR_2C)
67#define PWMPWBFR_2E (PWM.PWBFR_2E)
68#define PWMPWBFR_2G (PWM.PWBFR_2G)
69
70
71typedef struct st_pwm
72{
73 /* PWM */
74 volatile uint8_t dummy559[2]; /* */
75 volatile uint8_t PWBTCR; /* PWBTCR */
76 volatile uint8_t dummy560[217]; /* */
77
78/* start of struct st_pwm_common */
79 volatile uint8_t PWCR_1; /* PWCR_1 */
80 volatile uint8_t dummy561[3]; /* */
81 volatile uint8_t PWPR_1; /* PWPR_1 */
82 volatile uint8_t dummy562[1]; /* */
83 volatile uint16_t PWCYR_1; /* PWCYR_1 */
84 volatile uint16_t PWBFR_1A; /* PWBFR_1A */
85 volatile uint16_t PWBFR_1C; /* PWBFR_1C */
86 volatile uint16_t PWBFR_1E; /* PWBFR_1E */
87 volatile uint16_t PWBFR_1G; /* PWBFR_1G */
88
89/* end of struct st_pwm_common */
90
91/* start of struct st_pwm_common */
92 volatile uint8_t PWCR_2; /* PWCR_2 */
93 volatile uint8_t dummy563[3]; /* */
94 volatile uint8_t PWPR_2; /* PWPR_2 */
95 volatile uint8_t dummy564[1]; /* */
96 volatile uint16_t PWCYR_2; /* PWCYR_2 */
97 volatile uint16_t PWBFR_2A; /* PWBFR_2A */
98 volatile uint16_t PWBFR_2C; /* PWBFR_2C */
99 volatile uint16_t PWBFR_2E; /* PWBFR_2E */
100 volatile uint16_t PWBFR_2G; /* PWBFR_2G */
101
102/* end of struct st_pwm_common */
103} r_io_pwm_t;
104
105
106typedef struct st_pwm_common
107{
108
109 volatile uint8_t PWCR_1; /* PWCR_1 */
110 volatile uint8_t dummy562[3]; /* */
111 volatile uint8_t PWPR_1; /* PWPR_1 */
112 volatile uint8_t dummy563[1]; /* */
113 volatile uint16_t PWCYR_1; /* PWCYR_1 */
114 volatile uint16_t PWBFR_1A; /* PWBFR_1A */
115 volatile uint16_t PWBFR_1C; /* PWBFR_1C */
116 volatile uint16_t PWBFR_1E; /* PWBFR_1E */
117 volatile uint16_t PWBFR_1G; /* PWBFR_1G */
118} r_io_pwm_common_t;
119
120
121/* Channel array defines of PWMn (2)*/
122#ifdef DECLARE_PWMn_CHANNELS
123volatile struct st_pwm_common* PWMn[ PWMn_COUNT ] =
124 /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */
125 PWMn_ADDRESS_LIST;
126 /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */
127#endif /* DECLARE_PWMn_CHANNELS */
128/* End of channel array defines of PWMn (2)*/
129
130
131/* <-SEC M1.10.1 */
132/* <-MISRA 18.4 */ /* <-SEC M1.6.2 */
133/* <-QAC 0857 */
134/* <-QAC 0639 */
135#endif
Note: See TracBrowser for help on using the repository browser.