source: asp3_tinet_ecnl_arm/trunk/asp3_dcre/mbed/targets/TARGET_RENESAS/TARGET_RZA1XX/TARGET_RZ_A1H/device/inc/iodefines/mmc_iodefine.h@ 374

Last change on this file since 374 was 374, checked in by coas-nagasima, 5 years ago

mbed関連を更新
シリアルドライバをmbedのHALを使うよう変更
ファイルディスクリプタの処理を更新
  • Property svn:eol-style set to native
  • Property svn:mime-type set to text/x-chdr;charset=UTF-8
File size: 5.4 KB
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1/*******************************************************************************
2* DISCLAIMER
3* This software is supplied by Renesas Electronics Corporation and is only
4* intended for use with Renesas products. No other uses are authorized. This
5* software is owned by Renesas Electronics Corporation and is protected under
6* all applicable laws, including copyright laws.
7* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
8* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
9* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
10* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
11* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
12* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
13* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
14* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
15* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
16* Renesas reserves the right, without notice, to make changes to this software
17* and to discontinue the availability of this software. By using this software,
18* you agree to the additional terms and conditions found by accessing the
19* following link:
20* http://www.renesas.com/disclaimer*
21* Copyright (C) 2013-2015 Renesas Electronics Corporation. All rights reserved.
22*******************************************************************************/
23/*******************************************************************************
24* File Name : mmc_iodefine.h
25* $Rev: $
26* $Date:: $
27* Description : Definition of I/O Register for RZ/A1H,M (V2.00h)
28******************************************************************************/
29#ifndef MMC_IODEFINE_H
30#define MMC_IODEFINE_H
31/* ->QAC 0639 : Over 127 members (C90) */
32/* ->QAC 0857 : Over 1024 #define (C90) */
33/* ->MISRA 18.4 : Pack unpack union */ /* ->SEC M1.6.2 */
34/* ->SEC M1.10.1 : Not magic number */
35
36#define MMC (*(struct st_mmc *)0xE804C800uL) /* MMC */
37
38
39#define MMCCE_CMD_SETH (MMC.CE_CMD_SETH)
40#define MMCCE_CMD_SETL (MMC.CE_CMD_SETL)
41#define MMCCE_ARG (MMC.CE_ARG)
42#define MMCCE_ARG_CMD12 (MMC.CE_ARG_CMD12)
43#define MMCCE_CMD_CTRL (MMC.CE_CMD_CTRL)
44#define MMCCE_BLOCK_SET (MMC.CE_BLOCK_SET)
45#define MMCCE_CLK_CTRL (MMC.CE_CLK_CTRL)
46#define MMCCE_BUF_ACC (MMC.CE_BUF_ACC)
47#define MMCCE_RESP3 (MMC.CE_RESP3)
48#define MMCCE_RESP2 (MMC.CE_RESP2)
49#define MMCCE_RESP1 (MMC.CE_RESP1)
50#define MMCCE_RESP0 (MMC.CE_RESP0)
51#define MMCCE_RESP_CMD12 (MMC.CE_RESP_CMD12)
52#define MMCCE_DATA (MMC.CE_DATA)
53#define MMCCE_INT (MMC.CE_INT)
54#define MMCCE_INT_EN (MMC.CE_INT_EN)
55#define MMCCE_HOST_STS1 (MMC.CE_HOST_STS1)
56#define MMCCE_HOST_STS2 (MMC.CE_HOST_STS2)
57#define MMCCE_DMA_MODE (MMC.CE_DMA_MODE)
58#define MMCCE_DETECT (MMC.CE_DETECT)
59#define MMCCE_ADD_MODE (MMC.CE_ADD_MODE)
60#define MMCCE_VERSION (MMC.CE_VERSION)
61
62#define MMC_CE_RESPn_COUNT (4)
63
64
65typedef struct st_mmc
66{
67 /* MMC */
68 volatile uint16_t CE_CMD_SETH; /* CE_CMD_SETH */
69 volatile uint16_t CE_CMD_SETL; /* CE_CMD_SETL */
70 volatile uint8_t dummy182[4]; /* */
71 volatile uint32_t CE_ARG; /* CE_ARG */
72 volatile uint32_t CE_ARG_CMD12; /* CE_ARG_CMD12 */
73 volatile uint32_t CE_CMD_CTRL; /* CE_CMD_CTRL */
74 volatile uint32_t CE_BLOCK_SET; /* CE_BLOCK_SET */
75 volatile uint32_t CE_CLK_CTRL; /* CE_CLK_CTRL */
76 volatile uint32_t CE_BUF_ACC; /* CE_BUF_ACC */
77
78/* #define MMC_CE_RESPn_COUNT (4) */
79 volatile uint32_t CE_RESP3; /* CE_RESP3 */
80 volatile uint32_t CE_RESP2; /* CE_RESP2 */
81 volatile uint32_t CE_RESP1; /* CE_RESP1 */
82 volatile uint32_t CE_RESP0; /* CE_RESP0 */
83 volatile uint32_t CE_RESP_CMD12; /* CE_RESP_CMD12 */
84 volatile uint32_t CE_DATA; /* CE_DATA */
85 volatile uint8_t dummy183[8]; /* */
86 volatile uint32_t CE_INT; /* CE_INT */
87 volatile uint32_t CE_INT_EN; /* CE_INT_EN */
88 volatile uint32_t CE_HOST_STS1; /* CE_HOST_STS1 */
89 volatile uint32_t CE_HOST_STS2; /* CE_HOST_STS2 */
90 volatile uint8_t dummy184[12]; /* */
91 volatile uint32_t CE_DMA_MODE; /* CE_DMA_MODE */
92 volatile uint8_t dummy185[16]; /* */
93 volatile uint32_t CE_DETECT; /* CE_DETECT */
94 volatile uint32_t CE_ADD_MODE; /* CE_ADD_MODE */
95 volatile uint8_t dummy186[4]; /* */
96 volatile uint32_t CE_VERSION; /* CE_VERSION */
97} r_io_mmc_t;
98
99
100/* <-SEC M1.10.1 */
101/* <-MISRA 18.4 */ /* <-SEC M1.6.2 */
102/* <-QAC 0857 */
103/* <-QAC 0639 */
104#endif
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