source: asp3_tinet_ecnl_arm/trunk/asp3_dcre/mbed/targets/TARGET_RENESAS/TARGET_RZA1XX/TARGET_RZ_A1H/device/inc/iodefines/l2c_iodefine.h@ 374

Last change on this file since 374 was 374, checked in by coas-nagasima, 5 years ago

mbed関連を更新
シリアルドライバをmbedのHALを使うよう変更
ファイルディスクリプタの処理を更新
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1/*******************************************************************************
2* DISCLAIMER
3* This software is supplied by Renesas Electronics Corporation and is only
4* intended for use with Renesas products. No other uses are authorized. This
5* software is owned by Renesas Electronics Corporation and is protected under
6* all applicable laws, including copyright laws.
7* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
8* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
9* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
10* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
11* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
12* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
13* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
14* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
15* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
16* Renesas reserves the right, without notice, to make changes to this software
17* and to discontinue the availability of this software. By using this software,
18* you agree to the additional terms and conditions found by accessing the
19* following link:
20* http://www.renesas.com/disclaimer*
21* Copyright (C) 2013-2015 Renesas Electronics Corporation. All rights reserved.
22*******************************************************************************/
23/*******************************************************************************
24* File Name : l2c_iodefine.h
25* $Rev: $
26* $Date:: $
27* Description : Definition of I/O Register for RZ/A1H,M (V2.00h)
28******************************************************************************/
29#ifndef L2C_IODEFINE_H
30#define L2C_IODEFINE_H
31/* ->QAC 0639 : Over 127 members (C90) */
32/* ->QAC 0857 : Over 1024 #define (C90) */
33/* ->MISRA 18.4 : Pack unpack union */ /* ->SEC M1.6.2 */
34/* ->SEC M1.10.1 : Not magic number */
35
36#define L2C (*(struct st_l2c *)0x3FFFF000uL) /* L2C */
37
38
39/* Start of channel array defines of L2C */
40
41/* Channel array defines of L2C_FROM_REG9_D_LOCKDOWN0_ARRAY */
42/*(Sample) value = L2C_FROM_REG9_D_LOCKDOWN0_ARRAY[ channel ]->REG9_D_LOCKDOWN0; */
43#define L2C_FROM_REG9_D_LOCKDOWN0_ARRAY_COUNT (8)
44#define L2C_FROM_REG9_D_LOCKDOWN0_ARRAY_ADDRESS_LIST \
45{ /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \
46 &L2C_FROM_REG9_D_LOCKDOWN0, &L2C_FROM_REG9_D_LOCKDOWN1, &L2C_FROM_REG9_D_LOCKDOWN2, &L2C_FROM_REG9_D_LOCKDOWN3, &L2C_FROM_REG9_D_LOCKDOWN4, &L2C_FROM_REG9_D_LOCKDOWN5, &L2C_FROM_REG9_D_LOCKDOWN6, &L2C_FROM_REG9_D_LOCKDOWN7 \
47} /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */
48#define L2C_FROM_REG9_D_LOCKDOWN0 (*(struct st_l2c_from_reg9_d_lockdown0 *)&L2C.REG9_D_LOCKDOWN0) /* L2C_FROM_REG9_D_LOCKDOWN0 */
49#define L2C_FROM_REG9_D_LOCKDOWN1 (*(struct st_l2c_from_reg9_d_lockdown0 *)&L2C.REG9_D_LOCKDOWN1) /* L2C_FROM_REG9_D_LOCKDOWN1 */
50#define L2C_FROM_REG9_D_LOCKDOWN2 (*(struct st_l2c_from_reg9_d_lockdown0 *)&L2C.REG9_D_LOCKDOWN2) /* L2C_FROM_REG9_D_LOCKDOWN2 */
51#define L2C_FROM_REG9_D_LOCKDOWN3 (*(struct st_l2c_from_reg9_d_lockdown0 *)&L2C.REG9_D_LOCKDOWN3) /* L2C_FROM_REG9_D_LOCKDOWN3 */
52#define L2C_FROM_REG9_D_LOCKDOWN4 (*(struct st_l2c_from_reg9_d_lockdown0 *)&L2C.REG9_D_LOCKDOWN4) /* L2C_FROM_REG9_D_LOCKDOWN4 */
53#define L2C_FROM_REG9_D_LOCKDOWN5 (*(struct st_l2c_from_reg9_d_lockdown0 *)&L2C.REG9_D_LOCKDOWN5) /* L2C_FROM_REG9_D_LOCKDOWN5 */
54#define L2C_FROM_REG9_D_LOCKDOWN6 (*(struct st_l2c_from_reg9_d_lockdown0 *)&L2C.REG9_D_LOCKDOWN6) /* L2C_FROM_REG9_D_LOCKDOWN6 */
55#define L2C_FROM_REG9_D_LOCKDOWN7 (*(struct st_l2c_from_reg9_d_lockdown0 *)&L2C.REG9_D_LOCKDOWN7) /* L2C_FROM_REG9_D_LOCKDOWN7 */
56
57/* End of channel array defines of L2C */
58
59
60#define L2CREG0_CACHE_ID (L2C.REG0_CACHE_ID)
61#define L2CREG0_CACHE_TYPE (L2C.REG0_CACHE_TYPE)
62#define L2CREG1_CONTROL (L2C.REG1_CONTROL)
63#define L2CREG1_AUX_CONTROL (L2C.REG1_AUX_CONTROL)
64#define L2CREG1_TAG_RAM_CONTROL (L2C.REG1_TAG_RAM_CONTROL)
65#define L2CREG1_DATA_RAM_CONTROL (L2C.REG1_DATA_RAM_CONTROL)
66#define L2CREG2_EV_COUNTER_CTRL (L2C.REG2_EV_COUNTER_CTRL)
67#define L2CREG2_EV_COUNTER1_CFG (L2C.REG2_EV_COUNTER1_CFG)
68#define L2CREG2_EV_COUNTER0_CFG (L2C.REG2_EV_COUNTER0_CFG)
69#define L2CREG2_EV_COUNTER1 (L2C.REG2_EV_COUNTER1)
70#define L2CREG2_EV_COUNTER0 (L2C.REG2_EV_COUNTER0)
71#define L2CREG2_INT_MASK (L2C.REG2_INT_MASK)
72#define L2CREG2_INT_MASK_STATUS (L2C.REG2_INT_MASK_STATUS)
73#define L2CREG2_INT_RAW_STATUS (L2C.REG2_INT_RAW_STATUS)
74#define L2CREG2_INT_CLEAR (L2C.REG2_INT_CLEAR)
75#define L2CREG7_CACHE_SYNC (L2C.REG7_CACHE_SYNC)
76#define L2CREG7_INV_PA (L2C.REG7_INV_PA)
77#define L2CREG7_INV_WAY (L2C.REG7_INV_WAY)
78#define L2CREG7_CLEAN_PA (L2C.REG7_CLEAN_PA)
79#define L2CREG7_CLEAN_INDEX (L2C.REG7_CLEAN_INDEX)
80#define L2CREG7_CLEAN_WAY (L2C.REG7_CLEAN_WAY)
81#define L2CREG7_CLEAN_INV_PA (L2C.REG7_CLEAN_INV_PA)
82#define L2CREG7_CLEAN_INV_INDEX (L2C.REG7_CLEAN_INV_INDEX)
83#define L2CREG7_CLEAN_INV_WAY (L2C.REG7_CLEAN_INV_WAY)
84#define L2CREG9_D_LOCKDOWN0 (L2C.REG9_D_LOCKDOWN0)
85#define L2CREG9_I_LOCKDOWN0 (L2C.REG9_I_LOCKDOWN0)
86#define L2CREG9_D_LOCKDOWN1 (L2C.REG9_D_LOCKDOWN1)
87#define L2CREG9_I_LOCKDOWN1 (L2C.REG9_I_LOCKDOWN1)
88#define L2CREG9_D_LOCKDOWN2 (L2C.REG9_D_LOCKDOWN2)
89#define L2CREG9_I_LOCKDOWN2 (L2C.REG9_I_LOCKDOWN2)
90#define L2CREG9_D_LOCKDOWN3 (L2C.REG9_D_LOCKDOWN3)
91#define L2CREG9_I_LOCKDOWN3 (L2C.REG9_I_LOCKDOWN3)
92#define L2CREG9_D_LOCKDOWN4 (L2C.REG9_D_LOCKDOWN4)
93#define L2CREG9_I_LOCKDOWN4 (L2C.REG9_I_LOCKDOWN4)
94#define L2CREG9_D_LOCKDOWN5 (L2C.REG9_D_LOCKDOWN5)
95#define L2CREG9_I_LOCKDOWN5 (L2C.REG9_I_LOCKDOWN5)
96#define L2CREG9_D_LOCKDOWN6 (L2C.REG9_D_LOCKDOWN6)
97#define L2CREG9_I_LOCKDOWN6 (L2C.REG9_I_LOCKDOWN6)
98#define L2CREG9_D_LOCKDOWN7 (L2C.REG9_D_LOCKDOWN7)
99#define L2CREG9_I_LOCKDOWN7 (L2C.REG9_I_LOCKDOWN7)
100#define L2CREG9_LOCK_LINE_EN (L2C.REG9_LOCK_LINE_EN)
101#define L2CREG9_UNLOCK_WAY (L2C.REG9_UNLOCK_WAY)
102#define L2CREG12_ADDR_FILTERING_START (L2C.REG12_ADDR_FILTERING_START)
103#define L2CREG12_ADDR_FILTERING_END (L2C.REG12_ADDR_FILTERING_END)
104#define L2CREG15_DEBUG_CTRL (L2C.REG15_DEBUG_CTRL)
105#define L2CREG15_PREFETCH_CTRL (L2C.REG15_PREFETCH_CTRL)
106#define L2CREG15_POWER_CTRL (L2C.REG15_POWER_CTRL)
107
108
109typedef struct st_l2c
110{
111 /* L2C */
112 volatile uint32_t REG0_CACHE_ID; /* REG0_CACHE_ID */
113 volatile uint32_t REG0_CACHE_TYPE; /* REG0_CACHE_TYPE */
114 volatile uint8_t dummy8[248]; /* */
115 volatile uint32_t REG1_CONTROL; /* REG1_CONTROL */
116 volatile uint32_t REG1_AUX_CONTROL; /* REG1_AUX_CONTROL */
117 volatile uint32_t REG1_TAG_RAM_CONTROL; /* REG1_TAG_RAM_CONTROL */
118 volatile uint32_t REG1_DATA_RAM_CONTROL; /* REG1_DATA_RAM_CONTROL */
119 volatile uint8_t dummy9[240]; /* */
120 volatile uint32_t REG2_EV_COUNTER_CTRL; /* REG2_EV_COUNTER_CTRL */
121 volatile uint32_t REG2_EV_COUNTER1_CFG; /* REG2_EV_COUNTER1_CFG */
122 volatile uint32_t REG2_EV_COUNTER0_CFG; /* REG2_EV_COUNTER0_CFG */
123 volatile uint32_t REG2_EV_COUNTER1; /* REG2_EV_COUNTER1 */
124 volatile uint32_t REG2_EV_COUNTER0; /* REG2_EV_COUNTER0 */
125 volatile uint32_t REG2_INT_MASK; /* REG2_INT_MASK */
126 volatile uint32_t REG2_INT_MASK_STATUS; /* REG2_INT_MASK_STATUS */
127 volatile uint32_t REG2_INT_RAW_STATUS; /* REG2_INT_RAW_STATUS */
128 volatile uint32_t REG2_INT_CLEAR; /* REG2_INT_CLEAR */
129 volatile uint8_t dummy10[1292]; /* */
130 volatile uint32_t REG7_CACHE_SYNC; /* REG7_CACHE_SYNC */
131 volatile uint8_t dummy11[60]; /* */
132 volatile uint32_t REG7_INV_PA; /* REG7_INV_PA */
133 volatile uint8_t dummy12[8]; /* */
134 volatile uint32_t REG7_INV_WAY; /* REG7_INV_WAY */
135 volatile uint8_t dummy13[48]; /* */
136 volatile uint32_t REG7_CLEAN_PA; /* REG7_CLEAN_PA */
137 volatile uint8_t dummy14[4]; /* */
138 volatile uint32_t REG7_CLEAN_INDEX; /* REG7_CLEAN_INDEX */
139 volatile uint32_t REG7_CLEAN_WAY; /* REG7_CLEAN_WAY */
140 volatile uint8_t dummy15[48]; /* */
141 volatile uint32_t REG7_CLEAN_INV_PA; /* REG7_CLEAN_INV_PA */
142 volatile uint8_t dummy16[4]; /* */
143 volatile uint32_t REG7_CLEAN_INV_INDEX; /* REG7_CLEAN_INV_INDEX */
144 volatile uint32_t REG7_CLEAN_INV_WAY; /* REG7_CLEAN_INV_WAY */
145 volatile uint8_t dummy17[256]; /* */
146
147/* start of struct st_l2c_from_reg9_d_lockdown0 */
148 volatile uint32_t REG9_D_LOCKDOWN0; /* REG9_D_LOCKDOWN0 */
149 volatile uint32_t REG9_I_LOCKDOWN0; /* REG9_I_LOCKDOWN0 */
150
151/* end of struct st_l2c_from_reg9_d_lockdown0 */
152
153/* start of struct st_l2c_from_reg9_d_lockdown0 */
154 volatile uint32_t REG9_D_LOCKDOWN1; /* REG9_D_LOCKDOWN1 */
155 volatile uint32_t REG9_I_LOCKDOWN1; /* REG9_I_LOCKDOWN1 */
156
157/* end of struct st_l2c_from_reg9_d_lockdown0 */
158
159/* start of struct st_l2c_from_reg9_d_lockdown0 */
160 volatile uint32_t REG9_D_LOCKDOWN2; /* REG9_D_LOCKDOWN2 */
161 volatile uint32_t REG9_I_LOCKDOWN2; /* REG9_I_LOCKDOWN2 */
162
163/* end of struct st_l2c_from_reg9_d_lockdown0 */
164
165/* start of struct st_l2c_from_reg9_d_lockdown0 */
166 volatile uint32_t REG9_D_LOCKDOWN3; /* REG9_D_LOCKDOWN3 */
167 volatile uint32_t REG9_I_LOCKDOWN3; /* REG9_I_LOCKDOWN3 */
168
169/* end of struct st_l2c_from_reg9_d_lockdown0 */
170
171/* start of struct st_l2c_from_reg9_d_lockdown0 */
172 volatile uint32_t REG9_D_LOCKDOWN4; /* REG9_D_LOCKDOWN4 */
173 volatile uint32_t REG9_I_LOCKDOWN4; /* REG9_I_LOCKDOWN4 */
174
175/* end of struct st_l2c_from_reg9_d_lockdown0 */
176
177/* start of struct st_l2c_from_reg9_d_lockdown0 */
178 volatile uint32_t REG9_D_LOCKDOWN5; /* REG9_D_LOCKDOWN5 */
179 volatile uint32_t REG9_I_LOCKDOWN5; /* REG9_I_LOCKDOWN5 */
180
181/* end of struct st_l2c_from_reg9_d_lockdown0 */
182
183/* start of struct st_l2c_from_reg9_d_lockdown0 */
184 volatile uint32_t REG9_D_LOCKDOWN6; /* REG9_D_LOCKDOWN6 */
185 volatile uint32_t REG9_I_LOCKDOWN6; /* REG9_I_LOCKDOWN6 */
186
187/* end of struct st_l2c_from_reg9_d_lockdown0 */
188
189/* start of struct st_l2c_from_reg9_d_lockdown0 */
190 volatile uint32_t REG9_D_LOCKDOWN7; /* REG9_D_LOCKDOWN7 */
191 volatile uint32_t REG9_I_LOCKDOWN7; /* REG9_I_LOCKDOWN7 */
192
193/* end of struct st_l2c_from_reg9_d_lockdown0 */
194 volatile uint8_t dummy18[16]; /* */
195 volatile uint32_t REG9_LOCK_LINE_EN; /* REG9_LOCK_LINE_EN */
196 volatile uint32_t REG9_UNLOCK_WAY; /* REG9_UNLOCK_WAY */
197 volatile uint8_t dummy19[680]; /* */
198 volatile uint32_t REG12_ADDR_FILTERING_START; /* REG12_ADDR_FILTERING_START */
199 volatile uint32_t REG12_ADDR_FILTERING_END; /* REG12_ADDR_FILTERING_END */
200 volatile uint8_t dummy20[824]; /* */
201 volatile uint32_t REG15_DEBUG_CTRL; /* REG15_DEBUG_CTRL */
202 volatile uint8_t dummy21[28]; /* */
203 volatile uint32_t REG15_PREFETCH_CTRL; /* REG15_PREFETCH_CTRL */
204 volatile uint8_t dummy22[28]; /* */
205 volatile uint32_t REG15_POWER_CTRL; /* REG15_POWER_CTRL */
206} r_io_l2c_t;
207
208
209typedef struct st_l2c_from_reg9_d_lockdown0
210{
211
212 volatile uint32_t REG9_D_LOCKDOWN0; /* REG9_D_LOCKDOWN0 */
213 volatile uint32_t REG9_I_LOCKDOWN0; /* REG9_I_LOCKDOWN0 */
214} r_io_l2c_from_reg9_d_lockdown_t /* Short of r_io_l2c_from_reg9_d_lockdown0_t */;
215
216
217/* Channel array defines of L2C (2)*/
218#ifdef DECLARE_L2C_FROM_REG9_D_LOCKDOWN0_ARRAY_CHANNELS
219volatile struct st_l2c_from_reg9_d_lockdown0* L2C_FROM_REG9_D_LOCKDOWN0_ARRAY[ L2C_FROM_REG9_D_LOCKDOWN0_ARRAY_COUNT ] =
220 /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */
221 L2C_FROM_REG9_D_LOCKDOWN0_ARRAY_ADDRESS_LIST;
222 /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */
223#endif /* DECLARE_L2C_FROM_REG9_D_LOCKDOWN0_ARRAY_CHANNELS */
224/* End of channel array defines of L2C (2)*/
225
226
227/* <-SEC M1.10.1 */
228/* <-MISRA 18.4 */ /* <-SEC M1.6.2 */
229/* <-QAC 0857 */
230/* <-QAC 0639 */
231#endif
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