source: asp3_tinet_ecnl_arm/trunk/asp3_dcre/mbed/targets/TARGET_RENESAS/TARGET_RZA1XX/TARGET_RZ_A1H/device/inc/iodefines/jcu_iodefine.h@ 374

Last change on this file since 374 was 374, checked in by coas-nagasima, 5 years ago

mbed関連を更新
シリアルドライバをmbedのHALを使うよう変更
ファイルディスクリプタの処理を更新
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  • Property svn:mime-type set to text/x-chdr;charset=UTF-8
File size: 9.7 KB
RevLine 
[352]1/*******************************************************************************
2* DISCLAIMER
3* This software is supplied by Renesas Electronics Corporation and is only
4* intended for use with Renesas products. No other uses are authorized. This
5* software is owned by Renesas Electronics Corporation and is protected under
6* all applicable laws, including copyright laws.
7* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
8* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
9* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
10* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
11* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
12* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
13* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
14* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
15* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
16* Renesas reserves the right, without notice, to make changes to this software
17* and to discontinue the availability of this software. By using this software,
18* you agree to the additional terms and conditions found by accessing the
19* following link:
20* http://www.renesas.com/disclaimer*
[374]21* Copyright (C) 2013-2015 Renesas Electronics Corporation. All rights reserved.
[352]22*******************************************************************************/
23/*******************************************************************************
24* File Name : jcu_iodefine.h
25* $Rev: $
26* $Date:: $
[374]27* Description : Definition of I/O Register for RZ/A1H,M (V2.00h)
[352]28******************************************************************************/
29#ifndef JCU_IODEFINE_H
30#define JCU_IODEFINE_H
[374]31/* ->QAC 0639 : Over 127 members (C90) */
32/* ->QAC 0857 : Over 1024 #define (C90) */
33/* ->MISRA 18.4 : Pack unpack union */ /* ->SEC M1.6.2 */
[352]34/* ->SEC M1.10.1 : Not magic number */
35
[374]36#define JCU (*(struct st_jcu *)0xE8017000uL) /* JCU */
37
38
39/* Start of channel array defines of JCU */
40
41/* Channel array defines of JCU_JCQTBL0 */
42/*(Sample) value = JCU_JCQTBL0[ channel ]->JCQTBL0; */
43#define JCU_JCQTBL0_COUNT (4)
44#define JCU_JCQTBL0_ADDRESS_LIST \
45{ /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \
46 &JCU_FROM_JCQTBL0, &JCU_FROM_JCQTBL1, &JCU_FROM_JCQTBL2, &JCU_FROM_JCQTBL3 \
47} /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */
48#define JCU_FROM_JCQTBL0 (*(struct st_jcu_from_jcqtbl0 *)&JCU.JCQTBL0) /* JCU_FROM_JCQTBL0 */
49#define JCU_FROM_JCQTBL1 (*(struct st_jcu_from_jcqtbl0 *)&JCU.JCQTBL1) /* JCU_FROM_JCQTBL1 */
50#define JCU_FROM_JCQTBL2 (*(struct st_jcu_from_jcqtbl0 *)&JCU.JCQTBL2) /* JCU_FROM_JCQTBL2 */
51#define JCU_FROM_JCQTBL3 (*(struct st_jcu_from_jcqtbl0 *)&JCU.JCQTBL3) /* JCU_FROM_JCQTBL3 */
52
53/* End of channel array defines of JCU */
54
55
56#define JCUJCMOD (JCU.JCMOD)
57#define JCUJCCMD (JCU.JCCMD)
58#define JCUJCQTN (JCU.JCQTN)
59#define JCUJCHTN (JCU.JCHTN)
60#define JCUJCDRIU (JCU.JCDRIU)
61#define JCUJCDRID (JCU.JCDRID)
62#define JCUJCVSZU (JCU.JCVSZU)
63#define JCUJCVSZD (JCU.JCVSZD)
64#define JCUJCHSZU (JCU.JCHSZU)
65#define JCUJCHSZD (JCU.JCHSZD)
66#define JCUJCDTCU (JCU.JCDTCU)
67#define JCUJCDTCM (JCU.JCDTCM)
68#define JCUJCDTCD (JCU.JCDTCD)
69#define JCUJINTE0 (JCU.JINTE0)
70#define JCUJINTS0 (JCU.JINTS0)
71#define JCUJCDERR (JCU.JCDERR)
72#define JCUJCRST (JCU.JCRST)
73#define JCUJIFECNT (JCU.JIFECNT)
74#define JCUJIFESA (JCU.JIFESA)
75#define JCUJIFESOFST (JCU.JIFESOFST)
76#define JCUJIFEDA (JCU.JIFEDA)
77#define JCUJIFESLC (JCU.JIFESLC)
78#define JCUJIFEDDC (JCU.JIFEDDC)
79#define JCUJIFDCNT (JCU.JIFDCNT)
80#define JCUJIFDSA (JCU.JIFDSA)
81#define JCUJIFDDOFST (JCU.JIFDDOFST)
82#define JCUJIFDDA (JCU.JIFDDA)
83#define JCUJIFDSDC (JCU.JIFDSDC)
84#define JCUJIFDDLC (JCU.JIFDDLC)
85#define JCUJIFDADT (JCU.JIFDADT)
86#define JCUJINTE1 (JCU.JINTE1)
87#define JCUJINTS1 (JCU.JINTS1)
88#define JCUJIFESVSZ (JCU.JIFESVSZ)
89#define JCUJIFESHSZ (JCU.JIFESHSZ)
90#define JCUJCQTBL0 (JCU.JCQTBL0)
91#define JCUJCQTBL1 (JCU.JCQTBL1)
92#define JCUJCQTBL2 (JCU.JCQTBL2)
93#define JCUJCQTBL3 (JCU.JCQTBL3)
94#define JCUJCHTBD0 (JCU.JCHTBD0)
95#define JCUJCHTBA0 (JCU.JCHTBA0)
96#define JCUJCHTBD1 (JCU.JCHTBD1)
97#define JCUJCHTBA1 (JCU.JCHTBA1)
98
99
100typedef struct st_jcu
101{
102 /* JCU */
[352]103 volatile uint8_t JCMOD; /* JCMOD */
104 volatile uint8_t JCCMD; /* JCCMD */
105 volatile uint8_t dummy145[1]; /* */
106 volatile uint8_t JCQTN; /* JCQTN */
107 volatile uint8_t JCHTN; /* JCHTN */
108 volatile uint8_t JCDRIU; /* JCDRIU */
109 volatile uint8_t JCDRID; /* JCDRID */
110 volatile uint8_t JCVSZU; /* JCVSZU */
111 volatile uint8_t JCVSZD; /* JCVSZD */
112 volatile uint8_t JCHSZU; /* JCHSZU */
113 volatile uint8_t JCHSZD; /* JCHSZD */
114 volatile uint8_t JCDTCU; /* JCDTCU */
115 volatile uint8_t JCDTCM; /* JCDTCM */
116 volatile uint8_t JCDTCD; /* JCDTCD */
117 volatile uint8_t JINTE0; /* JINTE0 */
118 volatile uint8_t JINTS0; /* JINTS0 */
119 volatile uint8_t JCDERR; /* JCDERR */
120 volatile uint8_t JCRST; /* JCRST */
121 volatile uint8_t dummy146[46]; /* */
122 volatile uint32_t JIFECNT; /* JIFECNT */
123 volatile uint32_t JIFESA; /* JIFESA */
124 volatile uint32_t JIFESOFST; /* JIFESOFST */
125 volatile uint32_t JIFEDA; /* JIFEDA */
126 volatile uint32_t JIFESLC; /* JIFESLC */
127 volatile uint32_t JIFEDDC; /* JIFEDDC */
128 volatile uint32_t JIFDCNT; /* JIFDCNT */
129 volatile uint32_t JIFDSA; /* JIFDSA */
130 volatile uint32_t JIFDDOFST; /* JIFDDOFST */
131 volatile uint32_t JIFDDA; /* JIFDDA */
132 volatile uint32_t JIFDSDC; /* JIFDSDC */
133 volatile uint32_t JIFDDLC; /* JIFDDLC */
134 volatile uint32_t JIFDADT; /* JIFDADT */
135 volatile uint8_t dummy147[24]; /* */
136 volatile uint32_t JINTE1; /* JINTE1 */
137 volatile uint32_t JINTS1; /* JINTS1 */
138 volatile uint32_t JIFESVSZ; /* JIFESVSZ */
139 volatile uint32_t JIFESHSZ; /* JIFESHSZ */
140 volatile uint8_t dummy148[100]; /* */
[374]141
[352]142/* start of struct st_jcu_from_jcqtbl0 */
143 volatile uint8_t JCQTBL0; /* JCQTBL0 */
144 volatile uint8_t dummy149[63]; /* */
[374]145
[352]146/* end of struct st_jcu_from_jcqtbl0 */
[374]147
[352]148/* start of struct st_jcu_from_jcqtbl0 */
149 volatile uint8_t JCQTBL1; /* JCQTBL1 */
150 volatile uint8_t dummy150[63]; /* */
[374]151
[352]152/* end of struct st_jcu_from_jcqtbl0 */
[374]153
[352]154/* start of struct st_jcu_from_jcqtbl0 */
155 volatile uint8_t JCQTBL2; /* JCQTBL2 */
156 volatile uint8_t dummy151[63]; /* */
[374]157
[352]158/* end of struct st_jcu_from_jcqtbl0 */
[374]159
[352]160/* start of struct st_jcu_from_jcqtbl0 */
161 volatile uint8_t JCQTBL3; /* JCQTBL3 */
162 volatile uint8_t dummy152[63]; /* */
[374]163
[352]164/* end of struct st_jcu_from_jcqtbl0 */
165 volatile uint8_t JCHTBD0; /* JCHTBD0 */
166 volatile uint8_t dummy153[31]; /* */
167 volatile uint8_t JCHTBA0; /* JCHTBA0 */
168 volatile uint8_t dummy154[223]; /* */
169 volatile uint8_t JCHTBD1; /* JCHTBD1 */
170 volatile uint8_t dummy155[31]; /* */
171 volatile uint8_t JCHTBA1; /* JCHTBA1 */
[374]172} r_io_jcu_t;
[352]173
174
[374]175typedef struct st_jcu_from_jcqtbl0
[352]176{
[374]177
[352]178 volatile uint8_t JCQTBL0; /* JCQTBL0 */
179 volatile uint8_t dummy1[63]; /* */
[374]180} r_io_jcu_from_jcqtbl0_t;
[352]181
182
[374]183/* Channel array defines of JCU (2)*/
184#ifdef DECLARE_JCU_JCQTBL0_CHANNELS
185volatile struct st_jcu_from_jcqtbl0* JCU_JCQTBL0[ JCU_JCQTBL0_COUNT ] =
186 /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */
187 JCU_JCQTBL0_ADDRESS_LIST;
188 /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */
189#endif /* DECLARE_JCU_JCQTBL0_CHANNELS */
190/* End of channel array defines of JCU (2)*/
[352]191
192
193/* <-SEC M1.10.1 */
[374]194/* <-MISRA 18.4 */ /* <-SEC M1.6.2 */
195/* <-QAC 0857 */
196/* <-QAC 0639 */
[352]197#endif
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