source: asp3_tinet_ecnl_arm/trunk/asp3_dcre/mbed/targets/TARGET_RENESAS/TARGET_RZA1XX/TARGET_RZ_A1H/device/inc/iodefines/ieb_iodefine.h@ 374

Last change on this file since 374 was 374, checked in by coas-nagasima, 5 years ago

mbed関連を更新
シリアルドライバをmbedのHALを使うよう変更
ファイルディスクリプタの処理を更新
  • Property svn:eol-style set to native
  • Property svn:mime-type set to text/x-chdr;charset=UTF-8
File size: 7.3 KB
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1/*******************************************************************************
2* DISCLAIMER
3* This software is supplied by Renesas Electronics Corporation and is only
4* intended for use with Renesas products. No other uses are authorized. This
5* software is owned by Renesas Electronics Corporation and is protected under
6* all applicable laws, including copyright laws.
7* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
8* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
9* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
10* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
11* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
12* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
13* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
14* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
15* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
16* Renesas reserves the right, without notice, to make changes to this software
17* and to discontinue the availability of this software. By using this software,
18* you agree to the additional terms and conditions found by accessing the
19* following link:
20* http://www.renesas.com/disclaimer*
21* Copyright (C) 2013-2015 Renesas Electronics Corporation. All rights reserved.
22*******************************************************************************/
23/*******************************************************************************
24* File Name : ieb_iodefine.h
25* $Rev: $
26* $Date:: $
27* Description : Definition of I/O Register for RZ/A1H,M (V2.00h)
28******************************************************************************/
29#ifndef IEB_IODEFINE_H
30#define IEB_IODEFINE_H
31/* ->QAC 0639 : Over 127 members (C90) */
32/* ->QAC 0857 : Over 1024 #define (C90) */
33/* ->MISRA 18.4 : Pack unpack union */ /* ->SEC M1.6.2 */
34/* ->SEC M1.10.1 : Not magic number */
35
36#define IEB (*(struct st_ieb *)0xFCFEF000uL) /* IEB */
37
38
39#define IEBB0BCR (IEB.B0BCR)
40#define IEBB0PSR (IEB.B0PSR)
41#define IEBB0UAR (IEB.B0UAR)
42#define IEBB0SAR (IEB.B0SAR)
43#define IEBB0PAR (IEB.B0PAR)
44#define IEBB0RSA (IEB.B0RSA)
45#define IEBB0CDR (IEB.B0CDR)
46#define IEBB0TCD (IEB.B0TCD)
47#define IEBB0RCD (IEB.B0RCD)
48#define IEBB0DLR (IEB.B0DLR)
49#define IEBB0TDL (IEB.B0TDL)
50#define IEBB0RDL (IEB.B0RDL)
51#define IEBB0CKS (IEB.B0CKS)
52#define IEBB0TMS (IEB.B0TMS)
53#define IEBB0PCR (IEB.B0PCR)
54#define IEBB0BSR (IEB.B0BSR)
55#define IEBB0SSR (IEB.B0SSR)
56#define IEBB0USR (IEB.B0USR)
57#define IEBB0ISR (IEB.B0ISR)
58#define IEBB0ESR (IEB.B0ESR)
59#define IEBB0FSR (IEB.B0FSR)
60#define IEBB0SCR (IEB.B0SCR)
61#define IEBB0CCR (IEB.B0CCR)
62#define IEBB0STC0 (IEB.B0STC0)
63#define IEBB0STC1 (IEB.B0STC1)
64#define IEBB0DR (IEB.B0DR)
65
66
67typedef struct st_ieb
68{
69 /* IEB */
70 volatile uint8_t B0BCR; /* B0BCR */
71 volatile uint8_t dummy495[3]; /* */
72 volatile uint8_t B0PSR; /* B0PSR */
73 volatile uint8_t dummy496[3]; /* */
74 volatile uint16_t B0UAR; /* B0UAR */
75 volatile uint8_t dummy497[2]; /* */
76 volatile uint16_t B0SAR; /* B0SAR */
77 volatile uint8_t dummy498[2]; /* */
78 volatile uint16_t B0PAR; /* B0PAR */
79 volatile uint8_t dummy499[2]; /* */
80 volatile uint16_t B0RSA; /* B0RSA */
81 volatile uint8_t dummy500[2]; /* */
82 volatile uint8_t B0CDR; /* B0CDR */
83 volatile uint8_t dummy501[3]; /* */
84 volatile uint8_t B0TCD; /* B0TCD */
85 volatile uint8_t dummy502[3]; /* */
86 volatile uint8_t B0RCD; /* B0RCD */
87 volatile uint8_t dummy503[3]; /* */
88 volatile uint8_t B0DLR; /* B0DLR */
89 volatile uint8_t dummy504[3]; /* */
90 volatile uint8_t B0TDL; /* B0TDL */
91 volatile uint8_t dummy505[3]; /* */
92 volatile uint8_t B0RDL; /* B0RDL */
93 volatile uint8_t dummy506[3]; /* */
94 volatile uint8_t B0CKS; /* B0CKS */
95 volatile uint8_t dummy507[3]; /* */
96 volatile uint8_t B0TMS; /* B0TMS */
97 volatile uint8_t dummy508[3]; /* */
98 volatile uint8_t B0PCR; /* B0PCR */
99 volatile uint8_t dummy509[3]; /* */
100 volatile uint16_t B0BSR; /* B0BSR */
101 volatile uint8_t dummy510[2]; /* */
102 volatile uint8_t B0SSR; /* B0SSR */
103 volatile uint8_t dummy511[3]; /* */
104 volatile uint8_t B0USR; /* B0USR */
105 volatile uint8_t dummy512[3]; /* */
106 volatile uint8_t B0ISR; /* B0ISR */
107 volatile uint8_t dummy513[3]; /* */
108 volatile uint8_t B0ESR; /* B0ESR */
109 volatile uint8_t dummy514[3]; /* */
110 volatile uint8_t B0FSR; /* B0FSR */
111 volatile uint8_t dummy515[3]; /* */
112 volatile uint8_t B0SCR; /* B0SCR */
113 volatile uint8_t dummy516[3]; /* */
114 volatile uint8_t B0CCR; /* B0CCR */
115 volatile uint8_t dummy517[3]; /* */
116 volatile uint8_t B0STC0; /* B0STC0 */
117 volatile uint8_t dummy518[3]; /* */
118 volatile uint8_t B0STC1; /* B0STC1 */
119 volatile uint8_t dummy519[3]; /* */
120 volatile uint8_t B0DR; /* B0DR */
121} r_io_ieb_t;
122
123
124/* <-SEC M1.10.1 */
125/* <-MISRA 18.4 */ /* <-SEC M1.6.2 */
126/* <-QAC 0857 */
127/* <-QAC 0639 */
128#endif
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