source: asp3_tinet_ecnl_arm/trunk/asp3_dcre/mbed/targets/TARGET_RENESAS/TARGET_RZA1XX/TARGET_RZ_A1H/device/inc/iodefines/gpio_iodefine.h@ 374

Last change on this file since 374 was 374, checked in by coas-nagasima, 5 years ago

mbed関連を更新
シリアルドライバをmbedのHALを使うよう変更
ファイルディスクリプタの処理を更新
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File size: 65.0 KB
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1/*******************************************************************************
2* DISCLAIMER
3* This software is supplied by Renesas Electronics Corporation and is only
4* intended for use with Renesas products. No other uses are authorized. This
5* software is owned by Renesas Electronics Corporation and is protected under
6* all applicable laws, including copyright laws.
7* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
8* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
9* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
10* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
11* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
12* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
13* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
14* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
15* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
16* Renesas reserves the right, without notice, to make changes to this software
17* and to discontinue the availability of this software. By using this software,
18* you agree to the additional terms and conditions found by accessing the
19* following link:
20* http://www.renesas.com/disclaimer*
21* Copyright (C) 2013-2015 Renesas Electronics Corporation. All rights reserved.
22*******************************************************************************/
23/*******************************************************************************
24* File Name : gpio_iodefine.h
25* $Rev: $
26* $Date:: $
27* Description : Definition of I/O Register for RZ/A1H,M (V2.00h)
28******************************************************************************/
29#ifndef GPIO_IODEFINE_H
30#define GPIO_IODEFINE_H
31/* ->QAC 0639 : Over 127 members (C90) */
32/* ->QAC 0857 : Over 1024 #define (C90) */
33/* ->MISRA 18.4 : Pack unpack union */ /* ->SEC M1.6.2 */
34/* ->SEC M1.10.1 : Not magic number */
35
36#define GPIO (*(struct st_gpio *)0xFCFE3004uL) /* GPIO */
37
38
39/* Start of channel array defines of GPIO */
40
41/* Channel array defines of GPIO_FROM_PIPC1_ARRAY */
42/*(Sample) value = GPIO_FROM_PIPC1_ARRAY[ channel ]->PIPC1; */
43#define GPIO_FROM_PIPC1_ARRAY_COUNT (11)
44#define GPIO_FROM_PIPC1_ARRAY_ADDRESS_LIST \
45{ /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \
46 &GPIO_FROM_PIPC1, &GPIO_FROM_PIPC2, &GPIO_FROM_PIPC3, &GPIO_FROM_PIPC4, &GPIO_FROM_PIPC5, &GPIO_FROM_PIPC6, &GPIO_FROM_PIPC7, &GPIO_FROM_PIPC8, \
47 &GPIO_FROM_PIPC9, &GPIO_FROM_PIPC10, &GPIO_FROM_PIPC11 \
48} /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */
49#define GPIO_FROM_PIPC1 (*(struct st_gpio_from_pipc1 *)&GPIO.PIPC1) /* GPIO_FROM_PIPC1 */
50#define GPIO_FROM_PIPC2 (*(struct st_gpio_from_pipc1 *)&GPIO.PIPC2) /* GPIO_FROM_PIPC2 */
51#define GPIO_FROM_PIPC3 (*(struct st_gpio_from_pipc1 *)&GPIO.PIPC3) /* GPIO_FROM_PIPC3 */
52#define GPIO_FROM_PIPC4 (*(struct st_gpio_from_pipc1 *)&GPIO.PIPC4) /* GPIO_FROM_PIPC4 */
53#define GPIO_FROM_PIPC5 (*(struct st_gpio_from_pipc1 *)&GPIO.PIPC5) /* GPIO_FROM_PIPC5 */
54#define GPIO_FROM_PIPC6 (*(struct st_gpio_from_pipc1 *)&GPIO.PIPC6) /* GPIO_FROM_PIPC6 */
55#define GPIO_FROM_PIPC7 (*(struct st_gpio_from_pipc1 *)&GPIO.PIPC7) /* GPIO_FROM_PIPC7 */
56#define GPIO_FROM_PIPC8 (*(struct st_gpio_from_pipc1 *)&GPIO.PIPC8) /* GPIO_FROM_PIPC8 */
57#define GPIO_FROM_PIPC9 (*(struct st_gpio_from_pipc1 *)&GPIO.PIPC9) /* GPIO_FROM_PIPC9 */
58#define GPIO_FROM_PIPC10 (*(struct st_gpio_from_pipc1 *)&GPIO.PIPC10) /* GPIO_FROM_PIPC10 */
59#define GPIO_FROM_PIPC11 (*(struct st_gpio_from_pipc1 *)&GPIO.PIPC11) /* GPIO_FROM_PIPC11 */
60
61
62/* Channel array defines of GPIO_FROM_PBDC1_ARRAY */
63/*(Sample) value = GPIO_FROM_PBDC1_ARRAY[ channel ]->PBDC1; */
64#define GPIO_FROM_PBDC1_ARRAY_COUNT (11)
65#define GPIO_FROM_PBDC1_ARRAY_ADDRESS_LIST \
66{ /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \
67 &GPIO_FROM_PBDC1, &GPIO_FROM_PBDC2, &GPIO_FROM_PBDC3, &GPIO_FROM_PBDC4, &GPIO_FROM_PBDC5, &GPIO_FROM_PBDC6, &GPIO_FROM_PBDC7, &GPIO_FROM_PBDC8, \
68 &GPIO_FROM_PBDC9, &GPIO_FROM_PBDC10, &GPIO_FROM_PBDC11 \
69} /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */
70#define GPIO_FROM_PBDC1 (*(struct st_gpio_from_pbdc1 *)&GPIO.PBDC1) /* GPIO_FROM_PBDC1 */
71#define GPIO_FROM_PBDC2 (*(struct st_gpio_from_pbdc1 *)&GPIO.PBDC2) /* GPIO_FROM_PBDC2 */
72#define GPIO_FROM_PBDC3 (*(struct st_gpio_from_pbdc1 *)&GPIO.PBDC3) /* GPIO_FROM_PBDC3 */
73#define GPIO_FROM_PBDC4 (*(struct st_gpio_from_pbdc1 *)&GPIO.PBDC4) /* GPIO_FROM_PBDC4 */
74#define GPIO_FROM_PBDC5 (*(struct st_gpio_from_pbdc1 *)&GPIO.PBDC5) /* GPIO_FROM_PBDC5 */
75#define GPIO_FROM_PBDC6 (*(struct st_gpio_from_pbdc1 *)&GPIO.PBDC6) /* GPIO_FROM_PBDC6 */
76#define GPIO_FROM_PBDC7 (*(struct st_gpio_from_pbdc1 *)&GPIO.PBDC7) /* GPIO_FROM_PBDC7 */
77#define GPIO_FROM_PBDC8 (*(struct st_gpio_from_pbdc1 *)&GPIO.PBDC8) /* GPIO_FROM_PBDC8 */
78#define GPIO_FROM_PBDC9 (*(struct st_gpio_from_pbdc1 *)&GPIO.PBDC9) /* GPIO_FROM_PBDC9 */
79#define GPIO_FROM_PBDC10 (*(struct st_gpio_from_pbdc1 *)&GPIO.PBDC10) /* GPIO_FROM_PBDC10 */
80#define GPIO_FROM_PBDC11 (*(struct st_gpio_from_pbdc1 *)&GPIO.PBDC11) /* GPIO_FROM_PBDC11 */
81
82
83/* Channel array defines of GPIO_FROM_PIBC1_ARRAY */
84/*(Sample) value = GPIO_FROM_PIBC1_ARRAY[ channel ]->PIBC1; */
85#define GPIO_FROM_PIBC1_ARRAY_COUNT (12)
86#define GPIO_FROM_PIBC1_ARRAY_ADDRESS_LIST \
87{ /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \
88 &GPIO_FROM_PIBC0, &GPIO_FROM_PIBC1, &GPIO_FROM_PIBC2, &GPIO_FROM_PIBC3, &GPIO_FROM_PIBC4, &GPIO_FROM_PIBC5, &GPIO_FROM_PIBC6, &GPIO_FROM_PIBC7, \
89 &GPIO_FROM_PIBC8, &GPIO_FROM_PIBC9, &GPIO_FROM_PIBC10, &GPIO_FROM_PIBC11 \
90} /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */
91#define GPIO_FROM_PIBC0 (*(struct st_gpio_from_pibc1 *)&GPIO.PIBC0) /* GPIO_FROM_PIBC0 */
92#define GPIO_FROM_PIBC1 (*(struct st_gpio_from_pibc1 *)&GPIO.PIBC1) /* GPIO_FROM_PIBC1 */
93#define GPIO_FROM_PIBC2 (*(struct st_gpio_from_pibc1 *)&GPIO.PIBC2) /* GPIO_FROM_PIBC2 */
94#define GPIO_FROM_PIBC3 (*(struct st_gpio_from_pibc1 *)&GPIO.PIBC3) /* GPIO_FROM_PIBC3 */
95#define GPIO_FROM_PIBC4 (*(struct st_gpio_from_pibc1 *)&GPIO.PIBC4) /* GPIO_FROM_PIBC4 */
96#define GPIO_FROM_PIBC5 (*(struct st_gpio_from_pibc1 *)&GPIO.PIBC5) /* GPIO_FROM_PIBC5 */
97#define GPIO_FROM_PIBC6 (*(struct st_gpio_from_pibc1 *)&GPIO.PIBC6) /* GPIO_FROM_PIBC6 */
98#define GPIO_FROM_PIBC7 (*(struct st_gpio_from_pibc1 *)&GPIO.PIBC7) /* GPIO_FROM_PIBC7 */
99#define GPIO_FROM_PIBC8 (*(struct st_gpio_from_pibc1 *)&GPIO.PIBC8) /* GPIO_FROM_PIBC8 */
100#define GPIO_FROM_PIBC9 (*(struct st_gpio_from_pibc1 *)&GPIO.PIBC9) /* GPIO_FROM_PIBC9 */
101#define GPIO_FROM_PIBC10 (*(struct st_gpio_from_pibc1 *)&GPIO.PIBC10) /* GPIO_FROM_PIBC10 */
102#define GPIO_FROM_PIBC11 (*(struct st_gpio_from_pibc1 *)&GPIO.PIBC11) /* GPIO_FROM_PIBC11 */
103
104
105/* Channel array defines of GPIO_FROM_PFCAE1_ARRAY */
106/*(Sample) value = GPIO_FROM_PFCAE1_ARRAY[ channel ]->PFCAE1; */
107#define GPIO_FROM_PFCAE1_ARRAY_COUNT (11)
108#define GPIO_FROM_PFCAE1_ARRAY_ADDRESS_LIST \
109{ /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \
110 &GPIO_FROM_PFCAE1, &GPIO_FROM_PFCAE2, &GPIO_FROM_PFCAE3, &GPIO_FROM_PFCAE4, &GPIO_FROM_PFCAE5, &GPIO_FROM_PFCAE6, &GPIO_FROM_PFCAE7, &GPIO_FROM_PFCAE8, \
111 &GPIO_FROM_PFCAE9, &GPIO_FROM_PFCAE10, &GPIO_FROM_PFCAE11 \
112} /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */
113#define GPIO_FROM_PFCAE1 (*(struct st_gpio_from_pfcae1 *)&GPIO.PFCAE1) /* GPIO_FROM_PFCAE1 */
114#define GPIO_FROM_PFCAE2 (*(struct st_gpio_from_pfcae1 *)&GPIO.PFCAE2) /* GPIO_FROM_PFCAE2 */
115#define GPIO_FROM_PFCAE3 (*(struct st_gpio_from_pfcae1 *)&GPIO.PFCAE3) /* GPIO_FROM_PFCAE3 */
116#define GPIO_FROM_PFCAE4 (*(struct st_gpio_from_pfcae1 *)&GPIO.PFCAE4) /* GPIO_FROM_PFCAE4 */
117#define GPIO_FROM_PFCAE5 (*(struct st_gpio_from_pfcae1 *)&GPIO.PFCAE5) /* GPIO_FROM_PFCAE5 */
118#define GPIO_FROM_PFCAE6 (*(struct st_gpio_from_pfcae1 *)&GPIO.PFCAE6) /* GPIO_FROM_PFCAE6 */
119#define GPIO_FROM_PFCAE7 (*(struct st_gpio_from_pfcae1 *)&GPIO.PFCAE7) /* GPIO_FROM_PFCAE7 */
120#define GPIO_FROM_PFCAE8 (*(struct st_gpio_from_pfcae1 *)&GPIO.PFCAE8) /* GPIO_FROM_PFCAE8 */
121#define GPIO_FROM_PFCAE9 (*(struct st_gpio_from_pfcae1 *)&GPIO.PFCAE9) /* GPIO_FROM_PFCAE9 */
122#define GPIO_FROM_PFCAE10 (*(struct st_gpio_from_pfcae1 *)&GPIO.PFCAE10) /* GPIO_FROM_PFCAE10 */
123#define GPIO_FROM_PFCAE11 (*(struct st_gpio_from_pfcae1 *)&GPIO.PFCAE11) /* GPIO_FROM_PFCAE11 */
124
125
126/* Channel array defines of GPIO_FROM_PNOT1_ARRAY */
127/*(Sample) value = GPIO_FROM_PNOT1_ARRAY[ channel ]->PNOT1; */
128#define GPIO_FROM_PNOT1_ARRAY_COUNT (11)
129#define GPIO_FROM_PNOT1_ARRAY_ADDRESS_LIST \
130{ /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \
131 &GPIO_FROM_PNOT1, &GPIO_FROM_PNOT2, &GPIO_FROM_PNOT3, &GPIO_FROM_PNOT4, &GPIO_FROM_PNOT5, &GPIO_FROM_PNOT6, &GPIO_FROM_PNOT7, &GPIO_FROM_PNOT8, \
132 &GPIO_FROM_PNOT9, &GPIO_FROM_PNOT10, &GPIO_FROM_PNOT11 \
133} /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */
134#define GPIO_FROM_PNOT1 (*(struct st_gpio_from_pnot1 *)&GPIO.PNOT1) /* GPIO_FROM_PNOT1 */
135#define GPIO_FROM_PNOT2 (*(struct st_gpio_from_pnot1 *)&GPIO.PNOT2) /* GPIO_FROM_PNOT2 */
136#define GPIO_FROM_PNOT3 (*(struct st_gpio_from_pnot1 *)&GPIO.PNOT3) /* GPIO_FROM_PNOT3 */
137#define GPIO_FROM_PNOT4 (*(struct st_gpio_from_pnot1 *)&GPIO.PNOT4) /* GPIO_FROM_PNOT4 */
138#define GPIO_FROM_PNOT5 (*(struct st_gpio_from_pnot1 *)&GPIO.PNOT5) /* GPIO_FROM_PNOT5 */
139#define GPIO_FROM_PNOT6 (*(struct st_gpio_from_pnot1 *)&GPIO.PNOT6) /* GPIO_FROM_PNOT6 */
140#define GPIO_FROM_PNOT7 (*(struct st_gpio_from_pnot1 *)&GPIO.PNOT7) /* GPIO_FROM_PNOT7 */
141#define GPIO_FROM_PNOT8 (*(struct st_gpio_from_pnot1 *)&GPIO.PNOT8) /* GPIO_FROM_PNOT8 */
142#define GPIO_FROM_PNOT9 (*(struct st_gpio_from_pnot1 *)&GPIO.PNOT9) /* GPIO_FROM_PNOT9 */
143#define GPIO_FROM_PNOT10 (*(struct st_gpio_from_pnot1 *)&GPIO.PNOT10) /* GPIO_FROM_PNOT10 */
144#define GPIO_FROM_PNOT11 (*(struct st_gpio_from_pnot1 *)&GPIO.PNOT11) /* GPIO_FROM_PNOT11 */
145
146
147/* Channel array defines of GPIO_FROM_PFCE1_ARRAY */
148/*(Sample) value = GPIO_FROM_PFCE1_ARRAY[ channel ]->PFCE1; */
149#define GPIO_FROM_PFCE1_ARRAY_COUNT (11)
150#define GPIO_FROM_PFCE1_ARRAY_ADDRESS_LIST \
151{ /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \
152 &GPIO_FROM_PFCE1, &GPIO_FROM_PFCE2, &GPIO_FROM_PFCE3, &GPIO_FROM_PFCE4, &GPIO_FROM_PFCE5, &GPIO_FROM_PFCE6, &GPIO_FROM_PFCE7, &GPIO_FROM_PFCE8, \
153 &GPIO_FROM_PFCE9, &GPIO_FROM_PFCE10, &GPIO_FROM_PFCE11 \
154} /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */
155#define GPIO_FROM_PFCE1 (*(struct st_gpio_from_pfce1 *)&GPIO.PFCE1) /* GPIO_FROM_PFCE1 */
156#define GPIO_FROM_PFCE2 (*(struct st_gpio_from_pfce1 *)&GPIO.PFCE2) /* GPIO_FROM_PFCE2 */
157#define GPIO_FROM_PFCE3 (*(struct st_gpio_from_pfce1 *)&GPIO.PFCE3) /* GPIO_FROM_PFCE3 */
158#define GPIO_FROM_PFCE4 (*(struct st_gpio_from_pfce1 *)&GPIO.PFCE4) /* GPIO_FROM_PFCE4 */
159#define GPIO_FROM_PFCE5 (*(struct st_gpio_from_pfce1 *)&GPIO.PFCE5) /* GPIO_FROM_PFCE5 */
160#define GPIO_FROM_PFCE6 (*(struct st_gpio_from_pfce1 *)&GPIO.PFCE6) /* GPIO_FROM_PFCE6 */
161#define GPIO_FROM_PFCE7 (*(struct st_gpio_from_pfce1 *)&GPIO.PFCE7) /* GPIO_FROM_PFCE7 */
162#define GPIO_FROM_PFCE8 (*(struct st_gpio_from_pfce1 *)&GPIO.PFCE8) /* GPIO_FROM_PFCE8 */
163#define GPIO_FROM_PFCE9 (*(struct st_gpio_from_pfce1 *)&GPIO.PFCE9) /* GPIO_FROM_PFCE9 */
164#define GPIO_FROM_PFCE10 (*(struct st_gpio_from_pfce1 *)&GPIO.PFCE10) /* GPIO_FROM_PFCE10 */
165#define GPIO_FROM_PFCE11 (*(struct st_gpio_from_pfce1 *)&GPIO.PFCE11) /* GPIO_FROM_PFCE11 */
166
167
168/* Channel array defines of GPIO_FROM_PFC1_ARRAY */
169/*(Sample) value = GPIO_FROM_PFC1_ARRAY[ channel ]->PFC1; */
170#define GPIO_FROM_PFC1_ARRAY_COUNT (11)
171#define GPIO_FROM_PFC1_ARRAY_ADDRESS_LIST \
172{ /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \
173 &GPIO_FROM_PFC1, &GPIO_FROM_PFC2, &GPIO_FROM_PFC3, &GPIO_FROM_PFC4, &GPIO_FROM_PFC5, &GPIO_FROM_PFC6, &GPIO_FROM_PFC7, &GPIO_FROM_PFC8, \
174 &GPIO_FROM_PFC9, &GPIO_FROM_PFC10, &GPIO_FROM_PFC11 \
175} /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */
176#define GPIO_FROM_PFC1 (*(struct st_gpio_from_pfc1 *)&GPIO.PFC1) /* GPIO_FROM_PFC1 */
177#define GPIO_FROM_PFC2 (*(struct st_gpio_from_pfc1 *)&GPIO.PFC2) /* GPIO_FROM_PFC2 */
178#define GPIO_FROM_PFC3 (*(struct st_gpio_from_pfc1 *)&GPIO.PFC3) /* GPIO_FROM_PFC3 */
179#define GPIO_FROM_PFC4 (*(struct st_gpio_from_pfc1 *)&GPIO.PFC4) /* GPIO_FROM_PFC4 */
180#define GPIO_FROM_PFC5 (*(struct st_gpio_from_pfc1 *)&GPIO.PFC5) /* GPIO_FROM_PFC5 */
181#define GPIO_FROM_PFC6 (*(struct st_gpio_from_pfc1 *)&GPIO.PFC6) /* GPIO_FROM_PFC6 */
182#define GPIO_FROM_PFC7 (*(struct st_gpio_from_pfc1 *)&GPIO.PFC7) /* GPIO_FROM_PFC7 */
183#define GPIO_FROM_PFC8 (*(struct st_gpio_from_pfc1 *)&GPIO.PFC8) /* GPIO_FROM_PFC8 */
184#define GPIO_FROM_PFC9 (*(struct st_gpio_from_pfc1 *)&GPIO.PFC9) /* GPIO_FROM_PFC9 */
185#define GPIO_FROM_PFC10 (*(struct st_gpio_from_pfc1 *)&GPIO.PFC10) /* GPIO_FROM_PFC10 */
186#define GPIO_FROM_PFC11 (*(struct st_gpio_from_pfc1 *)&GPIO.PFC11) /* GPIO_FROM_PFC11 */
187
188
189/* Channel array defines of GPIO_FROM_PMC0_ARRAY */
190/*(Sample) value = GPIO_FROM_PMC0_ARRAY[ channel ]->PMC0; */
191#define GPIO_FROM_PMC0_ARRAY_COUNT (12)
192#define GPIO_FROM_PMC0_ARRAY_ADDRESS_LIST \
193{ /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \
194 &GPIO_FROM_PMC0, &GPIO_FROM_PMC1, &GPIO_FROM_PMC2, &GPIO_FROM_PMC3, &GPIO_FROM_PMC4, &GPIO_FROM_PMC5, &GPIO_FROM_PMC6, &GPIO_FROM_PMC7, \
195 &GPIO_FROM_PMC8, &GPIO_FROM_PMC9, &GPIO_FROM_PMC10, &GPIO_FROM_PMC11 \
196} /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */
197#define GPIO_FROM_PMC0 (*(struct st_gpio_from_pmc0 *)&GPIO.PMC0) /* GPIO_FROM_PMC0 */
198#define GPIO_FROM_PMC1 (*(struct st_gpio_from_pmc0 *)&GPIO.PMC1) /* GPIO_FROM_PMC1 */
199#define GPIO_FROM_PMC2 (*(struct st_gpio_from_pmc0 *)&GPIO.PMC2) /* GPIO_FROM_PMC2 */
200#define GPIO_FROM_PMC3 (*(struct st_gpio_from_pmc0 *)&GPIO.PMC3) /* GPIO_FROM_PMC3 */
201#define GPIO_FROM_PMC4 (*(struct st_gpio_from_pmc0 *)&GPIO.PMC4) /* GPIO_FROM_PMC4 */
202#define GPIO_FROM_PMC5 (*(struct st_gpio_from_pmc0 *)&GPIO.PMC5) /* GPIO_FROM_PMC5 */
203#define GPIO_FROM_PMC6 (*(struct st_gpio_from_pmc0 *)&GPIO.PMC6) /* GPIO_FROM_PMC6 */
204#define GPIO_FROM_PMC7 (*(struct st_gpio_from_pmc0 *)&GPIO.PMC7) /* GPIO_FROM_PMC7 */
205#define GPIO_FROM_PMC8 (*(struct st_gpio_from_pmc0 *)&GPIO.PMC8) /* GPIO_FROM_PMC8 */
206#define GPIO_FROM_PMC9 (*(struct st_gpio_from_pmc0 *)&GPIO.PMC9) /* GPIO_FROM_PMC9 */
207#define GPIO_FROM_PMC10 (*(struct st_gpio_from_pmc0 *)&GPIO.PMC10) /* GPIO_FROM_PMC10 */
208#define GPIO_FROM_PMC11 (*(struct st_gpio_from_pmc0 *)&GPIO.PMC11) /* GPIO_FROM_PMC11 */
209
210
211/* Channel array defines of GPIO_FROM_PM1_ARRAY */
212/*(Sample) value = GPIO_FROM_PM1_ARRAY[ channel ]->PM1; */
213#define GPIO_FROM_PM1_ARRAY_COUNT (11)
214#define GPIO_FROM_PM1_ARRAY_ADDRESS_LIST \
215{ /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \
216 &GPIO_FROM_PM1, &GPIO_FROM_PM2, &GPIO_FROM_PM3, &GPIO_FROM_PM4, &GPIO_FROM_PM5, &GPIO_FROM_PM6, &GPIO_FROM_PM7, &GPIO_FROM_PM8, \
217 &GPIO_FROM_PM9, &GPIO_FROM_PM10, &GPIO_FROM_PM11 \
218} /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */
219#define GPIO_FROM_PM1 (*(struct st_gpio_from_pm1 *)&GPIO.PM1) /* GPIO_FROM_PM1 */
220#define GPIO_FROM_PM2 (*(struct st_gpio_from_pm1 *)&GPIO.PM2) /* GPIO_FROM_PM2 */
221#define GPIO_FROM_PM3 (*(struct st_gpio_from_pm1 *)&GPIO.PM3) /* GPIO_FROM_PM3 */
222#define GPIO_FROM_PM4 (*(struct st_gpio_from_pm1 *)&GPIO.PM4) /* GPIO_FROM_PM4 */
223#define GPIO_FROM_PM5 (*(struct st_gpio_from_pm1 *)&GPIO.PM5) /* GPIO_FROM_PM5 */
224#define GPIO_FROM_PM6 (*(struct st_gpio_from_pm1 *)&GPIO.PM6) /* GPIO_FROM_PM6 */
225#define GPIO_FROM_PM7 (*(struct st_gpio_from_pm1 *)&GPIO.PM7) /* GPIO_FROM_PM7 */
226#define GPIO_FROM_PM8 (*(struct st_gpio_from_pm1 *)&GPIO.PM8) /* GPIO_FROM_PM8 */
227#define GPIO_FROM_PM9 (*(struct st_gpio_from_pm1 *)&GPIO.PM9) /* GPIO_FROM_PM9 */
228#define GPIO_FROM_PM10 (*(struct st_gpio_from_pm1 *)&GPIO.PM10) /* GPIO_FROM_PM10 */
229#define GPIO_FROM_PM11 (*(struct st_gpio_from_pm1 *)&GPIO.PM11) /* GPIO_FROM_PM11 */
230
231
232/* Channel array defines of GPIO_FROM_PPR0_ARRAY */
233/*(Sample) value = GPIO_FROM_PPR0_ARRAY[ channel ]->PPR0; */
234#define GPIO_FROM_PPR0_ARRAY_COUNT (12)
235#define GPIO_FROM_PPR0_ARRAY_ADDRESS_LIST \
236{ /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \
237 &GPIO_FROM_PPR0, &GPIO_FROM_PPR1, &GPIO_FROM_PPR2, &GPIO_FROM_PPR3, &GPIO_FROM_PPR4, &GPIO_FROM_PPR5, &GPIO_FROM_PPR6, &GPIO_FROM_PPR7, \
238 &GPIO_FROM_PPR8, &GPIO_FROM_PPR9, &GPIO_FROM_PPR10, &GPIO_FROM_PPR11 \
239} /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */
240#define GPIO_FROM_PPR0 (*(struct st_gpio_from_ppr0 *)&GPIO.PPR0) /* GPIO_FROM_PPR0 */
241#define GPIO_FROM_PPR1 (*(struct st_gpio_from_ppr0 *)&GPIO.PPR1) /* GPIO_FROM_PPR1 */
242#define GPIO_FROM_PPR2 (*(struct st_gpio_from_ppr0 *)&GPIO.PPR2) /* GPIO_FROM_PPR2 */
243#define GPIO_FROM_PPR3 (*(struct st_gpio_from_ppr0 *)&GPIO.PPR3) /* GPIO_FROM_PPR3 */
244#define GPIO_FROM_PPR4 (*(struct st_gpio_from_ppr0 *)&GPIO.PPR4) /* GPIO_FROM_PPR4 */
245#define GPIO_FROM_PPR5 (*(struct st_gpio_from_ppr0 *)&GPIO.PPR5) /* GPIO_FROM_PPR5 */
246#define GPIO_FROM_PPR6 (*(struct st_gpio_from_ppr0 *)&GPIO.PPR6) /* GPIO_FROM_PPR6 */
247#define GPIO_FROM_PPR7 (*(struct st_gpio_from_ppr0 *)&GPIO.PPR7) /* GPIO_FROM_PPR7 */
248#define GPIO_FROM_PPR8 (*(struct st_gpio_from_ppr0 *)&GPIO.PPR8) /* GPIO_FROM_PPR8 */
249#define GPIO_FROM_PPR9 (*(struct st_gpio_from_ppr0 *)&GPIO.PPR9) /* GPIO_FROM_PPR9 */
250#define GPIO_FROM_PPR10 (*(struct st_gpio_from_ppr0 *)&GPIO.PPR10) /* GPIO_FROM_PPR10 */
251#define GPIO_FROM_PPR11 (*(struct st_gpio_from_ppr0 *)&GPIO.PPR11) /* GPIO_FROM_PPR11 */
252
253
254/* Channel array defines of GPIO_FROM_P1_ARRAY */
255/*(Sample) value = GPIO_FROM_P1_ARRAY[ channel ]->P1; */
256#define GPIO_FROM_P1_ARRAY_COUNT (11)
257#define GPIO_FROM_P1_ARRAY_ADDRESS_LIST \
258{ /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \
259 &GPIO_FROM_P1, &GPIO_FROM_P2, &GPIO_FROM_P3, &GPIO_FROM_P4, &GPIO_FROM_P5, &GPIO_FROM_P6, &GPIO_FROM_P7, &GPIO_FROM_P8, \
260 &GPIO_FROM_P9, &GPIO_FROM_P10, &GPIO_FROM_P11 \
261} /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */
262#define GPIO_FROM_P1 (*(struct st_gpio_from_p1 *)&GPIO.P1) /* GPIO_FROM_P1 */
263#define GPIO_FROM_P2 (*(struct st_gpio_from_p1 *)&GPIO.P2) /* GPIO_FROM_P2 */
264#define GPIO_FROM_P3 (*(struct st_gpio_from_p1 *)&GPIO.P3) /* GPIO_FROM_P3 */
265#define GPIO_FROM_P4 (*(struct st_gpio_from_p1 *)&GPIO.P4) /* GPIO_FROM_P4 */
266#define GPIO_FROM_P5 (*(struct st_gpio_from_p1 *)&GPIO.P5) /* GPIO_FROM_P5 */
267#define GPIO_FROM_P6 (*(struct st_gpio_from_p1 *)&GPIO.P6) /* GPIO_FROM_P6 */
268#define GPIO_FROM_P7 (*(struct st_gpio_from_p1 *)&GPIO.P7) /* GPIO_FROM_P7 */
269#define GPIO_FROM_P8 (*(struct st_gpio_from_p1 *)&GPIO.P8) /* GPIO_FROM_P8 */
270#define GPIO_FROM_P9 (*(struct st_gpio_from_p1 *)&GPIO.P9) /* GPIO_FROM_P9 */
271#define GPIO_FROM_P10 (*(struct st_gpio_from_p1 *)&GPIO.P10) /* GPIO_FROM_P10 */
272#define GPIO_FROM_P11 (*(struct st_gpio_from_p1 *)&GPIO.P11) /* GPIO_FROM_P11 */
273
274/* End of channel array defines of GPIO */
275
276
277#define GPIOP1 (GPIO.P1)
278#define GPIOP2 (GPIO.P2)
279#define GPIOP3 (GPIO.P3)
280#define GPIOP4 (GPIO.P4)
281#define GPIOP5 (GPIO.P5)
282#define GPIOP6 (GPIO.P6)
283#define GPIOP7 (GPIO.P7)
284#define GPIOP8 (GPIO.P8)
285#define GPIOP9 (GPIO.P9)
286#define GPIOP10 (GPIO.P10)
287#define GPIOP11 (GPIO.P11)
288#define GPIOPSR1 (GPIO.PSR1)
289#define GPIOPSR2 (GPIO.PSR2)
290#define GPIOPSR3 (GPIO.PSR3)
291#define GPIOPSR4 (GPIO.PSR4)
292#define GPIOPSR5 (GPIO.PSR5)
293#define GPIOPSR6 (GPIO.PSR6)
294#define GPIOPSR7 (GPIO.PSR7)
295#define GPIOPSR8 (GPIO.PSR8)
296#define GPIOPSR9 (GPIO.PSR9)
297#define GPIOPSR10 (GPIO.PSR10)
298#define GPIOPSR11 (GPIO.PSR11)
299#define GPIOPPR0 (GPIO.PPR0)
300#define GPIOPPR1 (GPIO.PPR1)
301#define GPIOPPR2 (GPIO.PPR2)
302#define GPIOPPR3 (GPIO.PPR3)
303#define GPIOPPR4 (GPIO.PPR4)
304#define GPIOPPR5 (GPIO.PPR5)
305#define GPIOPPR6 (GPIO.PPR6)
306#define GPIOPPR7 (GPIO.PPR7)
307#define GPIOPPR8 (GPIO.PPR8)
308#define GPIOPPR9 (GPIO.PPR9)
309#define GPIOPPR10 (GPIO.PPR10)
310#define GPIOPPR11 (GPIO.PPR11)
311#define GPIOPM1 (GPIO.PM1)
312#define GPIOPM2 (GPIO.PM2)
313#define GPIOPM3 (GPIO.PM3)
314#define GPIOPM4 (GPIO.PM4)
315#define GPIOPM5 (GPIO.PM5)
316#define GPIOPM6 (GPIO.PM6)
317#define GPIOPM7 (GPIO.PM7)
318#define GPIOPM8 (GPIO.PM8)
319#define GPIOPM9 (GPIO.PM9)
320#define GPIOPM10 (GPIO.PM10)
321#define GPIOPM11 (GPIO.PM11)
322#define GPIOPMC0 (GPIO.PMC0)
323#define GPIOPMC1 (GPIO.PMC1)
324#define GPIOPMC2 (GPIO.PMC2)
325#define GPIOPMC3 (GPIO.PMC3)
326#define GPIOPMC4 (GPIO.PMC4)
327#define GPIOPMC5 (GPIO.PMC5)
328#define GPIOPMC6 (GPIO.PMC6)
329#define GPIOPMC7 (GPIO.PMC7)
330#define GPIOPMC8 (GPIO.PMC8)
331#define GPIOPMC9 (GPIO.PMC9)
332#define GPIOPMC10 (GPIO.PMC10)
333#define GPIOPMC11 (GPIO.PMC11)
334#define GPIOPFC1 (GPIO.PFC1)
335#define GPIOPFC2 (GPIO.PFC2)
336#define GPIOPFC3 (GPIO.PFC3)
337#define GPIOPFC4 (GPIO.PFC4)
338#define GPIOPFC5 (GPIO.PFC5)
339#define GPIOPFC6 (GPIO.PFC6)
340#define GPIOPFC7 (GPIO.PFC7)
341#define GPIOPFC8 (GPIO.PFC8)
342#define GPIOPFC9 (GPIO.PFC9)
343#define GPIOPFC10 (GPIO.PFC10)
344#define GPIOPFC11 (GPIO.PFC11)
345#define GPIOPFCE1 (GPIO.PFCE1)
346#define GPIOPFCE2 (GPIO.PFCE2)
347#define GPIOPFCE3 (GPIO.PFCE3)
348#define GPIOPFCE4 (GPIO.PFCE4)
349#define GPIOPFCE5 (GPIO.PFCE5)
350#define GPIOPFCE6 (GPIO.PFCE6)
351#define GPIOPFCE7 (GPIO.PFCE7)
352#define GPIOPFCE8 (GPIO.PFCE8)
353#define GPIOPFCE9 (GPIO.PFCE9)
354#define GPIOPFCE10 (GPIO.PFCE10)
355#define GPIOPFCE11 (GPIO.PFCE11)
356#define GPIOPNOT1 (GPIO.PNOT1)
357#define GPIOPNOT2 (GPIO.PNOT2)
358#define GPIOPNOT3 (GPIO.PNOT3)
359#define GPIOPNOT4 (GPIO.PNOT4)
360#define GPIOPNOT5 (GPIO.PNOT5)
361#define GPIOPNOT6 (GPIO.PNOT6)
362#define GPIOPNOT7 (GPIO.PNOT7)
363#define GPIOPNOT8 (GPIO.PNOT8)
364#define GPIOPNOT9 (GPIO.PNOT9)
365#define GPIOPNOT10 (GPIO.PNOT10)
366#define GPIOPNOT11 (GPIO.PNOT11)
367#define GPIOPMSR1 (GPIO.PMSR1)
368#define GPIOPMSR2 (GPIO.PMSR2)
369#define GPIOPMSR3 (GPIO.PMSR3)
370#define GPIOPMSR4 (GPIO.PMSR4)
371#define GPIOPMSR5 (GPIO.PMSR5)
372#define GPIOPMSR6 (GPIO.PMSR6)
373#define GPIOPMSR7 (GPIO.PMSR7)
374#define GPIOPMSR8 (GPIO.PMSR8)
375#define GPIOPMSR9 (GPIO.PMSR9)
376#define GPIOPMSR10 (GPIO.PMSR10)
377#define GPIOPMSR11 (GPIO.PMSR11)
378#define GPIOPMCSR0 (GPIO.PMCSR0)
379#define GPIOPMCSR1 (GPIO.PMCSR1)
380#define GPIOPMCSR2 (GPIO.PMCSR2)
381#define GPIOPMCSR3 (GPIO.PMCSR3)
382#define GPIOPMCSR4 (GPIO.PMCSR4)
383#define GPIOPMCSR5 (GPIO.PMCSR5)
384#define GPIOPMCSR6 (GPIO.PMCSR6)
385#define GPIOPMCSR7 (GPIO.PMCSR7)
386#define GPIOPMCSR8 (GPIO.PMCSR8)
387#define GPIOPMCSR9 (GPIO.PMCSR9)
388#define GPIOPMCSR10 (GPIO.PMCSR10)
389#define GPIOPMCSR11 (GPIO.PMCSR11)
390#define GPIOPFCAE1 (GPIO.PFCAE1)
391#define GPIOPFCAE2 (GPIO.PFCAE2)
392#define GPIOPFCAE3 (GPIO.PFCAE3)
393#define GPIOPFCAE4 (GPIO.PFCAE4)
394#define GPIOPFCAE5 (GPIO.PFCAE5)
395#define GPIOPFCAE6 (GPIO.PFCAE6)
396#define GPIOPFCAE7 (GPIO.PFCAE7)
397#define GPIOPFCAE8 (GPIO.PFCAE8)
398#define GPIOPFCAE9 (GPIO.PFCAE9)
399#define GPIOPFCAE10 (GPIO.PFCAE10)
400#define GPIOPFCAE11 (GPIO.PFCAE11)
401#define GPIOSNCR (GPIO.SNCR)
402#define GPIOPIBC0 (GPIO.PIBC0)
403#define GPIOPIBC1 (GPIO.PIBC1)
404#define GPIOPIBC2 (GPIO.PIBC2)
405#define GPIOPIBC3 (GPIO.PIBC3)
406#define GPIOPIBC4 (GPIO.PIBC4)
407#define GPIOPIBC5 (GPIO.PIBC5)
408#define GPIOPIBC6 (GPIO.PIBC6)
409#define GPIOPIBC7 (GPIO.PIBC7)
410#define GPIOPIBC8 (GPIO.PIBC8)
411#define GPIOPIBC9 (GPIO.PIBC9)
412#define GPIOPIBC10 (GPIO.PIBC10)
413#define GPIOPIBC11 (GPIO.PIBC11)
414#define GPIOPBDC1 (GPIO.PBDC1)
415#define GPIOPBDC2 (GPIO.PBDC2)
416#define GPIOPBDC3 (GPIO.PBDC3)
417#define GPIOPBDC4 (GPIO.PBDC4)
418#define GPIOPBDC5 (GPIO.PBDC5)
419#define GPIOPBDC6 (GPIO.PBDC6)
420#define GPIOPBDC7 (GPIO.PBDC7)
421#define GPIOPBDC8 (GPIO.PBDC8)
422#define GPIOPBDC9 (GPIO.PBDC9)
423#define GPIOPBDC10 (GPIO.PBDC10)
424#define GPIOPBDC11 (GPIO.PBDC11)
425#define GPIOPIPC1 (GPIO.PIPC1)
426#define GPIOPIPC2 (GPIO.PIPC2)
427#define GPIOPIPC3 (GPIO.PIPC3)
428#define GPIOPIPC4 (GPIO.PIPC4)
429#define GPIOPIPC5 (GPIO.PIPC5)
430#define GPIOPIPC6 (GPIO.PIPC6)
431#define GPIOPIPC7 (GPIO.PIPC7)
432#define GPIOPIPC8 (GPIO.PIPC8)
433#define GPIOPIPC9 (GPIO.PIPC9)
434#define GPIOPIPC10 (GPIO.PIPC10)
435#define GPIOPIPC11 (GPIO.PIPC11)
436#define GPIOJPPR0 (GPIO.JPPR0)
437#define GPIOJPMC0 (GPIO.JPMC0)
438#define GPIOJPMCSR0 (GPIO.JPMCSR0)
439#define GPIOJPIBC0 (GPIO.JPIBC0)
440
441#define GPIO_PSRn_COUNT (11)
442#define GPIO_PMSRn_COUNT (11)
443#define GPIO_PMCSRn_COUNT (12)
444
445
446typedef struct st_gpio
447{
448 /* GPIO */
449
450/* start of struct st_gpio_from_p1 */
451 volatile uint16_t P1; /* P1 */
452 volatile uint8_t dummy348[2]; /* */
453
454/* end of struct st_gpio_from_p1 */
455
456/* start of struct st_gpio_from_p1 */
457 volatile uint16_t P2; /* P2 */
458 volatile uint8_t dummy349[2]; /* */
459
460/* end of struct st_gpio_from_p1 */
461
462/* start of struct st_gpio_from_p1 */
463 volatile uint16_t P3; /* P3 */
464 volatile uint8_t dummy350[2]; /* */
465
466/* end of struct st_gpio_from_p1 */
467
468/* start of struct st_gpio_from_p1 */
469 volatile uint16_t P4; /* P4 */
470 volatile uint8_t dummy351[2]; /* */
471
472/* end of struct st_gpio_from_p1 */
473
474/* start of struct st_gpio_from_p1 */
475 volatile uint16_t P5; /* P5 */
476 volatile uint8_t dummy352[2]; /* */
477
478/* end of struct st_gpio_from_p1 */
479
480/* start of struct st_gpio_from_p1 */
481 volatile uint16_t P6; /* P6 */
482 volatile uint8_t dummy353[2]; /* */
483
484/* end of struct st_gpio_from_p1 */
485
486/* start of struct st_gpio_from_p1 */
487 volatile uint16_t P7; /* P7 */
488 volatile uint8_t dummy354[2]; /* */
489
490/* end of struct st_gpio_from_p1 */
491
492/* start of struct st_gpio_from_p1 */
493 volatile uint16_t P8; /* P8 */
494 volatile uint8_t dummy355[2]; /* */
495
496/* end of struct st_gpio_from_p1 */
497
498/* start of struct st_gpio_from_p1 */
499 volatile uint16_t P9; /* P9 */
500 volatile uint8_t dummy356[2]; /* */
501
502/* end of struct st_gpio_from_p1 */
503
504/* start of struct st_gpio_from_p1 */
505 volatile uint16_t P10; /* P10 */
506 volatile uint8_t dummy357[2]; /* */
507
508/* end of struct st_gpio_from_p1 */
509
510/* start of struct st_gpio_from_p1 */
511 volatile uint16_t P11; /* P11 */
512 volatile uint8_t dummy3580[2]; /* */
513
514/* end of struct st_gpio_from_p1 */
515 volatile uint8_t dummy3581[212]; /* */
516
517/* #define GPIO_PSRn_COUNT (11) */
518 volatile uint32_t PSR1; /* PSR1 */
519 volatile uint32_t PSR2; /* PSR2 */
520 volatile uint32_t PSR3; /* PSR3 */
521 volatile uint32_t PSR4; /* PSR4 */
522 volatile uint32_t PSR5; /* PSR5 */
523 volatile uint32_t PSR6; /* PSR6 */
524 volatile uint32_t PSR7; /* PSR7 */
525 volatile uint32_t PSR8; /* PSR8 */
526 volatile uint32_t PSR9; /* PSR9 */
527 volatile uint32_t PSR10; /* PSR10 */
528 volatile uint32_t PSR11; /* PSR11 */
529 volatile uint8_t dummy359[208]; /* */
530
531/* start of struct st_gpio_from_ppr0 */
532 volatile uint16_t PPR0; /* PPR0 */
533 volatile uint8_t dummy360[2]; /* */
534
535/* end of struct st_gpio_from_ppr0 */
536
537/* start of struct st_gpio_from_ppr0 */
538 volatile uint16_t PPR1; /* PPR1 */
539 volatile uint8_t dummy361[2]; /* */
540
541/* end of struct st_gpio_from_ppr0 */
542
543/* start of struct st_gpio_from_ppr0 */
544 volatile uint16_t PPR2; /* PPR2 */
545 volatile uint8_t dummy362[2]; /* */
546
547/* end of struct st_gpio_from_ppr0 */
548
549/* start of struct st_gpio_from_ppr0 */
550 volatile uint16_t PPR3; /* PPR3 */
551 volatile uint8_t dummy363[2]; /* */
552
553/* end of struct st_gpio_from_ppr0 */
554
555/* start of struct st_gpio_from_ppr0 */
556 volatile uint16_t PPR4; /* PPR4 */
557 volatile uint8_t dummy364[2]; /* */
558
559/* end of struct st_gpio_from_ppr0 */
560
561/* start of struct st_gpio_from_ppr0 */
562 volatile uint16_t PPR5; /* PPR5 */
563 volatile uint8_t dummy365[2]; /* */
564
565/* end of struct st_gpio_from_ppr0 */
566
567/* start of struct st_gpio_from_ppr0 */
568 volatile uint16_t PPR6; /* PPR6 */
569 volatile uint8_t dummy366[2]; /* */
570
571/* end of struct st_gpio_from_ppr0 */
572
573/* start of struct st_gpio_from_ppr0 */
574 volatile uint16_t PPR7; /* PPR7 */
575 volatile uint8_t dummy367[2]; /* */
576
577/* end of struct st_gpio_from_ppr0 */
578
579/* start of struct st_gpio_from_ppr0 */
580 volatile uint16_t PPR8; /* PPR8 */
581 volatile uint8_t dummy368[2]; /* */
582
583/* end of struct st_gpio_from_ppr0 */
584
585/* start of struct st_gpio_from_ppr0 */
586 volatile uint16_t PPR9; /* PPR9 */
587 volatile uint8_t dummy369[2]; /* */
588
589/* end of struct st_gpio_from_ppr0 */
590
591/* start of struct st_gpio_from_ppr0 */
592 volatile uint16_t PPR10; /* PPR10 */
593 volatile uint8_t dummy370[2]; /* */
594
595/* end of struct st_gpio_from_ppr0 */
596
597/* start of struct st_gpio_from_ppr0 */
598 volatile uint16_t PPR11; /* PPR11 */
599 volatile uint8_t dummy3710[2]; /* */
600
601/* end of struct st_gpio_from_ppr0 */
602 volatile uint8_t dummy3711[212]; /* */
603
604/* start of struct st_gpio_from_pm1 */
605 volatile uint16_t PM1; /* PM1 */
606 volatile uint8_t dummy372[2]; /* */
607
608/* end of struct st_gpio_from_pm1 */
609
610/* start of struct st_gpio_from_pm1 */
611 volatile uint16_t PM2; /* PM2 */
612 volatile uint8_t dummy373[2]; /* */
613
614/* end of struct st_gpio_from_pm1 */
615
616/* start of struct st_gpio_from_pm1 */
617 volatile uint16_t PM3; /* PM3 */
618 volatile uint8_t dummy374[2]; /* */
619
620/* end of struct st_gpio_from_pm1 */
621
622/* start of struct st_gpio_from_pm1 */
623 volatile uint16_t PM4; /* PM4 */
624 volatile uint8_t dummy375[2]; /* */
625
626/* end of struct st_gpio_from_pm1 */
627
628/* start of struct st_gpio_from_pm1 */
629 volatile uint16_t PM5; /* PM5 */
630 volatile uint8_t dummy376[2]; /* */
631
632/* end of struct st_gpio_from_pm1 */
633
634/* start of struct st_gpio_from_pm1 */
635 volatile uint16_t PM6; /* PM6 */
636 volatile uint8_t dummy377[2]; /* */
637
638/* end of struct st_gpio_from_pm1 */
639
640/* start of struct st_gpio_from_pm1 */
641 volatile uint16_t PM7; /* PM7 */
642 volatile uint8_t dummy378[2]; /* */
643
644/* end of struct st_gpio_from_pm1 */
645
646/* start of struct st_gpio_from_pm1 */
647 volatile uint16_t PM8; /* PM8 */
648 volatile uint8_t dummy379[2]; /* */
649
650/* end of struct st_gpio_from_pm1 */
651
652/* start of struct st_gpio_from_pm1 */
653 volatile uint16_t PM9; /* PM9 */
654 volatile uint8_t dummy380[2]; /* */
655
656/* end of struct st_gpio_from_pm1 */
657
658/* start of struct st_gpio_from_pm1 */
659 volatile uint16_t PM10; /* PM10 */
660 volatile uint8_t dummy381[2]; /* */
661
662/* end of struct st_gpio_from_pm1 */
663
664/* start of struct st_gpio_from_pm1 */
665 volatile uint16_t PM11; /* PM11 */
666 volatile uint8_t dummy3820[2]; /* */
667
668/* end of struct st_gpio_from_pm1 */
669 volatile uint8_t dummy3821[208]; /* */
670
671/* start of struct st_gpio_from_pmc0 */
672 volatile uint16_t PMC0; /* PMC0 */
673 volatile uint8_t dummy383[2]; /* */
674
675/* end of struct st_gpio_from_pmc0 */
676
677/* start of struct st_gpio_from_pmc0 */
678 volatile uint16_t PMC1; /* PMC1 */
679 volatile uint8_t dummy384[2]; /* */
680
681/* end of struct st_gpio_from_pmc0 */
682
683/* start of struct st_gpio_from_pmc0 */
684 volatile uint16_t PMC2; /* PMC2 */
685 volatile uint8_t dummy385[2]; /* */
686
687/* end of struct st_gpio_from_pmc0 */
688
689/* start of struct st_gpio_from_pmc0 */
690 volatile uint16_t PMC3; /* PMC3 */
691 volatile uint8_t dummy386[2]; /* */
692
693/* end of struct st_gpio_from_pmc0 */
694
695/* start of struct st_gpio_from_pmc0 */
696 volatile uint16_t PMC4; /* PMC4 */
697 volatile uint8_t dummy387[2]; /* */
698
699/* end of struct st_gpio_from_pmc0 */
700
701/* start of struct st_gpio_from_pmc0 */
702 volatile uint16_t PMC5; /* PMC5 */
703 volatile uint8_t dummy388[2]; /* */
704
705/* end of struct st_gpio_from_pmc0 */
706
707/* start of struct st_gpio_from_pmc0 */
708 volatile uint16_t PMC6; /* PMC6 */
709 volatile uint8_t dummy389[2]; /* */
710
711/* end of struct st_gpio_from_pmc0 */
712
713/* start of struct st_gpio_from_pmc0 */
714 volatile uint16_t PMC7; /* PMC7 */
715 volatile uint8_t dummy390[2]; /* */
716
717/* end of struct st_gpio_from_pmc0 */
718
719/* start of struct st_gpio_from_pmc0 */
720 volatile uint16_t PMC8; /* PMC8 */
721 volatile uint8_t dummy391[2]; /* */
722
723/* end of struct st_gpio_from_pmc0 */
724
725/* start of struct st_gpio_from_pmc0 */
726 volatile uint16_t PMC9; /* PMC9 */
727 volatile uint8_t dummy392[2]; /* */
728
729/* end of struct st_gpio_from_pmc0 */
730
731/* start of struct st_gpio_from_pmc0 */
732 volatile uint16_t PMC10; /* PMC10 */
733 volatile uint8_t dummy393[2]; /* */
734
735/* end of struct st_gpio_from_pmc0 */
736
737/* start of struct st_gpio_from_pmc0 */
738 volatile uint16_t PMC11; /* PMC11 */
739 volatile uint8_t dummy3940[2]; /* */
740
741/* end of struct st_gpio_from_pmc0 */
742 volatile uint8_t dummy3941[212]; /* */
743
744/* start of struct st_gpio_from_pfc1 */
745 volatile uint16_t PFC1; /* PFC1 */
746 volatile uint8_t dummy395[2]; /* */
747
748/* end of struct st_gpio_from_pfc1 */
749
750/* start of struct st_gpio_from_pfc1 */
751 volatile uint16_t PFC2; /* PFC2 */
752 volatile uint8_t dummy396[2]; /* */
753
754/* end of struct st_gpio_from_pfc1 */
755
756/* start of struct st_gpio_from_pfc1 */
757 volatile uint16_t PFC3; /* PFC3 */
758 volatile uint8_t dummy397[2]; /* */
759
760/* end of struct st_gpio_from_pfc1 */
761
762/* start of struct st_gpio_from_pfc1 */
763 volatile uint16_t PFC4; /* PFC4 */
764 volatile uint8_t dummy398[2]; /* */
765
766/* end of struct st_gpio_from_pfc1 */
767
768/* start of struct st_gpio_from_pfc1 */
769 volatile uint16_t PFC5; /* PFC5 */
770 volatile uint8_t dummy399[2]; /* */
771
772/* end of struct st_gpio_from_pfc1 */
773
774/* start of struct st_gpio_from_pfc1 */
775 volatile uint16_t PFC6; /* PFC6 */
776 volatile uint8_t dummy400[2]; /* */
777
778/* end of struct st_gpio_from_pfc1 */
779
780/* start of struct st_gpio_from_pfc1 */
781 volatile uint16_t PFC7; /* PFC7 */
782 volatile uint8_t dummy401[2]; /* */
783
784/* end of struct st_gpio_from_pfc1 */
785
786/* start of struct st_gpio_from_pfc1 */
787 volatile uint16_t PFC8; /* PFC8 */
788 volatile uint8_t dummy402[2]; /* */
789
790/* end of struct st_gpio_from_pfc1 */
791
792/* start of struct st_gpio_from_pfc1 */
793 volatile uint16_t PFC9; /* PFC9 */
794 volatile uint8_t dummy403[2]; /* */
795
796/* end of struct st_gpio_from_pfc1 */
797
798/* start of struct st_gpio_from_pfc1 */
799 volatile uint16_t PFC10; /* PFC10 */
800 volatile uint8_t dummy404[2]; /* */
801
802/* end of struct st_gpio_from_pfc1 */
803
804/* start of struct st_gpio_from_pfc1 */
805 volatile uint16_t PFC11; /* PFC11 */
806 volatile uint8_t dummy4050[2]; /* */
807
808/* end of struct st_gpio_from_pfc1 */
809 volatile uint8_t dummy4051[212]; /* */
810
811/* start of struct st_gpio_from_pfce1 */
812 volatile uint16_t PFCE1; /* PFCE1 */
813 volatile uint8_t dummy406[2]; /* */
814
815/* end of struct st_gpio_from_pfce1 */
816
817/* start of struct st_gpio_from_pfce1 */
818 volatile uint16_t PFCE2; /* PFCE2 */
819 volatile uint8_t dummy407[2]; /* */
820
821/* end of struct st_gpio_from_pfce1 */
822
823/* start of struct st_gpio_from_pfce1 */
824 volatile uint16_t PFCE3; /* PFCE3 */
825 volatile uint8_t dummy408[2]; /* */
826
827/* end of struct st_gpio_from_pfce1 */
828
829/* start of struct st_gpio_from_pfce1 */
830 volatile uint16_t PFCE4; /* PFCE4 */
831 volatile uint8_t dummy409[2]; /* */
832
833/* end of struct st_gpio_from_pfce1 */
834
835/* start of struct st_gpio_from_pfce1 */
836 volatile uint16_t PFCE5; /* PFCE5 */
837 volatile uint8_t dummy410[2]; /* */
838
839/* end of struct st_gpio_from_pfce1 */
840
841/* start of struct st_gpio_from_pfce1 */
842 volatile uint16_t PFCE6; /* PFCE6 */
843 volatile uint8_t dummy411[2]; /* */
844
845/* end of struct st_gpio_from_pfce1 */
846
847/* start of struct st_gpio_from_pfce1 */
848 volatile uint16_t PFCE7; /* PFCE7 */
849 volatile uint8_t dummy412[2]; /* */
850
851/* end of struct st_gpio_from_pfce1 */
852
853/* start of struct st_gpio_from_pfce1 */
854 volatile uint16_t PFCE8; /* PFCE8 */
855 volatile uint8_t dummy413[2]; /* */
856
857/* end of struct st_gpio_from_pfce1 */
858
859/* start of struct st_gpio_from_pfce1 */
860 volatile uint16_t PFCE9; /* PFCE9 */
861 volatile uint8_t dummy414[2]; /* */
862
863/* end of struct st_gpio_from_pfce1 */
864
865/* start of struct st_gpio_from_pfce1 */
866 volatile uint16_t PFCE10; /* PFCE10 */
867 volatile uint8_t dummy415[2]; /* */
868
869/* end of struct st_gpio_from_pfce1 */
870
871/* start of struct st_gpio_from_pfce1 */
872 volatile uint16_t PFCE11; /* PFCE11 */
873 volatile uint8_t dummy4160[2]; /* */
874
875/* end of struct st_gpio_from_pfce1 */
876 volatile uint8_t dummy4161[212]; /* */
877
878/* start of struct st_gpio_from_pnot1 */
879 volatile uint16_t PNOT1; /* PNOT1 */
880 volatile uint8_t dummy417[2]; /* */
881
882/* end of struct st_gpio_from_pnot1 */
883
884/* start of struct st_gpio_from_pnot1 */
885 volatile uint16_t PNOT2; /* PNOT2 */
886 volatile uint8_t dummy418[2]; /* */
887
888/* end of struct st_gpio_from_pnot1 */
889
890/* start of struct st_gpio_from_pnot1 */
891 volatile uint16_t PNOT3; /* PNOT3 */
892 volatile uint8_t dummy419[2]; /* */
893
894/* end of struct st_gpio_from_pnot1 */
895
896/* start of struct st_gpio_from_pnot1 */
897 volatile uint16_t PNOT4; /* PNOT4 */
898 volatile uint8_t dummy420[2]; /* */
899
900/* end of struct st_gpio_from_pnot1 */
901
902/* start of struct st_gpio_from_pnot1 */
903 volatile uint16_t PNOT5; /* PNOT5 */
904 volatile uint8_t dummy421[2]; /* */
905
906/* end of struct st_gpio_from_pnot1 */
907
908/* start of struct st_gpio_from_pnot1 */
909 volatile uint16_t PNOT6; /* PNOT6 */
910 volatile uint8_t dummy422[2]; /* */
911
912/* end of struct st_gpio_from_pnot1 */
913
914/* start of struct st_gpio_from_pnot1 */
915 volatile uint16_t PNOT7; /* PNOT7 */
916 volatile uint8_t dummy423[2]; /* */
917
918/* end of struct st_gpio_from_pnot1 */
919
920/* start of struct st_gpio_from_pnot1 */
921 volatile uint16_t PNOT8; /* PNOT8 */
922 volatile uint8_t dummy424[2]; /* */
923
924/* end of struct st_gpio_from_pnot1 */
925
926/* start of struct st_gpio_from_pnot1 */
927 volatile uint16_t PNOT9; /* PNOT9 */
928 volatile uint8_t dummy425[2]; /* */
929
930/* end of struct st_gpio_from_pnot1 */
931
932/* start of struct st_gpio_from_pnot1 */
933 volatile uint16_t PNOT10; /* PNOT10 */
934 volatile uint8_t dummy426[2]; /* */
935
936/* end of struct st_gpio_from_pnot1 */
937
938/* start of struct st_gpio_from_pnot1 */
939 volatile uint16_t PNOT11; /* PNOT11 */
940 volatile uint8_t dummy4270[2]; /* */
941
942/* end of struct st_gpio_from_pnot1 */
943 volatile uint8_t dummy4271[212]; /* */
944
945/* #define GPIO_PMSRn_COUNT (11) */
946 volatile uint32_t PMSR1; /* PMSR1 */
947 volatile uint32_t PMSR2; /* PMSR2 */
948 volatile uint32_t PMSR3; /* PMSR3 */
949 volatile uint32_t PMSR4; /* PMSR4 */
950 volatile uint32_t PMSR5; /* PMSR5 */
951 volatile uint32_t PMSR6; /* PMSR6 */
952 volatile uint32_t PMSR7; /* PMSR7 */
953 volatile uint32_t PMSR8; /* PMSR8 */
954 volatile uint32_t PMSR9; /* PMSR9 */
955 volatile uint32_t PMSR10; /* PMSR10 */
956 volatile uint32_t PMSR11; /* PMSR11 */
957 volatile uint8_t dummy428[208]; /* */
958
959/* #define GPIO_PMCSRn_COUNT (12) */
960 volatile uint32_t PMCSR0; /* PMCSR0 */
961 volatile uint32_t PMCSR1; /* PMCSR1 */
962 volatile uint32_t PMCSR2; /* PMCSR2 */
963 volatile uint32_t PMCSR3; /* PMCSR3 */
964 volatile uint32_t PMCSR4; /* PMCSR4 */
965 volatile uint32_t PMCSR5; /* PMCSR5 */
966 volatile uint32_t PMCSR6; /* PMCSR6 */
967 volatile uint32_t PMCSR7; /* PMCSR7 */
968 volatile uint32_t PMCSR8; /* PMCSR8 */
969 volatile uint32_t PMCSR9; /* PMCSR9 */
970 volatile uint32_t PMCSR10; /* PMCSR10 */
971 volatile uint32_t PMCSR11; /* PMCSR11 */
972 volatile uint8_t dummy429[212]; /* */
973
974/* start of struct st_gpio_from_pfcae1 */
975 volatile uint16_t PFCAE1; /* PFCAE1 */
976 volatile uint8_t dummy430[2]; /* */
977
978/* end of struct st_gpio_from_pfcae1 */
979
980/* start of struct st_gpio_from_pfcae1 */
981 volatile uint16_t PFCAE2; /* PFCAE2 */
982 volatile uint8_t dummy431[2]; /* */
983
984/* end of struct st_gpio_from_pfcae1 */
985
986/* start of struct st_gpio_from_pfcae1 */
987 volatile uint16_t PFCAE3; /* PFCAE3 */
988 volatile uint8_t dummy432[2]; /* */
989
990/* end of struct st_gpio_from_pfcae1 */
991
992/* start of struct st_gpio_from_pfcae1 */
993 volatile uint16_t PFCAE4; /* PFCAE4 */
994 volatile uint8_t dummy433[2]; /* */
995
996/* end of struct st_gpio_from_pfcae1 */
997
998/* start of struct st_gpio_from_pfcae1 */
999 volatile uint16_t PFCAE5; /* PFCAE5 */
1000 volatile uint8_t dummy434[2]; /* */
1001
1002/* end of struct st_gpio_from_pfcae1 */
1003
1004/* start of struct st_gpio_from_pfcae1 */
1005 volatile uint16_t PFCAE6; /* PFCAE6 */
1006 volatile uint8_t dummy435[2]; /* */
1007
1008/* end of struct st_gpio_from_pfcae1 */
1009
1010/* start of struct st_gpio_from_pfcae1 */
1011 volatile uint16_t PFCAE7; /* PFCAE7 */
1012 volatile uint8_t dummy436[2]; /* */
1013
1014/* end of struct st_gpio_from_pfcae1 */
1015
1016/* start of struct st_gpio_from_pfcae1 */
1017 volatile uint16_t PFCAE8; /* PFCAE8 */
1018 volatile uint8_t dummy437[2]; /* */
1019
1020/* end of struct st_gpio_from_pfcae1 */
1021
1022/* start of struct st_gpio_from_pfcae1 */
1023 volatile uint16_t PFCAE9; /* PFCAE9 */
1024 volatile uint8_t dummy438[2]; /* */
1025
1026/* end of struct st_gpio_from_pfcae1 */
1027
1028/* start of struct st_gpio_from_pfcae1 */
1029 volatile uint16_t PFCAE10; /* PFCAE10 */
1030 volatile uint8_t dummy439[2]; /* */
1031
1032/* end of struct st_gpio_from_pfcae1 */
1033
1034/* start of struct st_gpio_from_pfcae1 */
1035 volatile uint16_t PFCAE11; /* PFCAE11 */
1036 volatile uint8_t dummy4400[2]; /* */
1037
1038/* end of struct st_gpio_from_pfcae1 */
1039 volatile uint8_t dummy4401[464]; /* */
1040 volatile uint32_t SNCR; /* SNCR */
1041 volatile uint8_t dummy441[13308]; /* */
1042
1043/* start of struct st_gpio_from_pibc1 */
1044 volatile uint16_t PIBC0; /* PIBC0 */
1045 volatile uint8_t dummy442[2]; /* */
1046
1047/* end of struct st_gpio_from_pibc1 */
1048
1049/* start of struct st_gpio_from_pibc1 */
1050 volatile uint16_t PIBC1; /* PIBC1 */
1051 volatile uint8_t dummy443[2]; /* */
1052
1053/* end of struct st_gpio_from_pibc1 */
1054
1055/* start of struct st_gpio_from_pibc1 */
1056 volatile uint16_t PIBC2; /* PIBC2 */
1057 volatile uint8_t dummy444[2]; /* */
1058
1059/* end of struct st_gpio_from_pibc1 */
1060
1061/* start of struct st_gpio_from_pibc1 */
1062 volatile uint16_t PIBC3; /* PIBC3 */
1063 volatile uint8_t dummy445[2]; /* */
1064
1065/* end of struct st_gpio_from_pibc1 */
1066
1067/* start of struct st_gpio_from_pibc1 */
1068 volatile uint16_t PIBC4; /* PIBC4 */
1069 volatile uint8_t dummy446[2]; /* */
1070
1071/* end of struct st_gpio_from_pibc1 */
1072
1073/* start of struct st_gpio_from_pibc1 */
1074 volatile uint16_t PIBC5; /* PIBC5 */
1075 volatile uint8_t dummy447[2]; /* */
1076
1077/* end of struct st_gpio_from_pibc1 */
1078
1079/* start of struct st_gpio_from_pibc1 */
1080 volatile uint16_t PIBC6; /* PIBC6 */
1081 volatile uint8_t dummy448[2]; /* */
1082
1083/* end of struct st_gpio_from_pibc1 */
1084
1085/* start of struct st_gpio_from_pibc1 */
1086 volatile uint16_t PIBC7; /* PIBC7 */
1087 volatile uint8_t dummy449[2]; /* */
1088
1089/* end of struct st_gpio_from_pibc1 */
1090
1091/* start of struct st_gpio_from_pibc1 */
1092 volatile uint16_t PIBC8; /* PIBC8 */
1093 volatile uint8_t dummy450[2]; /* */
1094
1095/* end of struct st_gpio_from_pibc1 */
1096
1097/* start of struct st_gpio_from_pibc1 */
1098 volatile uint16_t PIBC9; /* PIBC9 */
1099 volatile uint8_t dummy451[2]; /* */
1100
1101/* end of struct st_gpio_from_pibc1 */
1102
1103/* start of struct st_gpio_from_pibc1 */
1104 volatile uint16_t PIBC10; /* PIBC10 */
1105 volatile uint8_t dummy452[2]; /* */
1106
1107/* end of struct st_gpio_from_pibc1 */
1108
1109/* start of struct st_gpio_from_pibc1 */
1110 volatile uint16_t PIBC11; /* PIBC11 */
1111 volatile uint8_t dummy4530[2]; /* */
1112
1113/* end of struct st_gpio_from_pibc1 */
1114 volatile uint8_t dummy4531[212]; /* */
1115
1116/* start of struct st_gpio_from_pbdc1 */
1117 volatile uint16_t PBDC1; /* PBDC1 */
1118 volatile uint8_t dummy454[2]; /* */
1119
1120/* end of struct st_gpio_from_pbdc1 */
1121
1122/* start of struct st_gpio_from_pbdc1 */
1123 volatile uint16_t PBDC2; /* PBDC2 */
1124 volatile uint8_t dummy455[2]; /* */
1125
1126/* end of struct st_gpio_from_pbdc1 */
1127
1128/* start of struct st_gpio_from_pbdc1 */
1129 volatile uint16_t PBDC3; /* PBDC3 */
1130 volatile uint8_t dummy456[2]; /* */
1131
1132/* end of struct st_gpio_from_pbdc1 */
1133
1134/* start of struct st_gpio_from_pbdc1 */
1135 volatile uint16_t PBDC4; /* PBDC4 */
1136 volatile uint8_t dummy457[2]; /* */
1137
1138/* end of struct st_gpio_from_pbdc1 */
1139
1140/* start of struct st_gpio_from_pbdc1 */
1141 volatile uint16_t PBDC5; /* PBDC5 */
1142 volatile uint8_t dummy458[2]; /* */
1143
1144/* end of struct st_gpio_from_pbdc1 */
1145
1146/* start of struct st_gpio_from_pbdc1 */
1147 volatile uint16_t PBDC6; /* PBDC6 */
1148 volatile uint8_t dummy459[2]; /* */
1149
1150/* end of struct st_gpio_from_pbdc1 */
1151
1152/* start of struct st_gpio_from_pbdc1 */
1153 volatile uint16_t PBDC7; /* PBDC7 */
1154 volatile uint8_t dummy460[2]; /* */
1155
1156/* end of struct st_gpio_from_pbdc1 */
1157
1158/* start of struct st_gpio_from_pbdc1 */
1159 volatile uint16_t PBDC8; /* PBDC8 */
1160 volatile uint8_t dummy461[2]; /* */
1161
1162/* end of struct st_gpio_from_pbdc1 */
1163
1164/* start of struct st_gpio_from_pbdc1 */
1165 volatile uint16_t PBDC9; /* PBDC9 */
1166 volatile uint8_t dummy462[2]; /* */
1167
1168/* end of struct st_gpio_from_pbdc1 */
1169
1170/* start of struct st_gpio_from_pbdc1 */
1171 volatile uint16_t PBDC10; /* PBDC10 */
1172 volatile uint8_t dummy463[2]; /* */
1173
1174/* end of struct st_gpio_from_pbdc1 */
1175
1176/* start of struct st_gpio_from_pbdc1 */
1177 volatile uint16_t PBDC11; /* PBDC11 */
1178 volatile uint8_t dummy4640[2]; /* */
1179
1180/* end of struct st_gpio_from_pbdc1 */
1181 volatile uint8_t dummy4641[212]; /* */
1182
1183/* start of struct st_gpio_from_pipc1 */
1184 volatile uint16_t PIPC1; /* PIPC1 */
1185 volatile uint8_t dummy465[2]; /* */
1186
1187/* end of struct st_gpio_from_pipc1 */
1188
1189/* start of struct st_gpio_from_pipc1 */
1190 volatile uint16_t PIPC2; /* PIPC2 */
1191 volatile uint8_t dummy466[2]; /* */
1192
1193/* end of struct st_gpio_from_pipc1 */
1194
1195/* start of struct st_gpio_from_pipc1 */
1196 volatile uint16_t PIPC3; /* PIPC3 */
1197 volatile uint8_t dummy467[2]; /* */
1198
1199/* end of struct st_gpio_from_pipc1 */
1200
1201/* start of struct st_gpio_from_pipc1 */
1202 volatile uint16_t PIPC4; /* PIPC4 */
1203 volatile uint8_t dummy468[2]; /* */
1204
1205/* end of struct st_gpio_from_pipc1 */
1206
1207/* start of struct st_gpio_from_pipc1 */
1208 volatile uint16_t PIPC5; /* PIPC5 */
1209 volatile uint8_t dummy469[2]; /* */
1210
1211/* end of struct st_gpio_from_pipc1 */
1212
1213/* start of struct st_gpio_from_pipc1 */
1214 volatile uint16_t PIPC6; /* PIPC6 */
1215 volatile uint8_t dummy470[2]; /* */
1216
1217/* end of struct st_gpio_from_pipc1 */
1218
1219/* start of struct st_gpio_from_pipc1 */
1220 volatile uint16_t PIPC7; /* PIPC7 */
1221 volatile uint8_t dummy471[2]; /* */
1222
1223/* end of struct st_gpio_from_pipc1 */
1224
1225/* start of struct st_gpio_from_pipc1 */
1226 volatile uint16_t PIPC8; /* PIPC8 */
1227 volatile uint8_t dummy472[2]; /* */
1228
1229/* end of struct st_gpio_from_pipc1 */
1230
1231/* start of struct st_gpio_from_pipc1 */
1232 volatile uint16_t PIPC9; /* PIPC9 */
1233 volatile uint8_t dummy473[2]; /* */
1234
1235/* end of struct st_gpio_from_pipc1 */
1236
1237/* start of struct st_gpio_from_pipc1 */
1238 volatile uint16_t PIPC10; /* PIPC10 */
1239 volatile uint8_t dummy474[2]; /* */
1240
1241/* end of struct st_gpio_from_pipc1 */
1242
1243/* start of struct st_gpio_from_pipc1 */
1244 volatile uint16_t PIPC11; /* PIPC11 */
1245 volatile uint8_t dummy4750[2]; /* */
1246
1247/* end of struct st_gpio_from_pipc1 */
1248 volatile uint8_t dummy4751[2288]; /* */
1249 volatile uint16_t JPPR0; /* JPPR0 */
1250 volatile uint8_t dummy476[30]; /* */
1251 volatile uint16_t JPMC0; /* JPMC0 */
1252 volatile uint8_t dummy477[78]; /* */
1253 volatile uint32_t JPMCSR0; /* JPMCSR0 */
1254 volatile uint8_t dummy478[876]; /* */
1255 volatile uint16_t JPIBC0; /* JPIBC0 */
1256} r_io_gpio_t;
1257
1258
1259typedef struct st_gpio_from_p1
1260{
1261
1262 volatile uint16_t P1; /* P1 */
1263 volatile uint8_t dummy1[3]; /* */
1264} r_io_gpio_from_p1_t;
1265
1266
1267typedef struct st_gpio_from_ppr0
1268{
1269
1270 volatile uint16_t PPR0; /* PPR0 */
1271 volatile uint8_t dummy1[2]; /* */
1272} r_io_gpio_from_ppr0_t;
1273
1274
1275typedef struct st_gpio_from_pm1
1276{
1277
1278 volatile uint16_t PM1; /* PM1 */
1279 volatile uint8_t dummy1[2]; /* */
1280} r_io_gpio_from_pm1_t;
1281
1282
1283typedef struct st_gpio_from_pmc0
1284{
1285
1286 volatile uint16_t PMC0; /* PMC0 */
1287 volatile uint8_t dummy1[2]; /* */
1288} r_io_gpio_from_pmc0_t;
1289
1290
1291typedef struct st_gpio_from_pfc1
1292{
1293
1294 volatile uint16_t PFC1; /* PFC1 */
1295 volatile uint8_t dummy1[2]; /* */
1296} r_io_gpio_from_pfc1_t;
1297
1298
1299typedef struct st_gpio_from_pfce1
1300{
1301
1302 volatile uint16_t PFCE1; /* PFCE1 */
1303 volatile uint8_t dummy1[2]; /* */
1304} r_io_gpio_from_pfce1_t;
1305
1306
1307typedef struct st_gpio_from_pnot1
1308{
1309
1310 volatile uint16_t PNOT1; /* PNOT1 */
1311 volatile uint8_t dummy1[2]; /* */
1312} r_io_gpio_from_pnot1_t;
1313
1314
1315typedef struct st_gpio_from_pfcae1
1316{
1317
1318 volatile uint16_t PFCAE1; /* PFCAE1 */
1319 volatile uint8_t dummy1[2]; /* */
1320} r_io_gpio_from_pfcae1_t;
1321
1322
1323typedef struct st_gpio_from_pibc1
1324{
1325
1326 volatile uint16_t PIBC1; /* PIBC1 */
1327 volatile uint8_t dummy1[2]; /* */
1328} r_io_gpio_from_pibc1_t;
1329
1330
1331typedef struct st_gpio_from_pbdc1
1332{
1333
1334 volatile uint16_t PBDC1; /* PBDC1 */
1335 volatile uint8_t dummy1[2]; /* */
1336} r_io_gpio_from_pbdc1_t;
1337
1338
1339typedef struct st_gpio_from_pipc1
1340{
1341
1342 volatile uint16_t PIPC1; /* PIPC1 */
1343 volatile uint8_t dummy1[2]; /* */
1344} r_io_gpio_from_pipc1_t;
1345
1346
1347/* Channel array defines of GPIO (2)*/
1348#ifdef DECLARE_GPIO_FROM_PIPC1_ARRAY_CHANNELS
1349volatile struct st_gpio_from_pipc1* GPIO_FROM_PIPC1_ARRAY[ GPIO_FROM_PIPC1_ARRAY_COUNT ] =
1350 /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */
1351 GPIO_FROM_PIPC1_ARRAY_ADDRESS_LIST;
1352 /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */
1353#endif /* DECLARE_GPIO_FROM_PIPC1_ARRAY_CHANNELS */
1354
1355#ifdef DECLARE_GPIO_FROM_PBDC1_ARRAY_CHANNELS
1356volatile struct st_gpio_from_pbdc1* GPIO_FROM_PBDC1_ARRAY[ GPIO_FROM_PBDC1_ARRAY_COUNT ] =
1357 /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */
1358 GPIO_FROM_PBDC1_ARRAY_ADDRESS_LIST;
1359 /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */
1360#endif /* DECLARE_GPIO_FROM_PBDC1_ARRAY_CHANNELS */
1361
1362#ifdef DECLARE_GPIO_FROM_PIBC1_ARRAY_CHANNELS
1363volatile struct st_gpio_from_pibc1* GPIO_FROM_PIBC1_ARRAY[ GPIO_FROM_PIBC1_ARRAY_COUNT ] =
1364 /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */
1365 GPIO_FROM_PIBC1_ARRAY_ADDRESS_LIST;
1366 /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */
1367#endif /* DECLARE_GPIO_FROM_PIBC1_ARRAY_CHANNELS */
1368
1369#ifdef DECLARE_GPIO_FROM_PFCAE1_ARRAY_CHANNELS
1370volatile struct st_gpio_from_pfcae1* GPIO_FROM_PFCAE1_ARRAY[ GPIO_FROM_PFCAE1_ARRAY_COUNT ] =
1371 /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */
1372 GPIO_FROM_PFCAE1_ARRAY_ADDRESS_LIST;
1373 /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */
1374#endif /* DECLARE_GPIO_FROM_PFCAE1_ARRAY_CHANNELS */
1375
1376#ifdef DECLARE_GPIO_FROM_PNOT1_ARRAY_CHANNELS
1377volatile struct st_gpio_from_pnot1* GPIO_FROM_PNOT1_ARRAY[ GPIO_FROM_PNOT1_ARRAY_COUNT ] =
1378 /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */
1379 GPIO_FROM_PNOT1_ARRAY_ADDRESS_LIST;
1380 /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */
1381#endif /* DECLARE_GPIO_FROM_PNOT1_ARRAY_CHANNELS */
1382
1383#ifdef DECLARE_GPIO_FROM_PFCE1_ARRAY_CHANNELS
1384volatile struct st_gpio_from_pfce1* GPIO_FROM_PFCE1_ARRAY[ GPIO_FROM_PFCE1_ARRAY_COUNT ] =
1385 /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */
1386 GPIO_FROM_PFCE1_ARRAY_ADDRESS_LIST;
1387 /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */
1388#endif /* DECLARE_GPIO_FROM_PFCE1_ARRAY_CHANNELS */
1389
1390#ifdef DECLARE_GPIO_FROM_PFC1_ARRAY_CHANNELS
1391volatile struct st_gpio_from_pfc1* GPIO_FROM_PFC1_ARRAY[ GPIO_FROM_PFC1_ARRAY_COUNT ] =
1392 /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */
1393 GPIO_FROM_PFC1_ARRAY_ADDRESS_LIST;
1394 /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */
1395#endif /* DECLARE_GPIO_FROM_PFC1_ARRAY_CHANNELS */
1396
1397#ifdef DECLARE_GPIO_FROM_PMC0_ARRAY_CHANNELS
1398volatile struct st_gpio_from_pmc0* GPIO_FROM_PMC0_ARRAY[ GPIO_FROM_PMC0_ARRAY_COUNT ] =
1399 /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */
1400 GPIO_FROM_PMC0_ARRAY_ADDRESS_LIST;
1401 /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */
1402#endif /* DECLARE_GPIO_FROM_PMC0_ARRAY_CHANNELS */
1403
1404#ifdef DECLARE_GPIO_FROM_PM1_ARRAY_CHANNELS
1405volatile struct st_gpio_from_pm1* GPIO_FROM_PM1_ARRAY[ GPIO_FROM_PM1_ARRAY_COUNT ] =
1406 /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */
1407 GPIO_FROM_PM1_ARRAY_ADDRESS_LIST;
1408 /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */
1409#endif /* DECLARE_GPIO_FROM_PM1_ARRAY_CHANNELS */
1410
1411#ifdef DECLARE_GPIO_FROM_PPR0_ARRAY_CHANNELS
1412volatile struct st_gpio_from_ppr0* GPIO_FROM_PPR0_ARRAY[ GPIO_FROM_PPR0_ARRAY_COUNT ] =
1413 /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */
1414 GPIO_FROM_PPR0_ARRAY_ADDRESS_LIST;
1415 /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */
1416#endif /* DECLARE_GPIO_FROM_PPR0_ARRAY_CHANNELS */
1417
1418#ifdef DECLARE_GPIO_FROM_P1_ARRAY_CHANNELS
1419volatile struct st_gpio_from_p1* GPIO_FROM_P1_ARRAY[ GPIO_FROM_P1_ARRAY_COUNT ] =
1420 /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */
1421 GPIO_FROM_P1_ARRAY_ADDRESS_LIST;
1422 /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */
1423#endif /* DECLARE_GPIO_FROM_P1_ARRAY_CHANNELS */
1424/* End of channel array defines of GPIO (2)*/
1425
1426
1427/* <-SEC M1.10.1 */
1428/* <-MISRA 18.4 */ /* <-SEC M1.6.2 */
1429/* <-QAC 0857 */
1430/* <-QAC 0639 */
1431#endif
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