source: asp3_tinet_ecnl_arm/trunk/asp3_dcre/mbed/targets/TARGET_RENESAS/TARGET_RZA1XX/TARGET_RZ_A1H/device/inc/iodefines/flctl_iodefine.h@ 374

Last change on this file since 374 was 374, checked in by coas-nagasima, 5 years ago

mbed関連を更新
シリアルドライバをmbedのHALを使うよう変更
ファイルディスクリプタの処理を更新
  • Property svn:eol-style set to native
  • Property svn:mime-type set to text/x-chdr;charset=UTF-8
File size: 4.0 KB
Line 
1/*******************************************************************************
2* DISCLAIMER
3* This software is supplied by Renesas Electronics Corporation and is only
4* intended for use with Renesas products. No other uses are authorized. This
5* software is owned by Renesas Electronics Corporation and is protected under
6* all applicable laws, including copyright laws.
7* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
8* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
9* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
10* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
11* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
12* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
13* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
14* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
15* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
16* Renesas reserves the right, without notice, to make changes to this software
17* and to discontinue the availability of this software. By using this software,
18* you agree to the additional terms and conditions found by accessing the
19* following link:
20* http://www.renesas.com/disclaimer*
21* Copyright (C) 2013-2015 Renesas Electronics Corporation. All rights reserved.
22*******************************************************************************/
23/*******************************************************************************
24* File Name : flctl_iodefine.h
25* $Rev: $
26* $Date:: $
27* Description : Definition of I/O Register for RZ/A1H,M (V2.00h)
28******************************************************************************/
29#ifndef FLCTL_IODEFINE_H
30#define FLCTL_IODEFINE_H
31/* ->QAC 0639 : Over 127 members (C90) */
32/* ->QAC 0857 : Over 1024 #define (C90) */
33/* ->MISRA 18.4 : Pack unpack union */ /* ->SEC M1.6.2 */
34/* ->SEC M1.10.1 : Not magic number */
35
36#define FLCTL (*(struct st_flctl *)0xFCFF4000uL) /* FLCTL */
37
38
39#define FLCTLFLCMNCR (FLCTL.FLCMNCR)
40#define FLCTLFLCMDCR (FLCTL.FLCMDCR)
41#define FLCTLFLCMCDR (FLCTL.FLCMCDR)
42#define FLCTLFLADR (FLCTL.FLADR)
43#define FLCTLFLDATAR (FLCTL.FLDATAR)
44#define FLCTLFLDTCNTR (FLCTL.FLDTCNTR)
45#define FLCTLFLINTDMACR (FLCTL.FLINTDMACR)
46#define FLCTLFLBSYTMR (FLCTL.FLBSYTMR)
47#define FLCTLFLBSYCNT (FLCTL.FLBSYCNT)
48#define FLCTLFLTRCR (FLCTL.FLTRCR)
49#define FLCTLFLADR2 (FLCTL.FLADR2)
50#define FLCTLFLDTFIFO (FLCTL.FLDTFIFO)
51
52
53typedef struct st_flctl
54{
55 /* FLCTL */
56 volatile uint32_t FLCMNCR; /* FLCMNCR */
57 volatile uint32_t FLCMDCR; /* FLCMDCR */
58 volatile uint32_t FLCMCDR; /* FLCMCDR */
59 volatile uint32_t FLADR; /* FLADR */
60 volatile uint32_t FLDATAR; /* FLDATAR */
61 volatile uint32_t FLDTCNTR; /* FLDTCNTR */
62 volatile uint32_t FLINTDMACR; /* FLINTDMACR */
63 volatile uint32_t FLBSYTMR; /* FLBSYTMR */
64 volatile uint32_t FLBSYCNT; /* FLBSYCNT */
65 volatile uint8_t dummy555[8]; /* */
66 volatile uint8_t FLTRCR; /* FLTRCR */
67 volatile uint8_t dummy556[15]; /* */
68 volatile uint32_t FLADR2; /* FLADR2 */
69 volatile uint8_t dummy557[16]; /* */
70 volatile uint32_t FLDTFIFO; /* FLDTFIFO */
71} r_io_flctl_t;
72
73
74/* <-SEC M1.10.1 */
75/* <-MISRA 18.4 */ /* <-SEC M1.6.2 */
76/* <-QAC 0857 */
77/* <-QAC 0639 */
78#endif
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