source: asp3_tinet_ecnl_arm/trunk/asp3_dcre/mbed/targets/TARGET_RENESAS/TARGET_RZA1XX/TARGET_RZ_A1H/device/inc/iodefines/dmac_iodefine.h@ 374

Last change on this file since 374 was 374, checked in by coas-nagasima, 5 years ago

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[352]1/*******************************************************************************
2* DISCLAIMER
3* This software is supplied by Renesas Electronics Corporation and is only
4* intended for use with Renesas products. No other uses are authorized. This
5* software is owned by Renesas Electronics Corporation and is protected under
6* all applicable laws, including copyright laws.
7* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
8* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
9* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
10* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
11* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
12* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
13* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
14* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
15* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
16* Renesas reserves the right, without notice, to make changes to this software
17* and to discontinue the availability of this software. By using this software,
18* you agree to the additional terms and conditions found by accessing the
19* following link:
20* http://www.renesas.com/disclaimer*
[374]21* Copyright (C) 2013-2015 Renesas Electronics Corporation. All rights reserved.
[352]22*******************************************************************************/
23/*******************************************************************************
24* File Name : dmac_iodefine.h
25* $Rev: $
26* $Date:: $
[374]27* Description : Definition of I/O Register for RZ/A1H,M (V2.00h)
[352]28******************************************************************************/
29#ifndef DMAC_IODEFINE_H
30#define DMAC_IODEFINE_H
31/* ->QAC 0639 : Over 127 members (C90) */
[374]32/* ->QAC 0857 : Over 1024 #define (C90) */
33/* ->MISRA 18.4 : Pack unpack union */ /* ->SEC M1.6.2 */
[352]34/* ->SEC M1.10.1 : Not magic number */
35
[374]36
37
38/* Channel array defines of DMACmm */
39#define DMACmm_COUNT (8)
40#define DMACmm_ADDRESS_LIST \
41{ /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \
42 &DMAC01, &DMAC23, &DMAC45, &DMAC67, &DMAC89, &DMAC1011, &DMAC1213, &DMAC1415 \
43} /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */
44#define DMAC01 (*(struct st_dmars_mm *)&DMAC.DMARS0) /* DMAC0-1 */
45#define DMAC23 (*(struct st_dmars_mm *)&DMAC.DMARS1) /* DMAC2-3 */
46#define DMAC45 (*(struct st_dmars_mm *)&DMAC.DMARS2) /* DMAC4-5 */
47#define DMAC67 (*(struct st_dmars_mm *)&DMAC.DMARS3) /* DMAC6-7 */
48#define DMAC89 (*(struct st_dmars_mm *)&DMAC.DMARS4) /* DMAC8-9 */
49#define DMAC1011 (*(struct st_dmars_mm *)&DMAC.DMARS5) /* DMAC10-11 */
50#define DMAC1213 (*(struct st_dmars_mm *)&DMAC.DMARS6) /* DMAC12-13 */
51#define DMAC1415 (*(struct st_dmars_mm *)&DMAC.DMARS7) /* DMAC14-15 */
52
53
54/*(Sample) value = DMACmm[ channel / 2 ]->DMARS; */
55#define DMAC (*(struct st_dmac *)0xE8200000uL) /* DMAC */
56
57
58/* Start of channel array defines of DMAC */
59
60/* Channel array defines of DMACn */
61/*(Sample) value = DMACn[ channel ]->N0SA_n; */
62#define DMACn_COUNT (16)
63#define DMACn_ADDRESS_LIST \
64{ /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \
65 &DMAC0, &DMAC1, &DMAC2, &DMAC3, &DMAC4, &DMAC5, &DMAC6, &DMAC7, \
66 &DMAC8, &DMAC9, &DMAC10, &DMAC11, &DMAC12, &DMAC13, &DMAC14, &DMAC15 \
67} /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */
68#define DMAC0 (*(struct st_dmac_n *)&DMAC.N0SA_0) /* DMAC0 */
69#define DMAC1 (*(struct st_dmac_n *)&DMAC.N0SA_1) /* DMAC1 */
70#define DMAC2 (*(struct st_dmac_n *)&DMAC.N0SA_2) /* DMAC2 */
71#define DMAC3 (*(struct st_dmac_n *)&DMAC.N0SA_3) /* DMAC3 */
72#define DMAC4 (*(struct st_dmac_n *)&DMAC.N0SA_4) /* DMAC4 */
73#define DMAC5 (*(struct st_dmac_n *)&DMAC.N0SA_5) /* DMAC5 */
74#define DMAC6 (*(struct st_dmac_n *)&DMAC.N0SA_6) /* DMAC6 */
75#define DMAC7 (*(struct st_dmac_n *)&DMAC.N0SA_7) /* DMAC7 */
76#define DMAC8 (*(struct st_dmac_n *)&DMAC.N0SA_8) /* DMAC8 */
77#define DMAC9 (*(struct st_dmac_n *)&DMAC.N0SA_9) /* DMAC9 */
78#define DMAC10 (*(struct st_dmac_n *)&DMAC.N0SA_10) /* DMAC10 */
79#define DMAC11 (*(struct st_dmac_n *)&DMAC.N0SA_11) /* DMAC11 */
80#define DMAC12 (*(struct st_dmac_n *)&DMAC.N0SA_12) /* DMAC12 */
81#define DMAC13 (*(struct st_dmac_n *)&DMAC.N0SA_13) /* DMAC13 */
82#define DMAC14 (*(struct st_dmac_n *)&DMAC.N0SA_14) /* DMAC14 */
83#define DMAC15 (*(struct st_dmac_n *)&DMAC.N0SA_15) /* DMAC15 */
84
85
86/* Channel array defines of DMACnn */
87/*(Sample) value = DMACnn[ channel / 8 ]->DCTRL_0_7; */
88#define DMACnn_COUNT (2)
89#define DMACnn_ADDRESS_LIST \
90{ /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \
91 &DMAC07, &DMAC815 \
92} /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */
93#define DMAC07 (*(struct st_dmaccommon_n *)&DMAC.DCTRL_0_7) /* DMAC07 */
94#define DMAC815 (*(struct st_dmaccommon_n *)&DMAC.DCTRL_8_15) /* DMAC815 */
95
96/* End of channel array defines of DMAC */
97
98
99#define DMACN0SA_0 (DMAC.N0SA_0)
100#define DMACN0DA_0 (DMAC.N0DA_0)
101#define DMACN0TB_0 (DMAC.N0TB_0)
102#define DMACN1SA_0 (DMAC.N1SA_0)
103#define DMACN1DA_0 (DMAC.N1DA_0)
104#define DMACN1TB_0 (DMAC.N1TB_0)
105#define DMACCRSA_0 (DMAC.CRSA_0)
106#define DMACCRDA_0 (DMAC.CRDA_0)
107#define DMACCRTB_0 (DMAC.CRTB_0)
108#define DMACCHSTAT_0 (DMAC.CHSTAT_0)
109#define DMACCHCTRL_0 (DMAC.CHCTRL_0)
110#define DMACCHCFG_0 (DMAC.CHCFG_0)
111#define DMACCHITVL_0 (DMAC.CHITVL_0)
112#define DMACCHEXT_0 (DMAC.CHEXT_0)
113#define DMACNXLA_0 (DMAC.NXLA_0)
114#define DMACCRLA_0 (DMAC.CRLA_0)
115#define DMACN0SA_1 (DMAC.N0SA_1)
116#define DMACN0DA_1 (DMAC.N0DA_1)
117#define DMACN0TB_1 (DMAC.N0TB_1)
118#define DMACN1SA_1 (DMAC.N1SA_1)
119#define DMACN1DA_1 (DMAC.N1DA_1)
120#define DMACN1TB_1 (DMAC.N1TB_1)
121#define DMACCRSA_1 (DMAC.CRSA_1)
122#define DMACCRDA_1 (DMAC.CRDA_1)
123#define DMACCRTB_1 (DMAC.CRTB_1)
124#define DMACCHSTAT_1 (DMAC.CHSTAT_1)
125#define DMACCHCTRL_1 (DMAC.CHCTRL_1)
126#define DMACCHCFG_1 (DMAC.CHCFG_1)
127#define DMACCHITVL_1 (DMAC.CHITVL_1)
128#define DMACCHEXT_1 (DMAC.CHEXT_1)
129#define DMACNXLA_1 (DMAC.NXLA_1)
130#define DMACCRLA_1 (DMAC.CRLA_1)
131#define DMACN0SA_2 (DMAC.N0SA_2)
132#define DMACN0DA_2 (DMAC.N0DA_2)
133#define DMACN0TB_2 (DMAC.N0TB_2)
134#define DMACN1SA_2 (DMAC.N1SA_2)
135#define DMACN1DA_2 (DMAC.N1DA_2)
136#define DMACN1TB_2 (DMAC.N1TB_2)
137#define DMACCRSA_2 (DMAC.CRSA_2)
138#define DMACCRDA_2 (DMAC.CRDA_2)
139#define DMACCRTB_2 (DMAC.CRTB_2)
140#define DMACCHSTAT_2 (DMAC.CHSTAT_2)
141#define DMACCHCTRL_2 (DMAC.CHCTRL_2)
142#define DMACCHCFG_2 (DMAC.CHCFG_2)
143#define DMACCHITVL_2 (DMAC.CHITVL_2)
144#define DMACCHEXT_2 (DMAC.CHEXT_2)
145#define DMACNXLA_2 (DMAC.NXLA_2)
146#define DMACCRLA_2 (DMAC.CRLA_2)
147#define DMACN0SA_3 (DMAC.N0SA_3)
148#define DMACN0DA_3 (DMAC.N0DA_3)
149#define DMACN0TB_3 (DMAC.N0TB_3)
150#define DMACN1SA_3 (DMAC.N1SA_3)
151#define DMACN1DA_3 (DMAC.N1DA_3)
152#define DMACN1TB_3 (DMAC.N1TB_3)
153#define DMACCRSA_3 (DMAC.CRSA_3)
154#define DMACCRDA_3 (DMAC.CRDA_3)
155#define DMACCRTB_3 (DMAC.CRTB_3)
156#define DMACCHSTAT_3 (DMAC.CHSTAT_3)
157#define DMACCHCTRL_3 (DMAC.CHCTRL_3)
158#define DMACCHCFG_3 (DMAC.CHCFG_3)
159#define DMACCHITVL_3 (DMAC.CHITVL_3)
160#define DMACCHEXT_3 (DMAC.CHEXT_3)
161#define DMACNXLA_3 (DMAC.NXLA_3)
162#define DMACCRLA_3 (DMAC.CRLA_3)
163#define DMACN0SA_4 (DMAC.N0SA_4)
164#define DMACN0DA_4 (DMAC.N0DA_4)
165#define DMACN0TB_4 (DMAC.N0TB_4)
166#define DMACN1SA_4 (DMAC.N1SA_4)
167#define DMACN1DA_4 (DMAC.N1DA_4)
168#define DMACN1TB_4 (DMAC.N1TB_4)
169#define DMACCRSA_4 (DMAC.CRSA_4)
170#define DMACCRDA_4 (DMAC.CRDA_4)
171#define DMACCRTB_4 (DMAC.CRTB_4)
172#define DMACCHSTAT_4 (DMAC.CHSTAT_4)
173#define DMACCHCTRL_4 (DMAC.CHCTRL_4)
174#define DMACCHCFG_4 (DMAC.CHCFG_4)
175#define DMACCHITVL_4 (DMAC.CHITVL_4)
176#define DMACCHEXT_4 (DMAC.CHEXT_4)
177#define DMACNXLA_4 (DMAC.NXLA_4)
178#define DMACCRLA_4 (DMAC.CRLA_4)
179#define DMACN0SA_5 (DMAC.N0SA_5)
180#define DMACN0DA_5 (DMAC.N0DA_5)
181#define DMACN0TB_5 (DMAC.N0TB_5)
182#define DMACN1SA_5 (DMAC.N1SA_5)
183#define DMACN1DA_5 (DMAC.N1DA_5)
184#define DMACN1TB_5 (DMAC.N1TB_5)
185#define DMACCRSA_5 (DMAC.CRSA_5)
186#define DMACCRDA_5 (DMAC.CRDA_5)
187#define DMACCRTB_5 (DMAC.CRTB_5)
188#define DMACCHSTAT_5 (DMAC.CHSTAT_5)
189#define DMACCHCTRL_5 (DMAC.CHCTRL_5)
190#define DMACCHCFG_5 (DMAC.CHCFG_5)
191#define DMACCHITVL_5 (DMAC.CHITVL_5)
192#define DMACCHEXT_5 (DMAC.CHEXT_5)
193#define DMACNXLA_5 (DMAC.NXLA_5)
194#define DMACCRLA_5 (DMAC.CRLA_5)
195#define DMACN0SA_6 (DMAC.N0SA_6)
196#define DMACN0DA_6 (DMAC.N0DA_6)
197#define DMACN0TB_6 (DMAC.N0TB_6)
198#define DMACN1SA_6 (DMAC.N1SA_6)
199#define DMACN1DA_6 (DMAC.N1DA_6)
200#define DMACN1TB_6 (DMAC.N1TB_6)
201#define DMACCRSA_6 (DMAC.CRSA_6)
202#define DMACCRDA_6 (DMAC.CRDA_6)
203#define DMACCRTB_6 (DMAC.CRTB_6)
204#define DMACCHSTAT_6 (DMAC.CHSTAT_6)
205#define DMACCHCTRL_6 (DMAC.CHCTRL_6)
206#define DMACCHCFG_6 (DMAC.CHCFG_6)
207#define DMACCHITVL_6 (DMAC.CHITVL_6)
208#define DMACCHEXT_6 (DMAC.CHEXT_6)
209#define DMACNXLA_6 (DMAC.NXLA_6)
210#define DMACCRLA_6 (DMAC.CRLA_6)
211#define DMACN0SA_7 (DMAC.N0SA_7)
212#define DMACN0DA_7 (DMAC.N0DA_7)
213#define DMACN0TB_7 (DMAC.N0TB_7)
214#define DMACN1SA_7 (DMAC.N1SA_7)
215#define DMACN1DA_7 (DMAC.N1DA_7)
216#define DMACN1TB_7 (DMAC.N1TB_7)
217#define DMACCRSA_7 (DMAC.CRSA_7)
218#define DMACCRDA_7 (DMAC.CRDA_7)
219#define DMACCRTB_7 (DMAC.CRTB_7)
220#define DMACCHSTAT_7 (DMAC.CHSTAT_7)
221#define DMACCHCTRL_7 (DMAC.CHCTRL_7)
222#define DMACCHCFG_7 (DMAC.CHCFG_7)
223#define DMACCHITVL_7 (DMAC.CHITVL_7)
224#define DMACCHEXT_7 (DMAC.CHEXT_7)
225#define DMACNXLA_7 (DMAC.NXLA_7)
226#define DMACCRLA_7 (DMAC.CRLA_7)
227#define DMACDCTRL_0_7 (DMAC.DCTRL_0_7)
228#define DMACDSTAT_EN_0_7 (DMAC.DSTAT_EN_0_7)
229#define DMACDSTAT_ER_0_7 (DMAC.DSTAT_ER_0_7)
230#define DMACDSTAT_END_0_7 (DMAC.DSTAT_END_0_7)
231#define DMACDSTAT_TC_0_7 (DMAC.DSTAT_TC_0_7)
232#define DMACDSTAT_SUS_0_7 (DMAC.DSTAT_SUS_0_7)
233#define DMACN0SA_8 (DMAC.N0SA_8)
234#define DMACN0DA_8 (DMAC.N0DA_8)
235#define DMACN0TB_8 (DMAC.N0TB_8)
236#define DMACN1SA_8 (DMAC.N1SA_8)
237#define DMACN1DA_8 (DMAC.N1DA_8)
238#define DMACN1TB_8 (DMAC.N1TB_8)
239#define DMACCRSA_8 (DMAC.CRSA_8)
240#define DMACCRDA_8 (DMAC.CRDA_8)
241#define DMACCRTB_8 (DMAC.CRTB_8)
242#define DMACCHSTAT_8 (DMAC.CHSTAT_8)
243#define DMACCHCTRL_8 (DMAC.CHCTRL_8)
244#define DMACCHCFG_8 (DMAC.CHCFG_8)
245#define DMACCHITVL_8 (DMAC.CHITVL_8)
246#define DMACCHEXT_8 (DMAC.CHEXT_8)
247#define DMACNXLA_8 (DMAC.NXLA_8)
248#define DMACCRLA_8 (DMAC.CRLA_8)
249#define DMACN0SA_9 (DMAC.N0SA_9)
250#define DMACN0DA_9 (DMAC.N0DA_9)
251#define DMACN0TB_9 (DMAC.N0TB_9)
252#define DMACN1SA_9 (DMAC.N1SA_9)
253#define DMACN1DA_9 (DMAC.N1DA_9)
254#define DMACN1TB_9 (DMAC.N1TB_9)
255#define DMACCRSA_9 (DMAC.CRSA_9)
256#define DMACCRDA_9 (DMAC.CRDA_9)
257#define DMACCRTB_9 (DMAC.CRTB_9)
258#define DMACCHSTAT_9 (DMAC.CHSTAT_9)
259#define DMACCHCTRL_9 (DMAC.CHCTRL_9)
260#define DMACCHCFG_9 (DMAC.CHCFG_9)
261#define DMACCHITVL_9 (DMAC.CHITVL_9)
262#define DMACCHEXT_9 (DMAC.CHEXT_9)
263#define DMACNXLA_9 (DMAC.NXLA_9)
264#define DMACCRLA_9 (DMAC.CRLA_9)
265#define DMACN0SA_10 (DMAC.N0SA_10)
266#define DMACN0DA_10 (DMAC.N0DA_10)
267#define DMACN0TB_10 (DMAC.N0TB_10)
268#define DMACN1SA_10 (DMAC.N1SA_10)
269#define DMACN1DA_10 (DMAC.N1DA_10)
270#define DMACN1TB_10 (DMAC.N1TB_10)
271#define DMACCRSA_10 (DMAC.CRSA_10)
272#define DMACCRDA_10 (DMAC.CRDA_10)
273#define DMACCRTB_10 (DMAC.CRTB_10)
274#define DMACCHSTAT_10 (DMAC.CHSTAT_10)
275#define DMACCHCTRL_10 (DMAC.CHCTRL_10)
276#define DMACCHCFG_10 (DMAC.CHCFG_10)
277#define DMACCHITVL_10 (DMAC.CHITVL_10)
278#define DMACCHEXT_10 (DMAC.CHEXT_10)
279#define DMACNXLA_10 (DMAC.NXLA_10)
280#define DMACCRLA_10 (DMAC.CRLA_10)
281#define DMACN0SA_11 (DMAC.N0SA_11)
282#define DMACN0DA_11 (DMAC.N0DA_11)
283#define DMACN0TB_11 (DMAC.N0TB_11)
284#define DMACN1SA_11 (DMAC.N1SA_11)
285#define DMACN1DA_11 (DMAC.N1DA_11)
286#define DMACN1TB_11 (DMAC.N1TB_11)
287#define DMACCRSA_11 (DMAC.CRSA_11)
288#define DMACCRDA_11 (DMAC.CRDA_11)
289#define DMACCRTB_11 (DMAC.CRTB_11)
290#define DMACCHSTAT_11 (DMAC.CHSTAT_11)
291#define DMACCHCTRL_11 (DMAC.CHCTRL_11)
292#define DMACCHCFG_11 (DMAC.CHCFG_11)
293#define DMACCHITVL_11 (DMAC.CHITVL_11)
294#define DMACCHEXT_11 (DMAC.CHEXT_11)
295#define DMACNXLA_11 (DMAC.NXLA_11)
296#define DMACCRLA_11 (DMAC.CRLA_11)
297#define DMACN0SA_12 (DMAC.N0SA_12)
298#define DMACN0DA_12 (DMAC.N0DA_12)
299#define DMACN0TB_12 (DMAC.N0TB_12)
300#define DMACN1SA_12 (DMAC.N1SA_12)
301#define DMACN1DA_12 (DMAC.N1DA_12)
302#define DMACN1TB_12 (DMAC.N1TB_12)
303#define DMACCRSA_12 (DMAC.CRSA_12)
304#define DMACCRDA_12 (DMAC.CRDA_12)
305#define DMACCRTB_12 (DMAC.CRTB_12)
306#define DMACCHSTAT_12 (DMAC.CHSTAT_12)
307#define DMACCHCTRL_12 (DMAC.CHCTRL_12)
308#define DMACCHCFG_12 (DMAC.CHCFG_12)
309#define DMACCHITVL_12 (DMAC.CHITVL_12)
310#define DMACCHEXT_12 (DMAC.CHEXT_12)
311#define DMACNXLA_12 (DMAC.NXLA_12)
312#define DMACCRLA_12 (DMAC.CRLA_12)
313#define DMACN0SA_13 (DMAC.N0SA_13)
314#define DMACN0DA_13 (DMAC.N0DA_13)
315#define DMACN0TB_13 (DMAC.N0TB_13)
316#define DMACN1SA_13 (DMAC.N1SA_13)
317#define DMACN1DA_13 (DMAC.N1DA_13)
318#define DMACN1TB_13 (DMAC.N1TB_13)
319#define DMACCRSA_13 (DMAC.CRSA_13)
320#define DMACCRDA_13 (DMAC.CRDA_13)
321#define DMACCRTB_13 (DMAC.CRTB_13)
322#define DMACCHSTAT_13 (DMAC.CHSTAT_13)
323#define DMACCHCTRL_13 (DMAC.CHCTRL_13)
324#define DMACCHCFG_13 (DMAC.CHCFG_13)
325#define DMACCHITVL_13 (DMAC.CHITVL_13)
326#define DMACCHEXT_13 (DMAC.CHEXT_13)
327#define DMACNXLA_13 (DMAC.NXLA_13)
328#define DMACCRLA_13 (DMAC.CRLA_13)
329#define DMACN0SA_14 (DMAC.N0SA_14)
330#define DMACN0DA_14 (DMAC.N0DA_14)
331#define DMACN0TB_14 (DMAC.N0TB_14)
332#define DMACN1SA_14 (DMAC.N1SA_14)
333#define DMACN1DA_14 (DMAC.N1DA_14)
334#define DMACN1TB_14 (DMAC.N1TB_14)
335#define DMACCRSA_14 (DMAC.CRSA_14)
336#define DMACCRDA_14 (DMAC.CRDA_14)
337#define DMACCRTB_14 (DMAC.CRTB_14)
338#define DMACCHSTAT_14 (DMAC.CHSTAT_14)
339#define DMACCHCTRL_14 (DMAC.CHCTRL_14)
340#define DMACCHCFG_14 (DMAC.CHCFG_14)
341#define DMACCHITVL_14 (DMAC.CHITVL_14)
342#define DMACCHEXT_14 (DMAC.CHEXT_14)
343#define DMACNXLA_14 (DMAC.NXLA_14)
344#define DMACCRLA_14 (DMAC.CRLA_14)
345#define DMACN0SA_15 (DMAC.N0SA_15)
346#define DMACN0DA_15 (DMAC.N0DA_15)
347#define DMACN0TB_15 (DMAC.N0TB_15)
348#define DMACN1SA_15 (DMAC.N1SA_15)
349#define DMACN1DA_15 (DMAC.N1DA_15)
350#define DMACN1TB_15 (DMAC.N1TB_15)
351#define DMACCRSA_15 (DMAC.CRSA_15)
352#define DMACCRDA_15 (DMAC.CRDA_15)
353#define DMACCRTB_15 (DMAC.CRTB_15)
354#define DMACCHSTAT_15 (DMAC.CHSTAT_15)
355#define DMACCHCTRL_15 (DMAC.CHCTRL_15)
356#define DMACCHCFG_15 (DMAC.CHCFG_15)
357#define DMACCHITVL_15 (DMAC.CHITVL_15)
358#define DMACCHEXT_15 (DMAC.CHEXT_15)
359#define DMACNXLA_15 (DMAC.NXLA_15)
360#define DMACCRLA_15 (DMAC.CRLA_15)
361#define DMACDCTRL_8_15 (DMAC.DCTRL_8_15)
362#define DMACDSTAT_EN_8_15 (DMAC.DSTAT_EN_8_15)
363#define DMACDSTAT_ER_8_15 (DMAC.DSTAT_ER_8_15)
364#define DMACDSTAT_END_8_15 (DMAC.DSTAT_END_8_15)
365#define DMACDSTAT_TC_8_15 (DMAC.DSTAT_TC_8_15)
366#define DMACDSTAT_SUS_8_15 (DMAC.DSTAT_SUS_8_15)
367#define DMACDMARS0 (DMAC.DMARS0)
368#define DMACDMARS1 (DMAC.DMARS1)
369#define DMACDMARS2 (DMAC.DMARS2)
370#define DMACDMARS3 (DMAC.DMARS3)
371#define DMACDMARS4 (DMAC.DMARS4)
372#define DMACDMARS5 (DMAC.DMARS5)
373#define DMACDMARS6 (DMAC.DMARS6)
374#define DMACDMARS7 (DMAC.DMARS7)
375
376
377typedef struct st_dmars_mm
378{
379
380 volatile uint32_t DMARS; /* DMARS */
381} r_io_dmars_mm_t;
382
383
384typedef struct st_dmac
385{
386 /* DMAC */
387
[352]388/* start of struct st_dmac_n */
389 volatile uint32_t N0SA_0; /* N0SA_0 */
390 volatile uint32_t N0DA_0; /* N0DA_0 */
391 volatile uint32_t N0TB_0; /* N0TB_0 */
392 volatile uint32_t N1SA_0; /* N1SA_0 */
393 volatile uint32_t N1DA_0; /* N1DA_0 */
394 volatile uint32_t N1TB_0; /* N1TB_0 */
395 volatile uint32_t CRSA_0; /* CRSA_0 */
396 volatile uint32_t CRDA_0; /* CRDA_0 */
397 volatile uint32_t CRTB_0; /* CRTB_0 */
398 volatile uint32_t CHSTAT_0; /* CHSTAT_0 */
399 volatile uint32_t CHCTRL_0; /* CHCTRL_0 */
400 volatile uint32_t CHCFG_0; /* CHCFG_0 */
401 volatile uint32_t CHITVL_0; /* CHITVL_0 */
402 volatile uint32_t CHEXT_0; /* CHEXT_0 */
403 volatile uint32_t NXLA_0; /* NXLA_0 */
404 volatile uint32_t CRLA_0; /* CRLA_0 */
[374]405
[352]406/* end of struct st_dmac_n */
[374]407
[352]408/* start of struct st_dmac_n */
409 volatile uint32_t N0SA_1; /* N0SA_1 */
410 volatile uint32_t N0DA_1; /* N0DA_1 */
411 volatile uint32_t N0TB_1; /* N0TB_1 */
412 volatile uint32_t N1SA_1; /* N1SA_1 */
413 volatile uint32_t N1DA_1; /* N1DA_1 */
414 volatile uint32_t N1TB_1; /* N1TB_1 */
415 volatile uint32_t CRSA_1; /* CRSA_1 */
416 volatile uint32_t CRDA_1; /* CRDA_1 */
417 volatile uint32_t CRTB_1; /* CRTB_1 */
418 volatile uint32_t CHSTAT_1; /* CHSTAT_1 */
419 volatile uint32_t CHCTRL_1; /* CHCTRL_1 */
420 volatile uint32_t CHCFG_1; /* CHCFG_1 */
421 volatile uint32_t CHITVL_1; /* CHITVL_1 */
422 volatile uint32_t CHEXT_1; /* CHEXT_1 */
423 volatile uint32_t NXLA_1; /* NXLA_1 */
424 volatile uint32_t CRLA_1; /* CRLA_1 */
[374]425
[352]426/* end of struct st_dmac_n */
[374]427
[352]428/* start of struct st_dmac_n */
429 volatile uint32_t N0SA_2; /* N0SA_2 */
430 volatile uint32_t N0DA_2; /* N0DA_2 */
431 volatile uint32_t N0TB_2; /* N0TB_2 */
432 volatile uint32_t N1SA_2; /* N1SA_2 */
433 volatile uint32_t N1DA_2; /* N1DA_2 */
434 volatile uint32_t N1TB_2; /* N1TB_2 */
435 volatile uint32_t CRSA_2; /* CRSA_2 */
436 volatile uint32_t CRDA_2; /* CRDA_2 */
437 volatile uint32_t CRTB_2; /* CRTB_2 */
438 volatile uint32_t CHSTAT_2; /* CHSTAT_2 */
439 volatile uint32_t CHCTRL_2; /* CHCTRL_2 */
440 volatile uint32_t CHCFG_2; /* CHCFG_2 */
441 volatile uint32_t CHITVL_2; /* CHITVL_2 */
442 volatile uint32_t CHEXT_2; /* CHEXT_2 */
443 volatile uint32_t NXLA_2; /* NXLA_2 */
444 volatile uint32_t CRLA_2; /* CRLA_2 */
[374]445
[352]446/* end of struct st_dmac_n */
[374]447
[352]448/* start of struct st_dmac_n */
449 volatile uint32_t N0SA_3; /* N0SA_3 */
450 volatile uint32_t N0DA_3; /* N0DA_3 */
451 volatile uint32_t N0TB_3; /* N0TB_3 */
452 volatile uint32_t N1SA_3; /* N1SA_3 */
453 volatile uint32_t N1DA_3; /* N1DA_3 */
454 volatile uint32_t N1TB_3; /* N1TB_3 */
455 volatile uint32_t CRSA_3; /* CRSA_3 */
456 volatile uint32_t CRDA_3; /* CRDA_3 */
457 volatile uint32_t CRTB_3; /* CRTB_3 */
458 volatile uint32_t CHSTAT_3; /* CHSTAT_3 */
459 volatile uint32_t CHCTRL_3; /* CHCTRL_3 */
460 volatile uint32_t CHCFG_3; /* CHCFG_3 */
461 volatile uint32_t CHITVL_3; /* CHITVL_3 */
462 volatile uint32_t CHEXT_3; /* CHEXT_3 */
463 volatile uint32_t NXLA_3; /* NXLA_3 */
464 volatile uint32_t CRLA_3; /* CRLA_3 */
[374]465
[352]466/* end of struct st_dmac_n */
[374]467
[352]468/* start of struct st_dmac_n */
469 volatile uint32_t N0SA_4; /* N0SA_4 */
470 volatile uint32_t N0DA_4; /* N0DA_4 */
471 volatile uint32_t N0TB_4; /* N0TB_4 */
472 volatile uint32_t N1SA_4; /* N1SA_4 */
473 volatile uint32_t N1DA_4; /* N1DA_4 */
474 volatile uint32_t N1TB_4; /* N1TB_4 */
475 volatile uint32_t CRSA_4; /* CRSA_4 */
476 volatile uint32_t CRDA_4; /* CRDA_4 */
477 volatile uint32_t CRTB_4; /* CRTB_4 */
478 volatile uint32_t CHSTAT_4; /* CHSTAT_4 */
479 volatile uint32_t CHCTRL_4; /* CHCTRL_4 */
480 volatile uint32_t CHCFG_4; /* CHCFG_4 */
481 volatile uint32_t CHITVL_4; /* CHITVL_4 */
482 volatile uint32_t CHEXT_4; /* CHEXT_4 */
483 volatile uint32_t NXLA_4; /* NXLA_4 */
484 volatile uint32_t CRLA_4; /* CRLA_4 */
[374]485
[352]486/* end of struct st_dmac_n */
[374]487
[352]488/* start of struct st_dmac_n */
489 volatile uint32_t N0SA_5; /* N0SA_5 */
490 volatile uint32_t N0DA_5; /* N0DA_5 */
491 volatile uint32_t N0TB_5; /* N0TB_5 */
492 volatile uint32_t N1SA_5; /* N1SA_5 */
493 volatile uint32_t N1DA_5; /* N1DA_5 */
494 volatile uint32_t N1TB_5; /* N1TB_5 */
495 volatile uint32_t CRSA_5; /* CRSA_5 */
496 volatile uint32_t CRDA_5; /* CRDA_5 */
497 volatile uint32_t CRTB_5; /* CRTB_5 */
498 volatile uint32_t CHSTAT_5; /* CHSTAT_5 */
499 volatile uint32_t CHCTRL_5; /* CHCTRL_5 */
500 volatile uint32_t CHCFG_5; /* CHCFG_5 */
501 volatile uint32_t CHITVL_5; /* CHITVL_5 */
502 volatile uint32_t CHEXT_5; /* CHEXT_5 */
503 volatile uint32_t NXLA_5; /* NXLA_5 */
504 volatile uint32_t CRLA_5; /* CRLA_5 */
[374]505
[352]506/* end of struct st_dmac_n */
[374]507
[352]508/* start of struct st_dmac_n */
509 volatile uint32_t N0SA_6; /* N0SA_6 */
510 volatile uint32_t N0DA_6; /* N0DA_6 */
511 volatile uint32_t N0TB_6; /* N0TB_6 */
512 volatile uint32_t N1SA_6; /* N1SA_6 */
513 volatile uint32_t N1DA_6; /* N1DA_6 */
514 volatile uint32_t N1TB_6; /* N1TB_6 */
515 volatile uint32_t CRSA_6; /* CRSA_6 */
516 volatile uint32_t CRDA_6; /* CRDA_6 */
517 volatile uint32_t CRTB_6; /* CRTB_6 */
518 volatile uint32_t CHSTAT_6; /* CHSTAT_6 */
519 volatile uint32_t CHCTRL_6; /* CHCTRL_6 */
520 volatile uint32_t CHCFG_6; /* CHCFG_6 */
521 volatile uint32_t CHITVL_6; /* CHITVL_6 */
522 volatile uint32_t CHEXT_6; /* CHEXT_6 */
523 volatile uint32_t NXLA_6; /* NXLA_6 */
524 volatile uint32_t CRLA_6; /* CRLA_6 */
[374]525
[352]526/* end of struct st_dmac_n */
[374]527
[352]528/* start of struct st_dmac_n */
529 volatile uint32_t N0SA_7; /* N0SA_7 */
530 volatile uint32_t N0DA_7; /* N0DA_7 */
531 volatile uint32_t N0TB_7; /* N0TB_7 */
532 volatile uint32_t N1SA_7; /* N1SA_7 */
533 volatile uint32_t N1DA_7; /* N1DA_7 */
534 volatile uint32_t N1TB_7; /* N1TB_7 */
535 volatile uint32_t CRSA_7; /* CRSA_7 */
536 volatile uint32_t CRDA_7; /* CRDA_7 */
537 volatile uint32_t CRTB_7; /* CRTB_7 */
538 volatile uint32_t CHSTAT_7; /* CHSTAT_7 */
539 volatile uint32_t CHCTRL_7; /* CHCTRL_7 */
540 volatile uint32_t CHCFG_7; /* CHCFG_7 */
541 volatile uint32_t CHITVL_7; /* CHITVL_7 */
542 volatile uint32_t CHEXT_7; /* CHEXT_7 */
543 volatile uint32_t NXLA_7; /* NXLA_7 */
544 volatile uint32_t CRLA_7; /* CRLA_7 */
[374]545
[352]546/* end of struct st_dmac_n */
547 volatile uint8_t dummy187[256]; /* */
[374]548
[352]549/* start of struct st_dmaccommon_n */
550 volatile uint32_t DCTRL_0_7; /* DCTRL_0_7 */
551 volatile uint8_t dummy188[12]; /* */
552 volatile uint32_t DSTAT_EN_0_7; /* DSTAT_EN_0_7 */
553 volatile uint32_t DSTAT_ER_0_7; /* DSTAT_ER_0_7 */
554 volatile uint32_t DSTAT_END_0_7; /* DSTAT_END_0_7 */
555 volatile uint32_t DSTAT_TC_0_7; /* DSTAT_TC_0_7 */
556 volatile uint32_t DSTAT_SUS_0_7; /* DSTAT_SUS_0_7 */
[374]557
[352]558/* end of struct st_dmaccommon_n */
559 volatile uint8_t dummy189[220]; /* */
[374]560
[352]561/* start of struct st_dmac_n */
562 volatile uint32_t N0SA_8; /* N0SA_8 */
563 volatile uint32_t N0DA_8; /* N0DA_8 */
564 volatile uint32_t N0TB_8; /* N0TB_8 */
565 volatile uint32_t N1SA_8; /* N1SA_8 */
566 volatile uint32_t N1DA_8; /* N1DA_8 */
567 volatile uint32_t N1TB_8; /* N1TB_8 */
568 volatile uint32_t CRSA_8; /* CRSA_8 */
569 volatile uint32_t CRDA_8; /* CRDA_8 */
570 volatile uint32_t CRTB_8; /* CRTB_8 */
571 volatile uint32_t CHSTAT_8; /* CHSTAT_8 */
572 volatile uint32_t CHCTRL_8; /* CHCTRL_8 */
573 volatile uint32_t CHCFG_8; /* CHCFG_8 */
574 volatile uint32_t CHITVL_8; /* CHITVL_8 */
575 volatile uint32_t CHEXT_8; /* CHEXT_8 */
576 volatile uint32_t NXLA_8; /* NXLA_8 */
577 volatile uint32_t CRLA_8; /* CRLA_8 */
[374]578
[352]579/* end of struct st_dmac_n */
[374]580
[352]581/* start of struct st_dmac_n */
582 volatile uint32_t N0SA_9; /* N0SA_9 */
583 volatile uint32_t N0DA_9; /* N0DA_9 */
584 volatile uint32_t N0TB_9; /* N0TB_9 */
585 volatile uint32_t N1SA_9; /* N1SA_9 */
586 volatile uint32_t N1DA_9; /* N1DA_9 */
587 volatile uint32_t N1TB_9; /* N1TB_9 */
588 volatile uint32_t CRSA_9; /* CRSA_9 */
589 volatile uint32_t CRDA_9; /* CRDA_9 */
590 volatile uint32_t CRTB_9; /* CRTB_9 */
591 volatile uint32_t CHSTAT_9; /* CHSTAT_9 */
592 volatile uint32_t CHCTRL_9; /* CHCTRL_9 */
593 volatile uint32_t CHCFG_9; /* CHCFG_9 */
594 volatile uint32_t CHITVL_9; /* CHITVL_9 */
595 volatile uint32_t CHEXT_9; /* CHEXT_9 */
596 volatile uint32_t NXLA_9; /* NXLA_9 */
597 volatile uint32_t CRLA_9; /* CRLA_9 */
[374]598
[352]599/* end of struct st_dmac_n */
[374]600
[352]601/* start of struct st_dmac_n */
602 volatile uint32_t N0SA_10; /* N0SA_10 */
603 volatile uint32_t N0DA_10; /* N0DA_10 */
604 volatile uint32_t N0TB_10; /* N0TB_10 */
605 volatile uint32_t N1SA_10; /* N1SA_10 */
606 volatile uint32_t N1DA_10; /* N1DA_10 */
607 volatile uint32_t N1TB_10; /* N1TB_10 */
608 volatile uint32_t CRSA_10; /* CRSA_10 */
609 volatile uint32_t CRDA_10; /* CRDA_10 */
610 volatile uint32_t CRTB_10; /* CRTB_10 */
611 volatile uint32_t CHSTAT_10; /* CHSTAT_10 */
612 volatile uint32_t CHCTRL_10; /* CHCTRL_10 */
613 volatile uint32_t CHCFG_10; /* CHCFG_10 */
614 volatile uint32_t CHITVL_10; /* CHITVL_10 */
615 volatile uint32_t CHEXT_10; /* CHEXT_10 */
616 volatile uint32_t NXLA_10; /* NXLA_10 */
617 volatile uint32_t CRLA_10; /* CRLA_10 */
[374]618
[352]619/* end of struct st_dmac_n */
[374]620
[352]621/* start of struct st_dmac_n */
622 volatile uint32_t N0SA_11; /* N0SA_11 */
623 volatile uint32_t N0DA_11; /* N0DA_11 */
624 volatile uint32_t N0TB_11; /* N0TB_11 */
625 volatile uint32_t N1SA_11; /* N1SA_11 */
626 volatile uint32_t N1DA_11; /* N1DA_11 */
627 volatile uint32_t N1TB_11; /* N1TB_11 */
628 volatile uint32_t CRSA_11; /* CRSA_11 */
629 volatile uint32_t CRDA_11; /* CRDA_11 */
630 volatile uint32_t CRTB_11; /* CRTB_11 */
631 volatile uint32_t CHSTAT_11; /* CHSTAT_11 */
632 volatile uint32_t CHCTRL_11; /* CHCTRL_11 */
633 volatile uint32_t CHCFG_11; /* CHCFG_11 */
634 volatile uint32_t CHITVL_11; /* CHITVL_11 */
635 volatile uint32_t CHEXT_11; /* CHEXT_11 */
636 volatile uint32_t NXLA_11; /* NXLA_11 */
637 volatile uint32_t CRLA_11; /* CRLA_11 */
[374]638
[352]639/* end of struct st_dmac_n */
[374]640
[352]641/* start of struct st_dmac_n */
642 volatile uint32_t N0SA_12; /* N0SA_12 */
643 volatile uint32_t N0DA_12; /* N0DA_12 */
644 volatile uint32_t N0TB_12; /* N0TB_12 */
645 volatile uint32_t N1SA_12; /* N1SA_12 */
646 volatile uint32_t N1DA_12; /* N1DA_12 */
647 volatile uint32_t N1TB_12; /* N1TB_12 */
648 volatile uint32_t CRSA_12; /* CRSA_12 */
649 volatile uint32_t CRDA_12; /* CRDA_12 */
650 volatile uint32_t CRTB_12; /* CRTB_12 */
651 volatile uint32_t CHSTAT_12; /* CHSTAT_12 */
652 volatile uint32_t CHCTRL_12; /* CHCTRL_12 */
653 volatile uint32_t CHCFG_12; /* CHCFG_12 */
654 volatile uint32_t CHITVL_12; /* CHITVL_12 */
655 volatile uint32_t CHEXT_12; /* CHEXT_12 */
656 volatile uint32_t NXLA_12; /* NXLA_12 */
657 volatile uint32_t CRLA_12; /* CRLA_12 */
[374]658
[352]659/* end of struct st_dmac_n */
[374]660
[352]661/* start of struct st_dmac_n */
662 volatile uint32_t N0SA_13; /* N0SA_13 */
663 volatile uint32_t N0DA_13; /* N0DA_13 */
664 volatile uint32_t N0TB_13; /* N0TB_13 */
665 volatile uint32_t N1SA_13; /* N1SA_13 */
666 volatile uint32_t N1DA_13; /* N1DA_13 */
667 volatile uint32_t N1TB_13; /* N1TB_13 */
668 volatile uint32_t CRSA_13; /* CRSA_13 */
669 volatile uint32_t CRDA_13; /* CRDA_13 */
670 volatile uint32_t CRTB_13; /* CRTB_13 */
671 volatile uint32_t CHSTAT_13; /* CHSTAT_13 */
672 volatile uint32_t CHCTRL_13; /* CHCTRL_13 */
673 volatile uint32_t CHCFG_13; /* CHCFG_13 */
674 volatile uint32_t CHITVL_13; /* CHITVL_13 */
675 volatile uint32_t CHEXT_13; /* CHEXT_13 */
676 volatile uint32_t NXLA_13; /* NXLA_13 */
677 volatile uint32_t CRLA_13; /* CRLA_13 */
[374]678
[352]679/* end of struct st_dmac_n */
[374]680
[352]681/* start of struct st_dmac_n */
682 volatile uint32_t N0SA_14; /* N0SA_14 */
683 volatile uint32_t N0DA_14; /* N0DA_14 */
684 volatile uint32_t N0TB_14; /* N0TB_14 */
685 volatile uint32_t N1SA_14; /* N1SA_14 */
686 volatile uint32_t N1DA_14; /* N1DA_14 */
687 volatile uint32_t N1TB_14; /* N1TB_14 */
688 volatile uint32_t CRSA_14; /* CRSA_14 */
689 volatile uint32_t CRDA_14; /* CRDA_14 */
690 volatile uint32_t CRTB_14; /* CRTB_14 */
691 volatile uint32_t CHSTAT_14; /* CHSTAT_14 */
692 volatile uint32_t CHCTRL_14; /* CHCTRL_14 */
693 volatile uint32_t CHCFG_14; /* CHCFG_14 */
694 volatile uint32_t CHITVL_14; /* CHITVL_14 */
695 volatile uint32_t CHEXT_14; /* CHEXT_14 */
696 volatile uint32_t NXLA_14; /* NXLA_14 */
697 volatile uint32_t CRLA_14; /* CRLA_14 */
[374]698
[352]699/* end of struct st_dmac_n */
[374]700
[352]701/* start of struct st_dmac_n */
702 volatile uint32_t N0SA_15; /* N0SA_15 */
703 volatile uint32_t N0DA_15; /* N0DA_15 */
704 volatile uint32_t N0TB_15; /* N0TB_15 */
705 volatile uint32_t N1SA_15; /* N1SA_15 */
706 volatile uint32_t N1DA_15; /* N1DA_15 */
707 volatile uint32_t N1TB_15; /* N1TB_15 */
708 volatile uint32_t CRSA_15; /* CRSA_15 */
709 volatile uint32_t CRDA_15; /* CRDA_15 */
710 volatile uint32_t CRTB_15; /* CRTB_15 */
711 volatile uint32_t CHSTAT_15; /* CHSTAT_15 */
712 volatile uint32_t CHCTRL_15; /* CHCTRL_15 */
713 volatile uint32_t CHCFG_15; /* CHCFG_15 */
714 volatile uint32_t CHITVL_15; /* CHITVL_15 */
715 volatile uint32_t CHEXT_15; /* CHEXT_15 */
716 volatile uint32_t NXLA_15; /* NXLA_15 */
717 volatile uint32_t CRLA_15; /* CRLA_15 */
[374]718
[352]719/* end of struct st_dmac_n */
720 volatile uint8_t dummy190[256]; /* */
[374]721
[352]722/* start of struct st_dmaccommon_n */
723 volatile uint32_t DCTRL_8_15; /* DCTRL_8_15 */
724 volatile uint8_t dummy191[12]; /* */
725 volatile uint32_t DSTAT_EN_8_15; /* DSTAT_EN_8_15 */
726 volatile uint32_t DSTAT_ER_8_15; /* DSTAT_ER_8_15 */
727 volatile uint32_t DSTAT_END_8_15; /* DSTAT_END_8_15 */
728 volatile uint32_t DSTAT_TC_8_15; /* DSTAT_TC_8_15 */
729 volatile uint32_t DSTAT_SUS_8_15; /* DSTAT_SUS_8_15 */
[374]730
[352]731/* end of struct st_dmaccommon_n */
732 volatile uint8_t dummy192[350095580]; /* */
733 volatile uint32_t DMARS0; /* DMARS0 */
734 volatile uint32_t DMARS1; /* DMARS1 */
735 volatile uint32_t DMARS2; /* DMARS2 */
736 volatile uint32_t DMARS3; /* DMARS3 */
737 volatile uint32_t DMARS4; /* DMARS4 */
738 volatile uint32_t DMARS5; /* DMARS5 */
739 volatile uint32_t DMARS6; /* DMARS6 */
740 volatile uint32_t DMARS7; /* DMARS7 */
[374]741} r_io_dmac_t;
[352]742
743
[374]744typedef struct st_dmaccommon_n
[352]745{
[374]746
[352]747 volatile uint32_t DCTRL_0_7; /* DCTRL_0_7 */
748 volatile uint8_t dummy1[12]; /* */
749 volatile uint32_t DSTAT_EN_0_7; /* DSTAT_EN_0_7 */
750 volatile uint32_t DSTAT_ER_0_7; /* DSTAT_ER_0_7 */
751 volatile uint32_t DSTAT_END_0_7; /* DSTAT_END_0_7 */
752 volatile uint32_t DSTAT_TC_0_7; /* DSTAT_TC_0_7 */
753 volatile uint32_t DSTAT_SUS_0_7; /* DSTAT_SUS_0_7 */
[374]754} r_io_dmaccommon_n_t;
[352]755
756
[374]757typedef struct st_dmac_n
[352]758{
[374]759
[352]760 volatile uint32_t N0SA_n; /* N0SA_n */
761 volatile uint32_t N0DA_n; /* N0DA_n */
762 volatile uint32_t N0TB_n; /* N0TB_n */
763 volatile uint32_t N1SA_n; /* N1SA_n */
764 volatile uint32_t N1DA_n; /* N1DA_n */
765 volatile uint32_t N1TB_n; /* N1TB_n */
766 volatile uint32_t CRSA_n; /* CRSA_n */
767 volatile uint32_t CRDA_n; /* CRDA_n */
768 volatile uint32_t CRTB_n; /* CRTB_n */
769 volatile uint32_t CHSTAT_n; /* CHSTAT_n */
770 volatile uint32_t CHCTRL_n; /* CHCTRL_n */
771 volatile uint32_t CHCFG_n; /* CHCFG_n */
772 volatile uint32_t CHITVL_n; /* CHITVL_n */
773 volatile uint32_t CHEXT_n; /* CHEXT_n */
774 volatile uint32_t NXLA_n; /* NXLA_n */
775 volatile uint32_t CRLA_n; /* CRLA_n */
[374]776} r_io_dmac_n_t;
[352]777
778
[374]779/* Channel array defines of DMAC (2)*/
780#ifdef DECLARE_DMACmm_CHANNELS
781volatile struct st_dmars_mm* DMACmm[ DMACmm_COUNT ] =
782 /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */
783 DMACmm_ADDRESS_LIST;
784 /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */
785#endif /* DECLARE_DMACmm_CHANNELS */
[352]786
[374]787#ifdef DECLARE_DMACn_CHANNELS
788volatile struct st_dmac_n* DMACn[ DMACn_COUNT ] =
789 /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */
790 DMACn_ADDRESS_LIST;
791 /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */
792#endif /* DECLARE_DMACn_CHANNELS */
[352]793
[374]794#ifdef DECLARE_DMACnn_CHANNELS
795volatile struct st_dmaccommon_n* DMACnn[ DMACnn_COUNT ] =
796 /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */
797 DMACnn_ADDRESS_LIST;
798 /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */
799#endif /* DECLARE_DMACnn_CHANNELS */
800/* End of channel array defines of DMAC (2)*/
[352]801
802
803/* <-SEC M1.10.1 */
[374]804/* <-MISRA 18.4 */ /* <-SEC M1.6.2 */
805/* <-QAC 0857 */
[352]806/* <-QAC 0639 */
807#endif
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