source: asp3_tinet_ecnl_arm/trunk/asp3_dcre/mbed/targets/TARGET_RENESAS/TARGET_RZA1XX/TARGET_RZ_A1H/device/inc/iodefines/disc_iodefine.h@ 374

Last change on this file since 374 was 374, checked in by coas-nagasima, 5 years ago

mbed関連を更新
シリアルドライバをmbedのHALを使うよう変更
ファイルディスクリプタの処理を更新
  • Property svn:eol-style set to native
  • Property svn:mime-type set to text/x-chdr;charset=UTF-8
File size: 5.0 KB
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1/*******************************************************************************
2* DISCLAIMER
3* This software is supplied by Renesas Electronics Corporation and is only
4* intended for use with Renesas products. No other uses are authorized. This
5* software is owned by Renesas Electronics Corporation and is protected under
6* all applicable laws, including copyright laws.
7* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
8* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
9* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
10* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
11* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
12* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
13* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
14* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
15* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
16* Renesas reserves the right, without notice, to make changes to this software
17* and to discontinue the availability of this software. By using this software,
18* you agree to the additional terms and conditions found by accessing the
19* following link:
20* http://www.renesas.com/disclaimer*
21* Copyright (C) 2013-2015 Renesas Electronics Corporation. All rights reserved.
22*******************************************************************************/
23/*******************************************************************************
24* File Name : disc_iodefine.h
25* $Rev: $
26* $Date:: $
27* Description : Definition of I/O Register for RZ/A1H,M (V2.00h)
28******************************************************************************/
29#ifndef DISC_IODEFINE_H
30#define DISC_IODEFINE_H
31/* ->QAC 0639 : Over 127 members (C90) */
32/* ->QAC 0857 : Over 1024 #define (C90) */
33/* ->MISRA 18.4 : Pack unpack union */ /* ->SEC M1.6.2 */
34/* ->SEC M1.10.1 : Not magic number */
35
36#define DISC0 (*(struct st_disc *)0xFCFFA800uL) /* DISC0 */
37#define DISC1 (*(struct st_disc *)0xFCFFB000uL) /* DISC1 */
38
39
40/* Start of channel array defines of DISC */
41
42/* Channel array defines of DISC */
43/*(Sample) value = DISC[ channel ]->DOCMCR; */
44#define DISC_COUNT (2)
45#define DISC_ADDRESS_LIST \
46{ /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \
47 &DISC0, &DISC1 \
48} /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */
49
50/* End of channel array defines of DISC */
51
52
53#define DISC0DOCMCR (DISC0.DOCMCR)
54#define DISC0DOCMSTR (DISC0.DOCMSTR)
55#define DISC0DOCMCLSTR (DISC0.DOCMCLSTR)
56#define DISC0DOCMIENR (DISC0.DOCMIENR)
57#define DISC0DOCMPMR (DISC0.DOCMPMR)
58#define DISC0DOCMECRCR (DISC0.DOCMECRCR)
59#define DISC0DOCMCCRCR (DISC0.DOCMCCRCR)
60#define DISC0DOCMSPXR (DISC0.DOCMSPXR)
61#define DISC0DOCMSPYR (DISC0.DOCMSPYR)
62#define DISC0DOCMSZXR (DISC0.DOCMSZXR)
63#define DISC0DOCMSZYR (DISC0.DOCMSZYR)
64#define DISC0DOCMCRCIR (DISC0.DOCMCRCIR)
65#define DISC1DOCMCR (DISC1.DOCMCR)
66#define DISC1DOCMSTR (DISC1.DOCMSTR)
67#define DISC1DOCMCLSTR (DISC1.DOCMCLSTR)
68#define DISC1DOCMIENR (DISC1.DOCMIENR)
69#define DISC1DOCMPMR (DISC1.DOCMPMR)
70#define DISC1DOCMECRCR (DISC1.DOCMECRCR)
71#define DISC1DOCMCCRCR (DISC1.DOCMCCRCR)
72#define DISC1DOCMSPXR (DISC1.DOCMSPXR)
73#define DISC1DOCMSPYR (DISC1.DOCMSPYR)
74#define DISC1DOCMSZXR (DISC1.DOCMSZXR)
75#define DISC1DOCMSZYR (DISC1.DOCMSZYR)
76#define DISC1DOCMCRCIR (DISC1.DOCMCRCIR)
77
78
79typedef struct st_disc
80{
81 /* DISC */
82 volatile uint32_t DOCMCR; /* DOCMCR */
83 volatile uint32_t DOCMSTR; /* DOCMSTR */
84 volatile uint32_t DOCMCLSTR; /* DOCMCLSTR */
85 volatile uint32_t DOCMIENR; /* DOCMIENR */
86 volatile uint8_t dummy1[4]; /* */
87 volatile uint32_t DOCMPMR; /* DOCMPMR */
88 volatile uint32_t DOCMECRCR; /* DOCMECRCR */
89 volatile uint32_t DOCMCCRCR; /* DOCMCCRCR */
90 volatile uint32_t DOCMSPXR; /* DOCMSPXR */
91 volatile uint32_t DOCMSPYR; /* DOCMSPYR */
92 volatile uint32_t DOCMSZXR; /* DOCMSZXR */
93 volatile uint32_t DOCMSZYR; /* DOCMSZYR */
94 volatile uint32_t DOCMCRCIR; /* DOCMCRCIR */
95} r_io_disc_t;
96
97
98/* Channel array defines of DISC (2)*/
99#ifdef DECLARE_DISC_CHANNELS
100volatile struct st_disc* DISC[ DISC_COUNT ] =
101 /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */
102 DISC_ADDRESS_LIST;
103 /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */
104#endif /* DECLARE_DISC_CHANNELS */
105/* End of channel array defines of DISC (2)*/
106
107
108/* <-SEC M1.10.1 */
109/* <-MISRA 18.4 */ /* <-SEC M1.6.2 */
110/* <-QAC 0857 */
111/* <-QAC 0639 */
112#endif
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