source: asp3_tinet_ecnl_arm/trunk/asp3_dcre/mbed/targets/TARGET_RENESAS/TARGET_RZA1XX/TARGET_RZ_A1H/device/inc/iodefines/cpg_iodefine.h@ 374

Last change on this file since 374 was 374, checked in by coas-nagasima, 5 years ago

mbed関連を更新
シリアルドライバをmbedのHALを使うよう変更
ファイルディスクリプタの処理を更新
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1/*******************************************************************************
2* DISCLAIMER
3* This software is supplied by Renesas Electronics Corporation and is only
4* intended for use with Renesas products. No other uses are authorized. This
5* software is owned by Renesas Electronics Corporation and is protected under
6* all applicable laws, including copyright laws.
7* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
8* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
9* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
10* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
11* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
12* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
13* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
14* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
15* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
16* Renesas reserves the right, without notice, to make changes to this software
17* and to discontinue the availability of this software. By using this software,
18* you agree to the additional terms and conditions found by accessing the
19* following link:
20* http://www.renesas.com/disclaimer*
21* Copyright (C) 2013-2015 Renesas Electronics Corporation. All rights reserved.
22*******************************************************************************/
23/*******************************************************************************
24* File Name : cpg_iodefine.h
25* $Rev: $
26* $Date:: $
27* Description : Definition of I/O Register for RZ/A1H,M (V2.00h)
28******************************************************************************/
29#ifndef CPG_IODEFINE_H
30#define CPG_IODEFINE_H
31/* ->QAC 0639 : Over 127 members (C90) */
32/* ->QAC 0857 : Over 1024 #define (C90) */
33/* ->MISRA 18.4 : Pack unpack union */ /* ->SEC M1.6.2 */
34/* ->SEC M1.10.1 : Not magic number */
35
36#define CPG (*(struct st_cpg *)0xFCFE0010uL) /* CPG */
37
38
39/* Start of channel array defines of CPG */
40
41/* Channel array defines of CPG_FROM_SWRSTCR1_ARRAY */
42/*(Sample) value = CPG_FROM_SWRSTCR1_ARRAY[ channel ]->SWRSTCR1; */
43#define CPG_FROM_SWRSTCR1_ARRAY_COUNT (3)
44#define CPG_FROM_SWRSTCR1_ARRAY_ADDRESS_LIST \
45{ /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \
46 &CPG_FROM_SWRSTCR1, &CPG_FROM_SWRSTCR2, &CPG_FROM_SWRSTCR3 \
47} /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */
48#define CPG_FROM_SWRSTCR1 (*(struct st_cpg_from_swrstcr1 *)&CPG.SWRSTCR1) /* CPG_FROM_SWRSTCR1 */
49#define CPG_FROM_SWRSTCR2 (*(struct st_cpg_from_swrstcr1 *)&CPG.SWRSTCR2) /* CPG_FROM_SWRSTCR2 */
50#define CPG_FROM_SWRSTCR3 (*(struct st_cpg_from_swrstcr1 *)&CPG.SWRSTCR3) /* CPG_FROM_SWRSTCR3 */
51
52
53/* Channel array defines of CPG_FROM_STBCR3_ARRAY */
54/*(Sample) value = CPG_FROM_STBCR3_ARRAY[ channel ]->STBCR3; */
55#define CPG_FROM_STBCR3_ARRAY_COUNT (10)
56#define CPG_FROM_STBCR3_ARRAY_ADDRESS_LIST \
57{ /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \
58 &CPG_FROM_STBCR3, &CPG_FROM_STBCR4, &CPG_FROM_STBCR5, &CPG_FROM_STBCR6, &CPG_FROM_STBCR7, &CPG_FROM_STBCR8, &CPG_FROM_STBCR9, &CPG_FROM_STBCR10, \
59 &CPG_FROM_STBCR11, &CPG_FROM_STBCR12 \
60} /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */
61#define CPG_FROM_STBCR3 (*(struct st_cpg_from_stbcr3 *)&CPG.STBCR3) /* CPG_FROM_STBCR3 */
62#define CPG_FROM_STBCR4 (*(struct st_cpg_from_stbcr3 *)&CPG.STBCR4) /* CPG_FROM_STBCR4 */
63#define CPG_FROM_STBCR5 (*(struct st_cpg_from_stbcr3 *)&CPG.STBCR5) /* CPG_FROM_STBCR5 */
64#define CPG_FROM_STBCR6 (*(struct st_cpg_from_stbcr3 *)&CPG.STBCR6) /* CPG_FROM_STBCR6 */
65#define CPG_FROM_STBCR7 (*(struct st_cpg_from_stbcr3 *)&CPG.STBCR7) /* CPG_FROM_STBCR7 */
66#define CPG_FROM_STBCR8 (*(struct st_cpg_from_stbcr3 *)&CPG.STBCR8) /* CPG_FROM_STBCR8 */
67#define CPG_FROM_STBCR9 (*(struct st_cpg_from_stbcr3 *)&CPG.STBCR9) /* CPG_FROM_STBCR9 */
68#define CPG_FROM_STBCR10 (*(struct st_cpg_from_stbcr3 *)&CPG.STBCR10) /* CPG_FROM_STBCR10 */
69#define CPG_FROM_STBCR11 (*(struct st_cpg_from_stbcr3 *)&CPG.STBCR11) /* CPG_FROM_STBCR11 */
70#define CPG_FROM_STBCR12 (*(struct st_cpg_from_stbcr3 *)&CPG.STBCR12) /* CPG_FROM_STBCR12 */
71
72
73/* Channel array defines of CPG_FROM_SYSCR1_ARRAY */
74/*(Sample) value = CPG_FROM_SYSCR1_ARRAY[ channel ]->SYSCR1; */
75#define CPG_FROM_SYSCR1_ARRAY_COUNT (3)
76#define CPG_FROM_SYSCR1_ARRAY_ADDRESS_LIST \
77{ /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \
78 &CPG_FROM_SYSCR1, &CPG_FROM_SYSCR2, &CPG_FROM_SYSCR3 \
79} /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */
80#define CPG_FROM_SYSCR1 (*(struct st_cpg_from_syscr1 *)&CPG.SYSCR1) /* CPG_FROM_SYSCR1 */
81#define CPG_FROM_SYSCR2 (*(struct st_cpg_from_syscr1 *)&CPG.SYSCR2) /* CPG_FROM_SYSCR2 */
82#define CPG_FROM_SYSCR3 (*(struct st_cpg_from_syscr1 *)&CPG.SYSCR3) /* CPG_FROM_SYSCR3 */
83
84/* End of channel array defines of CPG */
85
86
87#define CPGFRQCR (CPG.FRQCR)
88#define CPGFRQCR2 (CPG.FRQCR2)
89#define CPGCPUSTS (CPG.CPUSTS)
90#define CPGSTBCR1 (CPG.STBCR1)
91#define CPGSTBCR2 (CPG.STBCR2)
92#define CPGSTBREQ1 (CPG.STBREQ1)
93#define CPGSTBREQ2 (CPG.STBREQ2)
94#define CPGSTBACK1 (CPG.STBACK1)
95#define CPGSTBACK2 (CPG.STBACK2)
96#define CPGSYSCR1 (CPG.SYSCR1)
97#define CPGSYSCR2 (CPG.SYSCR2)
98#define CPGSYSCR3 (CPG.SYSCR3)
99#define CPGSTBCR3 (CPG.STBCR3)
100#define CPGSTBCR4 (CPG.STBCR4)
101#define CPGSTBCR5 (CPG.STBCR5)
102#define CPGSTBCR6 (CPG.STBCR6)
103#define CPGSTBCR7 (CPG.STBCR7)
104#define CPGSTBCR8 (CPG.STBCR8)
105#define CPGSTBCR9 (CPG.STBCR9)
106#define CPGSTBCR10 (CPG.STBCR10)
107#define CPGSTBCR11 (CPG.STBCR11)
108#define CPGSTBCR12 (CPG.STBCR12)
109#define CPGSWRSTCR1 (CPG.SWRSTCR1)
110#define CPGSWRSTCR2 (CPG.SWRSTCR2)
111#define CPGSWRSTCR3 (CPG.SWRSTCR3)
112#define CPGSTBCR13 (CPG.STBCR13)
113#define CPGRRAMKP (CPG.RRAMKP)
114#define CPGDSCTR (CPG.DSCTR)
115#define CPGDSSSR (CPG.DSSSR)
116#define CPGDSESR (CPG.DSESR)
117#define CPGDSFR (CPG.DSFR)
118#define CPGXTALCTR (CPG.XTALCTR)
119
120
121typedef struct st_cpg
122{
123 /* CPG */
124 volatile uint16_t FRQCR; /* FRQCR */
125 volatile uint8_t dummy319[2]; /* */
126 volatile uint16_t FRQCR2; /* FRQCR2 */
127 volatile uint8_t dummy320[2]; /* */
128 volatile uint8_t CPUSTS; /* CPUSTS */
129 volatile uint8_t dummy321[7]; /* */
130 volatile uint8_t STBCR1; /* STBCR1 */
131 volatile uint8_t dummy322[3]; /* */
132 volatile uint8_t STBCR2; /* STBCR2 */
133 volatile uint8_t dummy323[11]; /* */
134 volatile uint8_t STBREQ1; /* STBREQ1 */
135 volatile uint8_t dummy324[3]; /* */
136 volatile uint8_t STBREQ2; /* STBREQ2 */
137 volatile uint8_t dummy325[11]; /* */
138 volatile uint8_t STBACK1; /* STBACK1 */
139 volatile uint8_t dummy326[3]; /* */
140 volatile uint8_t STBACK2; /* STBACK2 */
141 volatile uint8_t dummy327[955]; /* */
142
143/* start of struct st_cpg_from_syscr1 */
144 volatile uint8_t SYSCR1; /* SYSCR1 */
145 volatile uint8_t dummy328[3]; /* */
146
147/* end of struct st_cpg_from_syscr1 */
148
149/* start of struct st_cpg_from_syscr1 */
150 volatile uint8_t SYSCR2; /* SYSCR2 */
151 volatile uint8_t dummy329[3]; /* */
152
153/* end of struct st_cpg_from_syscr1 */
154
155/* start of struct st_cpg_from_syscr1 */
156 volatile uint8_t SYSCR3; /* SYSCR3 */
157 volatile uint8_t dummy3300[3]; /* */
158
159/* end of struct st_cpg_from_syscr1 */
160 volatile uint8_t dummy3301[20]; /* */
161
162/* start of struct st_cpg_from_stbcr3 */
163 volatile uint8_t STBCR3; /* STBCR3 */
164 volatile uint8_t dummy331[3]; /* */
165
166/* end of struct st_cpg_from_stbcr3 */
167
168/* start of struct st_cpg_from_stbcr3 */
169 volatile uint8_t STBCR4; /* STBCR4 */
170 volatile uint8_t dummy332[3]; /* */
171
172/* end of struct st_cpg_from_stbcr3 */
173
174/* start of struct st_cpg_from_stbcr3 */
175 volatile uint8_t STBCR5; /* STBCR5 */
176 volatile uint8_t dummy333[3]; /* */
177
178/* end of struct st_cpg_from_stbcr3 */
179
180/* start of struct st_cpg_from_stbcr3 */
181 volatile uint8_t STBCR6; /* STBCR6 */
182 volatile uint8_t dummy334[3]; /* */
183
184/* end of struct st_cpg_from_stbcr3 */
185
186/* start of struct st_cpg_from_stbcr3 */
187 volatile uint8_t STBCR7; /* STBCR7 */
188 volatile uint8_t dummy335[3]; /* */
189
190/* end of struct st_cpg_from_stbcr3 */
191
192/* start of struct st_cpg_from_stbcr3 */
193 volatile uint8_t STBCR8; /* STBCR8 */
194 volatile uint8_t dummy336[3]; /* */
195
196/* end of struct st_cpg_from_stbcr3 */
197
198/* start of struct st_cpg_from_stbcr3 */
199 volatile uint8_t STBCR9; /* STBCR9 */
200 volatile uint8_t dummy337[3]; /* */
201
202/* end of struct st_cpg_from_stbcr3 */
203
204/* start of struct st_cpg_from_stbcr3 */
205 volatile uint8_t STBCR10; /* STBCR10 */
206 volatile uint8_t dummy338[3]; /* */
207
208/* end of struct st_cpg_from_stbcr3 */
209
210/* start of struct st_cpg_from_stbcr3 */
211 volatile uint8_t STBCR11; /* STBCR11 */
212 volatile uint8_t dummy339[3]; /* */
213
214/* end of struct st_cpg_from_stbcr3 */
215
216/* start of struct st_cpg_from_stbcr3 */
217 volatile uint8_t STBCR12; /* STBCR12 */
218 volatile uint8_t dummy3400[3]; /* */
219
220/* end of struct st_cpg_from_stbcr3 */
221 volatile uint8_t dummy3401[24]; /* */
222
223/* start of struct st_cpg_from_swrstcr1 */
224 volatile uint8_t SWRSTCR1; /* SWRSTCR1 */
225 volatile uint8_t dummy341[3]; /* */
226
227/* end of struct st_cpg_from_swrstcr1 */
228
229/* start of struct st_cpg_from_swrstcr1 */
230 volatile uint8_t SWRSTCR2; /* SWRSTCR2 */
231 volatile uint8_t dummy342[3]; /* */
232
233/* end of struct st_cpg_from_swrstcr1 */
234
235/* start of struct st_cpg_from_swrstcr1 */
236 volatile uint8_t SWRSTCR3; /* SWRSTCR3 */
237 volatile uint8_t dummy3430[3]; /* */
238
239/* end of struct st_cpg_from_swrstcr1 */
240 volatile uint8_t dummy3431[4]; /* */
241 volatile uint8_t STBCR13; /* STBCR13 */
242 volatile uint8_t dummy344[70543]; /* */
243 volatile uint8_t RRAMKP; /* RRAMKP */
244 volatile uint8_t dummy345[1]; /* */
245 volatile uint8_t DSCTR; /* DSCTR */
246 volatile uint8_t dummy346[1]; /* */
247 volatile uint16_t DSSSR; /* DSSSR */
248 volatile uint16_t DSESR; /* DSESR */
249 volatile uint16_t DSFR; /* DSFR */
250 volatile uint8_t dummy347[6]; /* */
251 volatile uint8_t XTALCTR; /* XTALCTR */
252} r_io_cpg_t;
253
254
255typedef struct st_cpg_from_syscr1
256{
257
258 volatile uint8_t SYSCR1; /* SYSCR1 */
259 volatile uint8_t dummy1[3]; /* */
260} r_io_cpg_from_syscr1_t;
261
262
263typedef struct st_cpg_from_stbcr3
264{
265
266 volatile uint8_t STBCR3; /* STBCR3 */
267 volatile uint8_t dummy1[3]; /* */
268} r_io_cpg_from_stbcr3_t;
269
270
271typedef struct st_cpg_from_swrstcr1
272{
273
274 volatile uint8_t SWRSTCR1; /* SWRSTCR1 */
275 volatile uint8_t dummy1[3]; /* */
276} r_io_cpg_from_swrstcr1_t;
277
278
279/* Channel array defines of CPG (2)*/
280#ifdef DECLARE_CPG_FROM_SWRSTCR1_ARRAY_CHANNELS
281volatile struct st_cpg_from_swrstcr1* CPG_FROM_SWRSTCR1_ARRAY[ CPG_FROM_SWRSTCR1_ARRAY_COUNT ] =
282 /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */
283 CPG_FROM_SWRSTCR1_ARRAY_ADDRESS_LIST;
284 /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */
285#endif /* DECLARE_CPG_FROM_SWRSTCR1_ARRAY_CHANNELS */
286
287#ifdef DECLARE_CPG_FROM_STBCR3_ARRAY_CHANNELS
288volatile struct st_cpg_from_stbcr3* CPG_FROM_STBCR3_ARRAY[ CPG_FROM_STBCR3_ARRAY_COUNT ] =
289 /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */
290 CPG_FROM_STBCR3_ARRAY_ADDRESS_LIST;
291 /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */
292#endif /* DECLARE_CPG_FROM_STBCR3_ARRAY_CHANNELS */
293
294#ifdef DECLARE_CPG_FROM_SYSCR1_ARRAY_CHANNELS
295volatile struct st_cpg_from_syscr1* CPG_FROM_SYSCR1_ARRAY[ CPG_FROM_SYSCR1_ARRAY_COUNT ] =
296 /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */
297 CPG_FROM_SYSCR1_ARRAY_ADDRESS_LIST;
298 /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */
299#endif /* DECLARE_CPG_FROM_SYSCR1_ARRAY_CHANNELS */
300/* End of channel array defines of CPG (2)*/
301
302
303/* <-SEC M1.10.1 */
304/* <-MISRA 18.4 */ /* <-SEC M1.6.2 */
305/* <-QAC 0857 */
306/* <-QAC 0639 */
307#endif
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