source: asp3_tinet_ecnl_arm/trunk/asp3_dcre/mbed/targets/TARGET_RENESAS/TARGET_RZA1XX/TARGET_RZ_A1H/device/inc/iodefines/ceu_iodefine.h@ 374

Last change on this file since 374 was 374, checked in by coas-nagasima, 5 years ago

mbed関連を更新
シリアルドライバをmbedのHALを使うよう変更
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1/*******************************************************************************
2* DISCLAIMER
3* This software is supplied by Renesas Electronics Corporation and is only
4* intended for use with Renesas products. No other uses are authorized. This
5* software is owned by Renesas Electronics Corporation and is protected under
6* all applicable laws, including copyright laws.
7* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
8* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
9* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
10* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
11* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
12* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
13* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
14* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
15* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
16* Renesas reserves the right, without notice, to make changes to this software
17* and to discontinue the availability of this software. By using this software,
18* you agree to the additional terms and conditions found by accessing the
19* following link:
20* http://www.renesas.com/disclaimer*
21* Copyright (C) 2013-2015 Renesas Electronics Corporation. All rights reserved.
22*******************************************************************************/
23/*******************************************************************************
24* File Name : ceu_iodefine.h
25* $Rev: $
26* $Date:: $
27* Description : Definition of I/O Register for RZ/A1H,M (V2.00h)
28******************************************************************************/
29#ifndef CEU_IODEFINE_H
30#define CEU_IODEFINE_H
31/* ->QAC 0639 : Over 127 members (C90) */
32/* ->QAC 0857 : Over 1024 #define (C90) */
33/* ->MISRA 18.4 : Pack unpack union */ /* ->SEC M1.6.2 */
34/* ->SEC M1.10.1 : Not magic number */
35
36#define CEU (*(struct st_ceu *)0xE8210000uL) /* CEU */
37
38
39/* Start of channel array defines of CEU */
40
41/* Channel array defines of CEUn */
42/*(Sample) value = CEUn[ channel ]->CAMOR; */
43#define CEUn_COUNT (3)
44#define CEUn_ADDRESS_LIST \
45{ /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \
46 (volatile struct st_ceu_n*)&CEU_A, \
47 (volatile struct st_ceu_n*)&CEU_B, \
48 (volatile struct st_ceu_n*)&CEU_M \
49} /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */
50#define CEU_A (*(struct st_ceu_n *)&CEU.CAPSR) /* CEU_A */
51#define CEU_B (*(struct st_ceu_n *)&CEU.dummy3111) /* CEU_B */
52#define CEU_M (*(struct st_ceu_n *)&CEU.dummy3151) /* CEU_M */
53
54/* End of channel array defines of CEU */
55
56
57#define CEUCAPSR (CEU.CAPSR)
58#define CEUCAPCR (CEU.CAPCR)
59#define CEUCAMCR (CEU.CAMCR)
60#define CEUCMCYR (CEU.CMCYR)
61#define CEUCAMOR_A (CEU.CAMOR_A)
62#define CEUCAPWR_A (CEU.CAPWR_A)
63#define CEUCAIFR (CEU.CAIFR)
64#define CEUCRCNTR (CEU.CRCNTR)
65#define CEUCRCMPR (CEU.CRCMPR)
66#define CEUCFLCR_A (CEU.CFLCR_A)
67#define CEUCFSZR_A (CEU.CFSZR_A)
68#define CEUCDWDR_A (CEU.CDWDR_A)
69#define CEUCDAYR_A (CEU.CDAYR_A)
70#define CEUCDACR_A (CEU.CDACR_A)
71#define CEUCDBYR_A (CEU.CDBYR_A)
72#define CEUCDBCR_A (CEU.CDBCR_A)
73#define CEUCBDSR_A (CEU.CBDSR_A)
74#define CEUCFWCR (CEU.CFWCR)
75#define CEUCLFCR_A (CEU.CLFCR_A)
76#define CEUCDOCR_A (CEU.CDOCR_A)
77#define CEUCEIER (CEU.CEIER)
78#define CEUCETCR (CEU.CETCR)
79#define CEUCSTSR (CEU.CSTSR)
80#define CEUCDSSR (CEU.CDSSR)
81#define CEUCDAYR2_A (CEU.CDAYR2_A)
82#define CEUCDACR2_A (CEU.CDACR2_A)
83#define CEUCDBYR2_A (CEU.CDBYR2_A)
84#define CEUCDBCR2_A (CEU.CDBCR2_A)
85#define CEUCAMOR_B (CEU.CAMOR_B)
86#define CEUCAPWR_B (CEU.CAPWR_B)
87#define CEUCFLCR_B (CEU.CFLCR_B)
88#define CEUCFSZR_B (CEU.CFSZR_B)
89#define CEUCDWDR_B (CEU.CDWDR_B)
90#define CEUCDAYR_B (CEU.CDAYR_B)
91#define CEUCDACR_B (CEU.CDACR_B)
92#define CEUCDBYR_B (CEU.CDBYR_B)
93#define CEUCDBCR_B (CEU.CDBCR_B)
94#define CEUCBDSR_B (CEU.CBDSR_B)
95#define CEUCLFCR_B (CEU.CLFCR_B)
96#define CEUCDOCR_B (CEU.CDOCR_B)
97#define CEUCDAYR2_B (CEU.CDAYR2_B)
98#define CEUCDACR2_B (CEU.CDACR2_B)
99#define CEUCDBYR2_B (CEU.CDBYR2_B)
100#define CEUCDBCR2_B (CEU.CDBCR2_B)
101#define CEUCAMOR_M (CEU.CAMOR_M)
102#define CEUCAPWR_M (CEU.CAPWR_M)
103#define CEUCFLCR_M (CEU.CFLCR_M)
104#define CEUCFSZR_M (CEU.CFSZR_M)
105#define CEUCDWDR_M (CEU.CDWDR_M)
106#define CEUCDAYR_M (CEU.CDAYR_M)
107#define CEUCDACR_M (CEU.CDACR_M)
108#define CEUCDBYR_M (CEU.CDBYR_M)
109#define CEUCDBCR_M (CEU.CDBCR_M)
110#define CEUCBDSR_M (CEU.CBDSR_M)
111#define CEUCLFCR_M (CEU.CLFCR_M)
112#define CEUCDOCR_M (CEU.CDOCR_M)
113#define CEUCDAYR2_M (CEU.CDAYR2_M)
114#define CEUCDACR2_M (CEU.CDACR2_M)
115#define CEUCDBYR2_M (CEU.CDBYR2_M)
116#define CEUCDBCR2_M (CEU.CDBCR2_M)
117
118
119typedef struct st_ceu
120{
121 /* CEU */
122
123/* start of struct st_ceu_n */
124 volatile uint32_t CAPSR; /* CAPSR */
125 volatile uint32_t CAPCR; /* CAPCR */
126 volatile uint32_t CAMCR; /* CAMCR */
127 volatile uint32_t CMCYR; /* CMCYR */
128 volatile uint32_t CAMOR_A; /* CAMOR_A */
129 volatile uint32_t CAPWR_A; /* CAPWR_A */
130 volatile uint32_t CAIFR; /* CAIFR */
131 volatile uint8_t dummy305[12]; /* */
132 volatile uint32_t CRCNTR; /* CRCNTR */
133 volatile uint32_t CRCMPR; /* CRCMPR */
134 volatile uint32_t CFLCR_A; /* CFLCR_A */
135 volatile uint32_t CFSZR_A; /* CFSZR_A */
136 volatile uint32_t CDWDR_A; /* CDWDR_A */
137 volatile uint32_t CDAYR_A; /* CDAYR_A */
138 volatile uint32_t CDACR_A; /* CDACR_A */
139 volatile uint32_t CDBYR_A; /* CDBYR_A */
140 volatile uint32_t CDBCR_A; /* CDBCR_A */
141 volatile uint32_t CBDSR_A; /* CBDSR_A */
142 volatile uint8_t dummy306[12]; /* */
143 volatile uint32_t CFWCR; /* CFWCR */
144 volatile uint32_t CLFCR_A; /* CLFCR_A */
145 volatile uint32_t CDOCR_A; /* CDOCR_A */
146 volatile uint8_t dummy307[8]; /* */
147 volatile uint32_t CEIER; /* CEIER */
148 volatile uint32_t CETCR; /* CETCR */
149 volatile uint8_t dummy308[4]; /* */
150 volatile uint32_t CSTSR; /* CSTSR */
151 volatile uint8_t dummy309[4]; /* */
152 volatile uint32_t CDSSR; /* CDSSR */
153 volatile uint8_t dummy310[8]; /* */
154 volatile uint32_t CDAYR2_A; /* CDAYR2_A */
155 volatile uint32_t CDACR2_A; /* CDACR2_A */
156 volatile uint32_t CDBYR2_A; /* CDBYR2_A */
157 volatile uint32_t CDBCR2_A; /* CDBCR2_A */
158
159/* end of struct st_ceu_n */
160 volatile uint8_t dummy3110[3936]; /* */
161
162/* start of struct st_ceu_n */
163 volatile uint8_t dummy3111[4]; /* */
164 volatile uint8_t dummy3112[4]; /* */
165 volatile uint8_t dummy3113[4]; /* */
166 volatile uint8_t dummy3114[4]; /* */
167 volatile uint32_t CAMOR_B; /* CAMOR_B */
168 volatile uint32_t CAPWR_B; /* CAPWR_B */
169 volatile uint8_t dummy3120[4]; /* */
170 volatile uint8_t dummy3121[12]; /* */
171 volatile uint8_t dummy3122[4]; /* */
172 volatile uint8_t dummy3123[4]; /* */
173 volatile uint32_t CFLCR_B; /* CFLCR_B */
174 volatile uint32_t CFSZR_B; /* CFSZR_B */
175 volatile uint32_t CDWDR_B; /* CDWDR_B */
176 volatile uint32_t CDAYR_B; /* CDAYR_B */
177 volatile uint32_t CDACR_B; /* CDACR_B */
178 volatile uint32_t CDBYR_B; /* CDBYR_B */
179 volatile uint32_t CDBCR_B; /* CDBCR_B */
180 volatile uint32_t CBDSR_B; /* CBDSR_B */
181 volatile uint8_t dummy3130[12]; /* */
182 volatile uint8_t dummy3131[4]; /* */
183 volatile uint32_t CLFCR_B; /* CLFCR_B */
184 volatile uint32_t CDOCR_B; /* CDOCR_B */
185 volatile uint8_t dummy3140[8]; /* */
186 volatile uint8_t dummy3141[4]; /* */
187 volatile uint8_t dummy3142[4]; /* */
188 volatile uint8_t dummy3143[4]; /* */
189 volatile uint8_t dummy3144[4]; /* */
190 volatile uint8_t dummy3145[4]; /* */
191 volatile uint8_t dummy3146[4]; /* */
192 volatile uint8_t dummy3147[8]; /* */
193 volatile uint32_t CDAYR2_B; /* CDAYR2_B */
194 volatile uint32_t CDACR2_B; /* CDACR2_B */
195 volatile uint32_t CDBYR2_B; /* CDBYR2_B */
196 volatile uint32_t CDBCR2_B; /* CDBCR2_B */
197
198/* end of struct st_ceu_n */
199 volatile uint8_t dummy3150[3936]; /* */
200
201/* start of struct st_ceu_n */
202 volatile uint8_t dummy3151[4]; /* */
203 volatile uint8_t dummy3152[4]; /* */
204 volatile uint8_t dummy3153[4]; /* */
205 volatile uint8_t dummy3154[4]; /* */
206 volatile uint32_t CAMOR_M; /* CAMOR_M */
207 volatile uint32_t CAPWR_M; /* CAPWR_M */
208 volatile uint8_t dummy3160[4]; /* */
209 volatile uint8_t dummy3161[12]; /* */
210 volatile uint8_t dummy3162[4]; /* */
211 volatile uint8_t dummy3163[4]; /* */
212 volatile uint32_t CFLCR_M; /* CFLCR_M */
213 volatile uint32_t CFSZR_M; /* CFSZR_M */
214 volatile uint32_t CDWDR_M; /* CDWDR_M */
215 volatile uint32_t CDAYR_M; /* CDAYR_M */
216 volatile uint32_t CDACR_M; /* CDACR_M */
217 volatile uint32_t CDBYR_M; /* CDBYR_M */
218 volatile uint32_t CDBCR_M; /* CDBCR_M */
219 volatile uint32_t CBDSR_M; /* CBDSR_M */
220 volatile uint8_t dummy3170[12]; /* */
221 volatile uint8_t dummy3171[4]; /* */
222 volatile uint32_t CLFCR_M; /* CLFCR_M */
223 volatile uint32_t CDOCR_M; /* CDOCR_M */
224 volatile uint8_t dummy3180[8]; /* */
225 volatile uint8_t dummy3181[4]; /* */
226 volatile uint8_t dummy3182[4]; /* */
227 volatile uint8_t dummy3183[4]; /* */
228 volatile uint8_t dummy3184[4]; /* */
229 volatile uint8_t dummy3185[4]; /* */
230 volatile uint8_t dummy3186[4]; /* */
231 volatile uint8_t dummy3187[8]; /* */
232 volatile uint32_t CDAYR2_M; /* CDAYR2_M */
233 volatile uint32_t CDACR2_M; /* CDACR2_M */
234 volatile uint32_t CDBYR2_M; /* CDBYR2_M */
235 volatile uint32_t CDBCR2_M; /* CDBCR2_M */
236
237/* end of struct st_ceu_n */
238} r_io_ceu_t;
239
240
241typedef struct st_ceu_n
242{
243
244 volatile uint32_t not_common1; /* */
245 volatile uint32_t not_common2; /* */
246 volatile uint32_t not_common3; /* */
247 volatile uint32_t not_common4; /* */
248 volatile uint32_t CAMOR; /* CAMOR */
249 volatile uint32_t CAPWR; /* CAPWR */
250 volatile uint32_t not_common5; /* */
251 volatile uint8_t dummy322[12]; /* */
252 volatile uint32_t not_common6; /* */
253 volatile uint32_t not_common7; /* */
254 volatile uint32_t CFLCR; /* CFLCR */
255 volatile uint32_t CFSZR; /* CFSZR */
256 volatile uint32_t CDWDR; /* CDWDR */
257 volatile uint32_t CDAYR; /* CDAYR */
258 volatile uint32_t CDACR; /* CDACR */
259 volatile uint32_t CDBYR; /* CDBYR */
260 volatile uint32_t CDBCR; /* CDBCR */
261 volatile uint32_t CBDSR; /* CBDSR */
262 volatile uint8_t dummy323[12]; /* */
263 volatile uint32_t not_common8; /* */
264 volatile uint32_t CLFCR; /* CLFCR */
265 volatile uint32_t CDOCR; /* CDOCR */
266 volatile uint8_t dummy324[8]; /* */
267 volatile uint32_t not_common9; /* */
268 volatile uint32_t not_common10; /* */
269 volatile uint8_t dummy325[4]; /* */
270 volatile uint32_t not_common11; /* */
271 volatile uint8_t dummy326[4]; /* */
272 volatile uint32_t not_common12; /* */
273 volatile uint8_t dummy327[8]; /* */
274 volatile uint32_t CDAYR2; /* CDAYR2 */
275 volatile uint32_t CDACR2; /* CDACR2 */
276 volatile uint32_t CDBYR2; /* CDBYR2 */
277 volatile uint32_t CDBCR2; /* CDBCR2 */
278} r_io_ceu_n_t;
279
280
281/* Channel array defines of CEUn (2)*/
282#ifdef DECLARE_CEUn_CHANNELS
283volatile struct st_ceu_n* CEUn[ CEUn_COUNT ] =
284 /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */
285 CEUn_ADDRESS_LIST;
286 /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */
287#endif /* DECLARE_CEUn_CHANNELS */
288/* End of channel array defines of CEUn (2)*/
289
290
291/* <-SEC M1.10.1 */
292/* <-MISRA 18.4 */ /* <-SEC M1.6.2 */
293/* <-QAC 0857 */
294/* <-QAC 0639 */
295#endif
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