source: asp3_tinet_ecnl_arm/trunk/asp3_dcre/mbed/targets/TARGET_RENESAS/TARGET_RZA1XX/TARGET_RZ_A1H/device/inc/iodefines/adc_iodefine.h@ 374

Last change on this file since 374 was 374, checked in by coas-nagasima, 5 years ago

mbed関連を更新
シリアルドライバをmbedのHALを使うよう変更
ファイルディスクリプタの処理を更新
  • Property svn:eol-style set to native
  • Property svn:mime-type set to text/x-chdr;charset=UTF-8
File size: 5.5 KB
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1/*******************************************************************************
2* DISCLAIMER
3* This software is supplied by Renesas Electronics Corporation and is only
4* intended for use with Renesas products. No other uses are authorized. This
5* software is owned by Renesas Electronics Corporation and is protected under
6* all applicable laws, including copyright laws.
7* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
8* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
9* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
10* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
11* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
12* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
13* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
14* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
15* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
16* Renesas reserves the right, without notice, to make changes to this software
17* and to discontinue the availability of this software. By using this software,
18* you agree to the additional terms and conditions found by accessing the
19* following link:
20* http://www.renesas.com/disclaimer*
21* Copyright (C) 2013-2015 Renesas Electronics Corporation. All rights reserved.
22*******************************************************************************/
23/*******************************************************************************
24* File Name : adc_iodefine.h
25* $Rev: $
26* $Date:: $
27* Description : Definition of I/O Register for RZ/A1H,M (V2.00h)
28******************************************************************************/
29#ifndef ADC_IODEFINE_H
30#define ADC_IODEFINE_H
31/* ->QAC 0639 : Over 127 members (C90) */
32/* ->QAC 0857 : Over 1024 #define (C90) */
33/* ->MISRA 18.4 : Pack unpack union */ /* ->SEC M1.6.2 */
34/* ->SEC M1.10.1 : Not magic number */
35
36#define ADC (*(struct st_adc *)0xE8005800uL) /* ADC */
37
38
39#define ADCADDRA (ADC.ADDRA)
40#define ADCADDRB (ADC.ADDRB)
41#define ADCADDRC (ADC.ADDRC)
42#define ADCADDRD (ADC.ADDRD)
43#define ADCADDRE (ADC.ADDRE)
44#define ADCADDRF (ADC.ADDRF)
45#define ADCADDRG (ADC.ADDRG)
46#define ADCADDRH (ADC.ADDRH)
47#define ADCADCMPHA (ADC.ADCMPHA)
48#define ADCADCMPLA (ADC.ADCMPLA)
49#define ADCADCMPHB (ADC.ADCMPHB)
50#define ADCADCMPLB (ADC.ADCMPLB)
51#define ADCADCMPHC (ADC.ADCMPHC)
52#define ADCADCMPLC (ADC.ADCMPLC)
53#define ADCADCMPHD (ADC.ADCMPHD)
54#define ADCADCMPLD (ADC.ADCMPLD)
55#define ADCADCMPHE (ADC.ADCMPHE)
56#define ADCADCMPLE (ADC.ADCMPLE)
57#define ADCADCMPHF (ADC.ADCMPHF)
58#define ADCADCMPLF (ADC.ADCMPLF)
59#define ADCADCMPHG (ADC.ADCMPHG)
60#define ADCADCMPLG (ADC.ADCMPLG)
61#define ADCADCMPHH (ADC.ADCMPHH)
62#define ADCADCMPLH (ADC.ADCMPLH)
63#define ADCADCSR (ADC.ADCSR)
64#define ADCADCMPER (ADC.ADCMPER)
65#define ADCADCMPSR (ADC.ADCMPSR)
66
67
68typedef struct st_adc
69{
70 /* ADC */
71 volatile uint16_t ADDRA; /* ADDRA */
72 volatile uint16_t ADDRB; /* ADDRB */
73 volatile uint16_t ADDRC; /* ADDRC */
74 volatile uint16_t ADDRD; /* ADDRD */
75 volatile uint16_t ADDRE; /* ADDRE */
76 volatile uint16_t ADDRF; /* ADDRF */
77 volatile uint16_t ADDRG; /* ADDRG */
78 volatile uint16_t ADDRH; /* ADDRH */
79 volatile uint8_t dummy32[16]; /* */
80 volatile uint16_t ADCMPHA; /* ADCMPHA */
81 volatile uint16_t ADCMPLA; /* ADCMPLA */
82 volatile uint16_t ADCMPHB; /* ADCMPHB */
83 volatile uint16_t ADCMPLB; /* ADCMPLB */
84 volatile uint16_t ADCMPHC; /* ADCMPHC */
85 volatile uint16_t ADCMPLC; /* ADCMPLC */
86 volatile uint16_t ADCMPHD; /* ADCMPHD */
87 volatile uint16_t ADCMPLD; /* ADCMPLD */
88 volatile uint16_t ADCMPHE; /* ADCMPHE */
89 volatile uint16_t ADCMPLE; /* ADCMPLE */
90 volatile uint16_t ADCMPHF; /* ADCMPHF */
91 volatile uint16_t ADCMPLF; /* ADCMPLF */
92 volatile uint16_t ADCMPHG; /* ADCMPHG */
93 volatile uint16_t ADCMPLG; /* ADCMPLG */
94 volatile uint16_t ADCMPHH; /* ADCMPHH */
95 volatile uint16_t ADCMPLH; /* ADCMPLH */
96 volatile uint8_t dummy33[32]; /* */
97 volatile uint16_t ADCSR; /* ADCSR */
98 volatile uint16_t ADCMPER; /* ADCMPER */
99 volatile uint16_t ADCMPSR; /* ADCMPSR */
100} r_io_adc_t;
101
102
103/* <-SEC M1.10.1 */
104/* <-MISRA 18.4 */ /* <-SEC M1.6.2 */
105/* <-QAC 0857 */
106/* <-QAC 0639 */
107#endif
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