| 1 | /*******************************************************************************
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| 2 | * DISCLAIMER
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| 3 | * This software is supplied by Renesas Electronics Corporation and is only
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| 4 | * intended for use with Renesas products. No other uses are authorized. This
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| 5 | * software is owned by Renesas Electronics Corporation and is protected under
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| 6 | * all applicable laws, including copyright laws.
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| 7 | * THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
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| 8 | * THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
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| 9 | * LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
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| 10 | * AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
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| 11 | * TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
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| 12 | * ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
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| 13 | * FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
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| 14 | * ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
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| 15 | * BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
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| 16 | * Renesas reserves the right, without notice, to make changes to this software
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| 17 | * and to discontinue the availability of this software. By using this software,
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| 18 | * you agree to the additional terms and conditions found by accessing the
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| 19 | * following link:
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| 20 | * http://www.renesas.com/disclaimer
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| 21 | *
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| 22 | * Copyright (C) 2013 Renesas Electronics Corporation. All rights reserved.
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| 23 | *******************************************************************************/
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| 24 | /*******************************************************************************
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| 25 | * File Name : spibsc_iobitmask.h
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| 26 | * $Rev: $
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| 27 | * $Date:: $
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| 28 | * Description : SPI multi I/O bus controller register define header
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| 29 | *******************************************************************************/
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| 30 | #ifndef SPIBSC_IOBITMASK_H
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| 31 | #define SPIBSC_IOBITMASK_H
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| 32 |
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| 33 |
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| 34 | /* ==== Mask values for IO registers ==== */
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| 35 | #define SPIBSC_CMNCR_BSZ (0x00000003uL)
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| 36 |
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| 37 | #define SPIBSC_CMNCR_CPOL (0x00000008uL)
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| 38 | #define SPIBSC_CMNCR_SSLP (0x00000010uL)
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| 39 | #define SPIBSC_CMNCR_CPHAR (0x00000020uL)
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| 40 | #define SPIBSC_CMNCR_CPHAT (0x00000040uL)
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| 41 |
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| 42 | #define SPIBSC_CMNCR_IO0FV (0x00000300uL)
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| 43 |
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| 44 | #define SPIBSC_CMNCR_IO2FV (0x00003000uL)
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| 45 | #define SPIBSC_CMNCR_IO3FV (0x0000C000uL)
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| 46 | #define SPIBSC_CMNCR_MOIIO0 (0x00030000uL)
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| 47 | #define SPIBSC_CMNCR_MOIIO1 (0x000C0000uL)
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| 48 | #define SPIBSC_CMNCR_MOIIO2 (0x00300000uL)
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| 49 | #define SPIBSC_CMNCR_MOIIO3 (0x00C00000uL)
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| 50 | #define SPIBSC_CMNCR_SFDE (0x01000000uL)
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| 51 |
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| 52 | #define SPIBSC_CMNCR_MD (0x80000000uL)
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| 53 |
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| 54 | #define SPIBSC_SSLDR_SCKDL (0x00000007uL)
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| 55 |
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| 56 | #define SPIBSC_SSLDR_SLNDL (0x00000700uL)
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| 57 |
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| 58 | #define SPIBSC_SSLDR_SPNDL (0x00070000uL)
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| 59 |
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| 60 | #define SPIBSC_SPBCR_BRDV (0x00000003uL)
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| 61 |
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| 62 | #define SPIBSC_SPBCR_SPBR (0x0000FF00uL)
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| 63 |
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| 64 | #define SPIBSC_DRCR_SSLE (0x00000001uL)
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| 65 |
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| 66 | #define SPIBSC_DRCR_RBE (0x00000100uL)
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| 67 | #define SPIBSC_DRCR_RCF (0x00000200uL)
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| 68 |
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| 69 | #define SPIBSC_DRCR_RBURST (0x000F0000uL)
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| 70 |
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| 71 | #define SPIBSC_DRCR_SSLN (0x01000000uL)
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| 72 |
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| 73 | #define SPIBSC_DRCMR_OCMD (0x000000FFuL)
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| 74 |
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| 75 | #define SPIBSC_DRCMR_CMD (0x00FF0000uL)
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| 76 |
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| 77 | #define SPIBSC_DREAR_EAC (0x00000007uL)
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| 78 |
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| 79 | #define SPIBSC_DREAR_EAV (0x00FF0000uL)
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| 80 |
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| 81 | #define SPIBSC_DROPR_OPD0 (0x000000FFuL)
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| 82 | #define SPIBSC_DROPR_OPD1 (0x0000FF00uL)
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| 83 | #define SPIBSC_DROPR_OPD2 (0x00FF0000uL)
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| 84 | #define SPIBSC_DROPR_OPD3 (0xFF000000uL)
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| 85 |
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| 86 | #define SPIBSC_DRENR_OPDE (0x000000F0uL)
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| 87 | #define SPIBSC_DRENR_ADE (0x00000F00uL)
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| 88 | #define SPIBSC_DRENR_OCDE (0x00001000uL)
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| 89 |
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| 90 | #define SPIBSC_DRENR_CDE (0x00004000uL)
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| 91 | #define SPIBSC_DRENR_DME (0x00008000uL)
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| 92 | #define SPIBSC_DRENR_DRDB (0x00030000uL)
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| 93 |
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| 94 | #define SPIBSC_DRENR_OPDB (0x00300000uL)
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| 95 |
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| 96 | #define SPIBSC_DRENR_ADB (0x03000000uL)
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| 97 |
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| 98 | #define SPIBSC_DRENR_OCDB (0x30000000uL)
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| 99 | #define SPIBSC_DRENR_CDB (0xC0000000uL)
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| 100 |
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| 101 | #define SPIBSC_SMCR_SPIE (0x00000001uL)
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| 102 | #define SPIBSC_SMCR_SPIWE (0x00000002uL)
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| 103 | #define SPIBSC_SMCR_SPIRE (0x00000004uL)
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| 104 |
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| 105 | #define SPIBSC_SMCR_SSLKP (0x00000100uL)
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| 106 |
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| 107 | #define SPIBSC_SMCMR_OCMD (0x000000FFuL)
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| 108 |
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| 109 | #define SPIBSC_SMCMR_CMD (0x00FF0000uL)
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| 110 |
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| 111 | #define SPIBSC_SMADR_ADR (0xFFFFFFFFuL)
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| 112 |
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| 113 | #define SPIBSC_SMOPR_OPD0 (0x000000FFuL)
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| 114 | #define SPIBSC_SMOPR_OPD1 (0x0000FF00uL)
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| 115 | #define SPIBSC_SMOPR_OPD2 (0x00FF0000uL)
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| 116 | #define SPIBSC_SMOPR_OPD3 (0xFF000000uL)
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| 117 |
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| 118 | #define SPIBSC_SMENR_SPIDE (0x0000000FuL)
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| 119 | #define SPIBSC_SMENR_OPDE (0x000000F0uL)
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| 120 | #define SPIBSC_SMENR_ADE (0x00000F00uL)
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| 121 | #define SPIBSC_SMENR_OCDE (0x00001000uL)
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| 122 |
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| 123 | #define SPIBSC_SMENR_CDE (0x00004000uL)
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| 124 | #define SPIBSC_SMENR_DME (0x00008000uL)
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| 125 | #define SPIBSC_SMENR_SPIDB (0x00030000uL)
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| 126 |
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| 127 | #define SPIBSC_SMENR_OPDB (0x00300000uL)
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| 128 |
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| 129 | #define SPIBSC_SMENR_ADB (0x03000000uL)
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| 130 |
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| 131 | #define SPIBSC_SMENR_OCDB (0x30000000uL)
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| 132 | #define SPIBSC_SMENR_CDB (0xC0000000uL)
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| 133 |
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| 134 | #define SPIBSC_SMRDR0_RDATA0 (0xFFFFFFFFuL)
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| 135 | #define SPIBSC_SMRDR1_RDATA1 (0xFFFFFFFFuL)
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| 136 | #define SPIBSC_SMWDR0_WDATA0 (0xFFFFFFFFuL)
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| 137 | #define SPIBSC_SMWDR1_WDATA1 (0xFFFFFFFFuL)
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| 138 |
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| 139 | #define SPIBSC_CMNSR_TEND (0x00000001uL)
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| 140 | #define SPIBSC_CMNSR_SSLF (0x00000002uL)
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| 141 |
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| 142 | #define SPIBSC_DRDMCR_DMCYC (0x00000007uL)
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| 143 |
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| 144 | #define SPIBSC_DRDMCR_DMDB (0x00030000uL)
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| 145 |
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| 146 | #define SPIBSC_DRDRENR_DRDRE (0x00000001uL)
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| 147 |
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| 148 | #define SPIBSC_DRDRENR_OPDRE (0x00000010uL)
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| 149 |
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| 150 | #define SPIBSC_DRDRENR_ADDRE (0x00000100uL)
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| 151 |
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| 152 | #define SPIBSC_SMDMCR_DMCYC (0x00000007uL)
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| 153 |
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| 154 | #define SPIBSC_SMDMCR_DMDB (0x00030000uL)
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| 155 |
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| 156 | #define SPIBSC_SMDRENR_SPIDRE (0x00000001uL)
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| 157 |
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| 158 | #define SPIBSC_SMDRENR_OPDRE (0x00000010uL)
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| 159 |
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| 160 | #define SPIBSC_SMDRENR_ADDRE (0x00000100uL)
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| 161 |
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| 162 | /* Shift parameter */
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| 163 | #define SPIBSC_CMNCR_BSZ_SHIFT (0u)
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| 164 |
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| 165 | #define SPIBSC_CMNCR_CPOL_SHIFT (3u)
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| 166 | #define SPIBSC_CMNCR_SSLP_SHIFT (4u)
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| 167 | #define SPIBSC_CMNCR_CPHAR_SHIFT (5u)
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| 168 | #define SPIBSC_CMNCR_CPHAT_SHIFT (6u)
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| 169 |
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| 170 | #define SPIBSC_CMNCR_IO0FV_SHIFT (8u)
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| 171 |
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| 172 | #define SPIBSC_CMNCR_IO2FV_SHIFT (12u)
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| 173 | #define SPIBSC_CMNCR_IO3FV_SHIFT (14u)
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| 174 | #define SPIBSC_CMNCR_MOIIO0_SHIFT (16u)
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| 175 | #define SPIBSC_CMNCR_MOIIO1_SHIFT (18u)
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| 176 | #define SPIBSC_CMNCR_MOIIO2_SHIFT (20u)
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| 177 | #define SPIBSC_CMNCR_MOIIO3_SHIFT (22u)
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| 178 | #define SPIBSC_CMNCR_SFDE_SHIFT (24u)
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| 179 |
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| 180 | #define SPIBSC_CMNCR_MD_SHIFT (31u)
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| 181 |
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| 182 | #define SPIBSC_SSLDR_SCKDL_SHIFT (0u)
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| 183 |
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| 184 | #define SPIBSC_SSLDR_SLNDL_SHIFT (8u)
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| 185 |
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| 186 | #define SPIBSC_SSLDR_SPNDL_SHIFT (16u)
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| 187 |
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| 188 | #define SPIBSC_SPBCR_BRDV_SHIFT (0u)
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| 189 |
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| 190 | #define SPIBSC_SPBCR_SPBR_SHIFT (8u)
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| 191 |
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| 192 | #define SPIBSC_DRCR_SSLE_SHIFT (0u)
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| 193 |
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| 194 | #define SPIBSC_DRCR_RBE_SHIFT (8u)
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| 195 | #define SPIBSC_DRCR_RCF_SHIFT (9u)
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| 196 |
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| 197 | #define SPIBSC_DRCR_RBURST_SHIFT (16u)
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| 198 |
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| 199 | #define SPIBSC_DRCR_SSLN_SHIFT (24u)
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| 200 |
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| 201 | #define SPIBSC_DRCMR_OCMD_SHIFT (0u)
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| 202 |
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| 203 | #define SPIBSC_DRCMR_CMD_SHIFT (16u)
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| 204 |
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| 205 | #define SPIBSC_DREAR_EAC_SHIFT (0u)
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| 206 |
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| 207 | #define SPIBSC_DREAR_EAV_SHIFT (16u)
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| 208 |
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| 209 | #define SPIBSC_DROPR_OPD0_SHIFT (0u)
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| 210 | #define SPIBSC_DROPR_OPD1_SHIFT (8u)
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| 211 | #define SPIBSC_DROPR_OPD2_SHIFT (16u)
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| 212 | #define SPIBSC_DROPR_OPD3_SHIFT (24u)
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| 213 |
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| 214 | #define SPIBSC_DRENR_OPDE_SHIFT (4u)
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| 215 | #define SPIBSC_DRENR_ADE_SHIFT (8u)
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| 216 | #define SPIBSC_DRENR_OCDE_SHIFT (12u)
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| 217 |
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| 218 | #define SPIBSC_DRENR_CDE_SHIFT (14u)
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| 219 | #define SPIBSC_DRENR_DME_SHIFT (15u)
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| 220 | #define SPIBSC_DRENR_DRDB_SHIFT (16u)
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| 221 |
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| 222 | #define SPIBSC_DRENR_OPDB_SHIFT (20u)
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| 223 |
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| 224 | #define SPIBSC_DRENR_ADB_SHIFT (24u)
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| 225 |
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| 226 | #define SPIBSC_DRENR_OCDB_SHIFT (28u)
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| 227 | #define SPIBSC_DRENR_CDB_SHIFT (30u)
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| 228 |
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| 229 | #define SPIBSC_SMCR_SPIE_SHIFT (0u)
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| 230 | #define SPIBSC_SMCR_SPIWE_SHIFT (1u)
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| 231 | #define SPIBSC_SMCR_SPIRE_SHIFT (2u)
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| 232 |
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| 233 | #define SPIBSC_SMCR_SSLKP_SHIFT (8u)
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| 234 |
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| 235 | #define SPIBSC_SMCMR_OCMD_SHIFT (0u)
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| 236 |
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| 237 | #define SPIBSC_SMCMR_CMD_SHIFT (16u)
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| 238 |
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| 239 | #define SPIBSC_SMADR_ADR_SHIFT (0u)
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| 240 |
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| 241 | #define SPIBSC_SMOPR_OPD0_SHIFT (0u)
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| 242 | #define SPIBSC_SMOPR_OPD1_SHIFT (8u)
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| 243 | #define SPIBSC_SMOPR_OPD2_SHIFT (16u)
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| 244 | #define SPIBSC_SMOPR_OPD3_SHIFT (24u)
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| 245 |
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| 246 | #define SPIBSC_SMENR_SPIDE_SHIFT (0u)
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| 247 | #define SPIBSC_SMENR_OPDE_SHIFT (4u)
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| 248 | #define SPIBSC_SMENR_ADE_SHIFT (8u)
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| 249 | #define SPIBSC_SMENR_OCDE_SHIFT (12u)
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| 250 |
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| 251 | #define SPIBSC_SMENR_CDE_SHIFT (14u)
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| 252 | #define SPIBSC_SMENR_DME_SHIFT (15u)
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| 253 | #define SPIBSC_SMENR_SPIDB_SHIFT (16u)
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| 254 |
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| 255 | #define SPIBSC_SMENR_OPDB_SHIFT (20u)
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| 256 |
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| 257 | #define SPIBSC_SMENR_ADB_SHIFT (24u)
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| 258 |
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| 259 | #define SPIBSC_SMENR_OCDB_SHIFT (28u)
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| 260 | #define SPIBSC_SMENR_CDB_SHIFT (30u)
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| 261 |
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| 262 | #define SPIBSC_SMRDR0_RDATA0_SHIFT (0u)
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| 263 | #define SPIBSC_SMRDR1_RDATA1_SHIFT (0u)
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| 264 | #define SPIBSC_SMWDR0_WDATA0_SHIFT (0u)
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| 265 | #define SPIBSC_SMWDR1_WDATA1_SHIFT (0u)
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| 266 |
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| 267 | #define SPIBSC_CMNSR_TEND_SHIFT (0u)
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| 268 | #define SPIBSC_CMNSR_SSLF_SHIFT (1u)
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| 269 |
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| 270 | #define SPIBSC_DRDMCR_DMCYC_SHIFT (0u)
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| 271 |
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| 272 | #define SPIBSC_DRDMCR_DMDB_SHIFT (16u)
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| 273 |
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| 274 | #define SPIBSC_DRDRENR_DRDRE_SHIFT (0u)
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| 275 |
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| 276 | #define SPIBSC_DRDRENR_OPDRE_SHIFT (4u)
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| 277 |
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| 278 | #define SPIBSC_DRDRENR_ADDRE_SHIFT (8u)
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| 279 |
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| 280 | #define SPIBSC_SMDMCR_DMCYC_SHIFT (0u)
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| 281 |
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| 282 | #define SPIBSC_SMDMCR_DMDB_SHIFT (16u)
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| 283 |
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| 284 | #define SPIBSC_SMDRENR_SPIDRE_SHIFT (0u)
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| 285 |
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| 286 | #define SPIBSC_SMDRENR_OPDRE_SHIFT (4u)
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| 287 |
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| 288 | #define SPIBSC_SMDRENR_ADDRE_SHIFT (8u)
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| 289 |
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| 290 | #endif /* SPIBSC_IOBITMASK_H */
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| 291 |
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| 292 | /* End of File */
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