source: asp3_tinet_ecnl_arm/trunk/asp3_dcre/mbed/targets/TARGET_RENESAS/TARGET_RZA1XX/TARGET_RZ_A1H/device/TOOLCHAIN_GCC_ARM/startup_RZ1AH.S

Last change on this file was 374, checked in by coas-nagasima, 5 years ago

mbed関連を更新
シリアルドライバをmbedのHALを使うよう変更
ファイルディスクリプタの処理を更新
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1/* File: startup_ARMCM3.s
2 * Purpose: startup file for Cortex-M3/M4 devices. Should use with
3 * GNU Tools for ARM Embedded Processors
4 * Version: V1.1
5 * Date: 17 June 2011
6 *
7 * Copyright (C) 2011 ARM Limited. All rights reserved.
8 * ARM Limited (ARM) is supplying this software for use with Cortex-M3/M4
9 * processor based microcontrollers. This file can be freely distributed
10 * within development tools that are supporting such ARM based processors.
11 *
12 * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
13 * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
14 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
15 * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
16 * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
17 */
18 .syntax unified
19 .extern _start
20
21@ Standard definitions of mode bits and interrupt (I & F) flags in PSRs
22 .equ Mode_USR , 0x10
23 .equ Mode_FIQ , 0x11
24 .equ Mode_IRQ , 0x12
25 .equ Mode_SVC , 0x13
26 .equ Mode_ABT , 0x17
27 .equ Mode_UND , 0x1B
28 .equ Mode_SYS , 0x1F
29
30 .equ I_Bit , 0x80 @ when I bit is set, IRQ is disabled
31 .equ F_Bit , 0x40 @ when F bit is set, FIQ is disabled
32 .equ T_Bit , 0x20 @ when T bit is set, core is in Thumb state
33
34@ Stack Configuration
35
36 .EQU UND_Stack_Size , 0x00000100
37 .EQU SVC_Stack_Size , 0x00008000
38 .EQU ABT_Stack_Size , 0x00000100
39 .EQU FIQ_Stack_Size , 0x00000100
40 .EQU IRQ_Stack_Size , 0x00008000
41 .EQU USR_Stack_Size , 0x00004000
42
43 .EQU ISR_Stack_Size, (UND_Stack_Size + SVC_Stack_Size + ABT_Stack_Size + FIQ_Stack_Size + IRQ_Stack_Size)
44
45 .section .stack
46 .align 3
47 .globl __StackTop
48 .globl __StackLimit
49__StackLimit:
50 .space ISR_Stack_Size
51__initial_sp:
52 .space USR_Stack_Size
53 .size __StackLimit, . - __StackLimit
54__StackTop:
55 .size __StackTop, . - __StackTop
56
57
58@ Heap Configuration
59
60 .EQU Heap_Size , 0x00080000
61
62 .section .heap
63 .align 3
64 .globl __HeapBase
65 .globl __HeapLimit
66__HeapBase:
67 .space Heap_Size
68 .size __HeapBase, . - __HeapBase
69__HeapLimit:
70 .size __HeapLimit, . - __HeapLimit
71
72
73 .section .isr_vector
74 .align 2
75 .globl __isr_vector
76__isr_vector:
77 .long 0xe59ff018 /* 0x00 */
78 .long 0xe59ff018 /* 0x04 */
79 .long 0xe59ff018 /* 0x08 */
80 .long 0xe59ff018 /* 0x0c */
81 .long 0xe59ff018 /* 0x10 */
82 .long 0xe59ff018 /* 0x14 */
83 .long 0xe59ff018 /* 0x18 */
84 .long 0xe59ff018 /* 0x1c */
85
86 .long Reset_Handler /* 0x20 */
87 .long _kernel_undef_handler /* 0x24 */
88 .long _kernel_svc_handler /* 0x28 */
89 .long _kernel_pabort_handler /* 0x2c */
90 .long _kernel_dabort_handler /* 0x30 */
91 .long 0 /* Reserved */
92 .long _kernel_irq_handler /* IRQ */
93 .long _kernel_fiq_handler /* FIQ */
94
95
96 .size __isr_vector, . - __isr_vector
97
98 .text
99 .align 2
100 .globl Reset_Handler
101 .type Reset_Handler, %function
102Reset_Handler:
103 @ Mask interrupts
104 CPSID if
105
106 @ Put any cores other than 0 to sleep
107 mrc p15, 0, r0, c0, c0, 5 @ Read MPIDR
108 ands r0, r0, #3
109goToSleep:
110 wfine
111 bne goToSleep
112
113 @ Reset SCTLR Settings
114 mrc p15, 0, r0, c1, c0, 0 @ Read CP15 System Control register
115 bic r0, r0, #(0x1 << 12) @ Clear I bit 12 to disable I Cache
116 bic r0, r0, #(0x1 << 2) @ Clear C bit 2 to disable D Cache
117 bic r0, r0, #0x1 @ Clear M bit 0 to disable MMU
118 bic r0, r0, #(0x1 << 11) @ Clear Z bit 11 to disable branch prediction
119 bic r0, r0, #(0x1 << 13) @ Clear V bit 13 to disable hivecs
120 mcr p15, 0, r0, c1, c0, 0 @ Write value back to CP15 System Control register
121 isb
122
123 @ Configure ACTLR
124 MRC p15, 0, r0, c1, c0, 1 @ Read CP15 Auxiliary Control Register
125 ORR r0, r0, #(1 << 1) @ Enable L2 prefetch hint (UNK/WI since r4p1)
126 MCR p15, 0, r0, c1, c0, 1 @ Write CP15 Auxiliary Control Register
127
128@ Set Vector Base Address Register (VBAR) to point to this application's vector table
129 ldr r0, =__isr_vector
130 mcr p15, 0, r0, c12, c0, 0
131
132@ Setup Stack for each exceptional mode
133/* ldr r0, =__StackTop */
134 ldr r0, =(__StackTop - USR_Stack_Size)
135
136@ Enter Undefined Instruction Mode and set its Stack Pointer
137 msr cpsr_c, #(Mode_UND | I_Bit | F_Bit)
138 mov sp, r0
139 sub r0, r0, #UND_Stack_Size
140
141@ Enter Abort Mode and set its Stack Pointer
142 msr cpsr_c, #(Mode_ABT | I_Bit | F_Bit)
143 mov sp, r0
144 sub r0, r0, #ABT_Stack_Size
145
146@ Enter FIQ Mode and set its Stack Pointer
147 msr cpsr_c, #(Mode_FIQ | I_Bit | F_Bit)
148 mov sp, r0
149 sub r0, r0, #FIQ_Stack_Size
150
151@ Enter IRQ Mode and set its Stack Pointer
152 msr cpsr_c, #(Mode_IRQ | I_Bit | F_Bit)
153 mov sp, r0
154 sub r0, r0, #IRQ_Stack_Size
155
156@ Enter Supervisor Mode and set its Stack Pointer
157 msr cpsr_c, #(Mode_SVC | I_Bit | F_Bit)
158 mov sp, r0
159 sub r0, r0, #SVC_Stack_Size
160
161@ Enter System Mode to complete initialization and enter kernel
162 msr cpsr_c, #(Mode_SYS | I_Bit | F_Bit)
163 mov sp, r0
164
165@ USR/SYS stack pointer will be set during kernel init
166 ldr r0, =SystemInit
167 blx r0
168
169 @ Unmask interrupts
170 CPSIE if
171
172@ data sections copy
173 ldr r4, =__copy_table_start__
174 ldr r5, =__copy_table_end__
175
176.L_loop0:
177 cmp r4, r5
178 bge .L_loop0_done
179 ldr r1, [r4]
180 ldr r2, [r4, #4]
181 ldr r3, [r4, #8]
182
183.L_loop0_0:
184 subs r3, #4
185 ittt ge
186 ldrge r0, [r1, r3]
187 strge r0, [r2, r3]
188 bge .L_loop0_0
189
190 adds r4, #12
191 b .L_loop0
192
193.L_loop0_done:
194
195@ bss sections clear
196 ldr r3, =__zero_table_start__
197 ldr r4, =__zero_table_end__
198
199.L_loop2:
200 cmp r3, r4
201 bge .L_loop2_done
202 ldr r1, [r3]
203 ldr r2, [r3, #4]
204 movs r0, 0
205
206.L_loop2_0:
207 subs r2, #4
208 itt ge
209 strge r0, [r1, r2]
210 bge .L_loop2_0
211
212 adds r3, #8
213 b .L_loop2
214.L_loop2_done:
215
216
217 ldr r0, =_start
218 bx r0
219
220 ldr r0, sf_boot @ dummy to keep boot loader area
221loop_here:
222 b loop_here
223
224sf_boot:
225 .word boot_loader
226
227 .pool
228 .size Reset_Handler, . - Reset_Handler
229
230
231 .text
232
233/* Macro to define default handlers. Default handler
234 * will be weak symbol and just dead loops. They can be
235 * overwritten by other handlers */
236 .macro def_default_handler handler_name
237 .align 1
238 .thumb_func
239 .weak \handler_name
240 .type \handler_name, %function
241\handler_name :
242 b .
243 .size \handler_name, . - \handler_name
244 .endm
245
246 def_default_handler Undef_Handler
247 def_default_handler SVC_Handler
248 def_default_handler PAbt_Handler
249 def_default_handler DAbt_Handler
250 def_default_handler IRQ_Handler
251 def_default_handler FIQ_Handler
252
253 .END
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