[352] | 1 | /**************************************************************************//**
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| 2 | * @file core_cmInstr.h
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| 3 | * @brief CMSIS Cortex-M Core Instruction Access Header File
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| 4 | * @version V4.10
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| 5 | * @date 18. March 2015
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| 6 | *
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| 7 | * @note
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| 8 | *
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| 9 | ******************************************************************************/
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| 10 | /* Copyright (c) 2009 - 2014 ARM LIMITED
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| 11 |
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| 12 | All rights reserved.
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| 13 | Redistribution and use in source and binary forms, with or without
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| 14 | modification, are permitted provided that the following conditions are met:
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| 15 | - Redistributions of source code must retain the above copyright
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| 16 | notice, this list of conditions and the following disclaimer.
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| 17 | - Redistributions in binary form must reproduce the above copyright
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| 18 | notice, this list of conditions and the following disclaimer in the
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| 19 | documentation and/or other materials provided with the distribution.
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| 20 | - Neither the name of ARM nor the names of its contributors may be used
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| 21 | to endorse or promote products derived from this software without
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| 22 | specific prior written permission.
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| 23 | *
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| 24 | THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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| 25 | AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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| 26 | IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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| 27 | ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
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| 28 | LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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| 29 | CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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| 30 | SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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| 31 | INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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| 32 | CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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| 33 | ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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| 34 | POSSIBILITY OF SUCH DAMAGE.
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| 35 | ---------------------------------------------------------------------------*/
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| 36 |
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| 37 |
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| 38 | #ifndef __CORE_CMINSTR_H
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| 39 | #define __CORE_CMINSTR_H
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| 40 |
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| 41 |
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| 42 | /* ########################## Core Instruction Access ######################### */
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| 43 | /** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface
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| 44 | Access to dedicated instructions
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| 45 | @{
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| 46 | */
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| 47 |
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| 48 | #if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/
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| 49 | /* ARM armcc specific functions */
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| 50 |
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| 51 | #if (__ARMCC_VERSION < 400677)
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| 52 | #error "Please use ARM Compiler Toolchain V4.0.677 or later!"
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| 53 | #endif
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| 54 |
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| 55 |
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| 56 | /** \brief No Operation
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| 57 |
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| 58 | No Operation does nothing. This instruction can be used for code alignment purposes.
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| 59 | */
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| 60 | #define __NOP __nop
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| 61 |
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| 62 |
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| 63 | /** \brief Wait For Interrupt
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| 64 |
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| 65 | Wait For Interrupt is a hint instruction that suspends execution
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| 66 | until one of a number of events occurs.
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| 67 | */
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| 68 | #define __WFI __wfi
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| 69 |
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| 70 |
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| 71 | /** \brief Wait For Event
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| 72 |
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| 73 | Wait For Event is a hint instruction that permits the processor to enter
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| 74 | a low-power state until one of a number of events occurs.
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| 75 | */
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| 76 | #define __WFE __wfe
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| 77 |
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| 78 |
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| 79 | /** \brief Send Event
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| 80 |
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| 81 | Send Event is a hint instruction. It causes an event to be signaled to the CPU.
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| 82 | */
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| 83 | #define __SEV __sev
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| 84 |
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| 85 |
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| 86 | /** \brief Instruction Synchronization Barrier
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| 87 |
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| 88 | Instruction Synchronization Barrier flushes the pipeline in the processor,
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| 89 | so that all instructions following the ISB are fetched from cache or
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| 90 | memory, after the instruction has been completed.
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| 91 | */
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| 92 | #define __ISB() do {\
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| 93 | __schedule_barrier();\
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| 94 | __isb(0xF);\
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| 95 | __schedule_barrier();\
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| 96 | } while (0)
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| 97 |
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| 98 | /** \brief Data Synchronization Barrier
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| 99 |
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| 100 | This function acts as a special kind of Data Memory Barrier.
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| 101 | It completes when all explicit memory accesses before this instruction complete.
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| 102 | */
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| 103 | #define __DSB() do {\
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| 104 | __schedule_barrier();\
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| 105 | __dsb(0xF);\
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| 106 | __schedule_barrier();\
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| 107 | } while (0)
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| 108 |
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| 109 | /** \brief Data Memory Barrier
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| 110 |
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| 111 | This function ensures the apparent order of the explicit memory operations before
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| 112 | and after the instruction, without ensuring their completion.
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| 113 | */
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| 114 | #define __DMB() do {\
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| 115 | __schedule_barrier();\
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| 116 | __dmb(0xF);\
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| 117 | __schedule_barrier();\
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| 118 | } while (0)
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| 119 |
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| 120 | /** \brief Reverse byte order (32 bit)
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| 121 |
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| 122 | This function reverses the byte order in integer value.
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| 123 |
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| 124 | \param [in] value Value to reverse
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| 125 | \return Reversed value
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| 126 | */
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| 127 | #define __REV __rev
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| 128 |
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| 129 |
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| 130 | /** \brief Reverse byte order (16 bit)
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| 131 |
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| 132 | This function reverses the byte order in two unsigned short values.
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| 133 |
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| 134 | \param [in] value Value to reverse
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| 135 | \return Reversed value
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| 136 | */
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| 137 | #ifndef __NO_EMBEDDED_ASM
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| 138 | __attribute__((section(".rev16_text"))) __STATIC_INLINE __ASM uint32_t __REV16(uint32_t value)
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| 139 | {
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| 140 | rev16 r0, r0
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| 141 | bx lr
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| 142 | }
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| 143 | #endif
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| 144 |
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| 145 | /** \brief Reverse byte order in signed short value
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| 146 |
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| 147 | This function reverses the byte order in a signed short value with sign extension to integer.
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| 148 |
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| 149 | \param [in] value Value to reverse
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| 150 | \return Reversed value
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| 151 | */
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| 152 | #ifndef __NO_EMBEDDED_ASM
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| 153 | __attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int32_t __REVSH(int32_t value)
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| 154 | {
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| 155 | revsh r0, r0
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| 156 | bx lr
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| 157 | }
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| 158 | #endif
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| 159 |
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| 160 |
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| 161 | /** \brief Rotate Right in unsigned value (32 bit)
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| 162 |
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| 163 | This function Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.
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| 164 |
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| 165 | \param [in] value Value to rotate
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| 166 | \param [in] value Number of Bits to rotate
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| 167 | \return Rotated value
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| 168 | */
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| 169 | #define __ROR __ror
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| 170 |
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| 171 |
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| 172 | /** \brief Breakpoint
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| 173 |
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| 174 | This function causes the processor to enter Debug state.
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| 175 | Debug tools can use this to investigate system state when the instruction at a particular address is reached.
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| 176 |
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| 177 | \param [in] value is ignored by the processor.
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| 178 | If required, a debugger can use it to store additional information about the breakpoint.
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| 179 | */
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| 180 | #define __BKPT(value) __breakpoint(value)
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| 181 |
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| 182 |
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| 183 | /** \brief Reverse bit order of value
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| 184 |
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| 185 | This function reverses the bit order of the given value.
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| 186 |
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| 187 | \param [in] value Value to reverse
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| 188 | \return Reversed value
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| 189 | */
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| 190 | #if (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300)
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| 191 | #define __RBIT __rbit
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| 192 | #else
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| 193 | __attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value)
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| 194 | {
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| 195 | uint32_t result;
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| 196 | int32_t s = 4 /*sizeof(v)*/ * 8 - 1; // extra shift needed at end
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| 197 |
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| 198 | result = value; // r will be reversed bits of v; first get LSB of v
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| 199 | for (value >>= 1; value; value >>= 1)
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| 200 | {
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| 201 | result <<= 1;
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| 202 | result |= value & 1;
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| 203 | s--;
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| 204 | }
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| 205 | result <<= s; // shift when v's highest bits are zero
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| 206 | return(result);
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| 207 | }
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| 208 | #endif
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| 209 |
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| 210 |
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| 211 | /** \brief Count leading zeros
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| 212 |
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| 213 | This function counts the number of leading zeros of a data value.
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| 214 |
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| 215 | \param [in] value Value to count the leading zeros
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| 216 | \return number of leading zeros in value
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| 217 | */
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| 218 | #define __CLZ __clz
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| 219 |
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| 220 |
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| 221 | #if (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300)
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| 222 |
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| 223 | /** \brief LDR Exclusive (8 bit)
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| 224 |
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| 225 | This function executes a exclusive LDR instruction for 8 bit value.
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| 226 |
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| 227 | \param [in] ptr Pointer to data
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| 228 | \return value of type uint8_t at (*ptr)
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| 229 | */
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| 230 | #define __LDREXB(ptr) ((uint8_t ) __ldrex(ptr))
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| 231 |
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| 232 |
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| 233 | /** \brief LDR Exclusive (16 bit)
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| 234 |
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| 235 | This function executes a exclusive LDR instruction for 16 bit values.
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| 236 |
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| 237 | \param [in] ptr Pointer to data
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| 238 | \return value of type uint16_t at (*ptr)
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| 239 | */
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| 240 | #define __LDREXH(ptr) ((uint16_t) __ldrex(ptr))
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| 241 |
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| 242 |
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| 243 | /** \brief LDR Exclusive (32 bit)
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| 244 |
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| 245 | This function executes a exclusive LDR instruction for 32 bit values.
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| 246 |
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| 247 | \param [in] ptr Pointer to data
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| 248 | \return value of type uint32_t at (*ptr)
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| 249 | */
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| 250 | #define __LDREXW(ptr) ((uint32_t ) __ldrex(ptr))
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| 251 |
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| 252 |
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| 253 | /** \brief STR Exclusive (8 bit)
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| 254 |
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| 255 | This function executes a exclusive STR instruction for 8 bit values.
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| 256 |
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| 257 | \param [in] value Value to store
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| 258 | \param [in] ptr Pointer to location
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| 259 | \return 0 Function succeeded
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| 260 | \return 1 Function failed
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| 261 | */
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| 262 | #define __STREXB(value, ptr) __strex(value, ptr)
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| 263 |
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| 264 |
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| 265 | /** \brief STR Exclusive (16 bit)
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| 266 |
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| 267 | This function executes a exclusive STR instruction for 16 bit values.
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| 268 |
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| 269 | \param [in] value Value to store
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| 270 | \param [in] ptr Pointer to location
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| 271 | \return 0 Function succeeded
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| 272 | \return 1 Function failed
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| 273 | */
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| 274 | #define __STREXH(value, ptr) __strex(value, ptr)
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| 275 |
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| 276 |
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| 277 | /** \brief STR Exclusive (32 bit)
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| 278 |
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| 279 | This function executes a exclusive STR instruction for 32 bit values.
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| 280 |
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| 281 | \param [in] value Value to store
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| 282 | \param [in] ptr Pointer to location
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| 283 | \return 0 Function succeeded
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| 284 | \return 1 Function failed
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| 285 | */
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| 286 | #define __STREXW(value, ptr) __strex(value, ptr)
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| 287 |
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| 288 |
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| 289 | /** \brief Remove the exclusive lock
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| 290 |
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| 291 | This function removes the exclusive lock which is created by LDREX.
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| 292 |
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| 293 | */
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| 294 | #define __CLREX __clrex
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| 295 |
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| 296 |
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| 297 | /** \brief Signed Saturate
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| 298 |
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| 299 | This function saturates a signed value.
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| 300 |
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| 301 | \param [in] value Value to be saturated
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| 302 | \param [in] sat Bit position to saturate to (1..32)
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| 303 | \return Saturated value
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| 304 | */
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| 305 | #define __SSAT __ssat
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| 306 |
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| 307 |
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| 308 | /** \brief Unsigned Saturate
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| 309 |
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| 310 | This function saturates an unsigned value.
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| 311 |
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| 312 | \param [in] value Value to be saturated
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| 313 | \param [in] sat Bit position to saturate to (0..31)
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| 314 | \return Saturated value
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| 315 | */
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| 316 | #define __USAT __usat
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| 317 |
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| 318 |
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| 319 | /** \brief Rotate Right with Extend (32 bit)
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| 320 |
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| 321 | This function moves each bit of a bitstring right by one bit.
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| 322 | The carry input is shifted in at the left end of the bitstring.
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| 323 |
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| 324 | \param [in] value Value to rotate
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| 325 | \return Rotated value
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| 326 | */
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| 327 | #ifndef __NO_EMBEDDED_ASM
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| 328 | __attribute__((section(".rrx_text"))) __STATIC_INLINE __ASM uint32_t __RRX(uint32_t value)
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| 329 | {
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| 330 | rrx r0, r0
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| 331 | bx lr
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| 332 | }
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| 333 | #endif
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| 334 |
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| 335 |
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| 336 | /** \brief LDRT Unprivileged (8 bit)
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| 337 |
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| 338 | This function executes a Unprivileged LDRT instruction for 8 bit value.
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| 339 |
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| 340 | \param [in] ptr Pointer to data
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| 341 | \return value of type uint8_t at (*ptr)
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| 342 | */
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| 343 | #define __LDRBT(ptr) ((uint8_t ) __ldrt(ptr))
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| 344 |
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| 345 |
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| 346 | /** \brief LDRT Unprivileged (16 bit)
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| 347 |
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| 348 | This function executes a Unprivileged LDRT instruction for 16 bit values.
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| 349 |
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| 350 | \param [in] ptr Pointer to data
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| 351 | \return value of type uint16_t at (*ptr)
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| 352 | */
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| 353 | #define __LDRHT(ptr) ((uint16_t) __ldrt(ptr))
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| 354 |
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| 355 |
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| 356 | /** \brief LDRT Unprivileged (32 bit)
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| 357 |
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| 358 | This function executes a Unprivileged LDRT instruction for 32 bit values.
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| 359 |
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| 360 | \param [in] ptr Pointer to data
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| 361 | \return value of type uint32_t at (*ptr)
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| 362 | */
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| 363 | #define __LDRT(ptr) ((uint32_t ) __ldrt(ptr))
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| 364 |
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| 365 |
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| 366 | /** \brief STRT Unprivileged (8 bit)
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| 367 |
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| 368 | This function executes a Unprivileged STRT instruction for 8 bit values.
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| 369 |
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| 370 | \param [in] value Value to store
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| 371 | \param [in] ptr Pointer to location
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| 372 | */
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| 373 | #define __STRBT(value, ptr) __strt(value, ptr)
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| 374 |
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| 375 |
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| 376 | /** \brief STRT Unprivileged (16 bit)
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| 377 |
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| 378 | This function executes a Unprivileged STRT instruction for 16 bit values.
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| 379 |
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| 380 | \param [in] value Value to store
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| 381 | \param [in] ptr Pointer to location
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| 382 | */
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| 383 | #define __STRHT(value, ptr) __strt(value, ptr)
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| 384 |
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| 385 |
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| 386 | /** \brief STRT Unprivileged (32 bit)
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| 387 |
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| 388 | This function executes a Unprivileged STRT instruction for 32 bit values.
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| 389 |
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| 390 | \param [in] value Value to store
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| 391 | \param [in] ptr Pointer to location
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| 392 | */
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| 393 | #define __STRT(value, ptr) __strt(value, ptr)
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| 394 |
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| 395 | #endif /* (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300) */
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| 396 |
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| 397 |
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| 398 | #elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/
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| 399 | /* GNU gcc specific functions */
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| 400 |
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| 401 | /* Define macros for porting to both thumb1 and thumb2.
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| 402 | * For thumb1, use low register (r0-r7), specified by constrant "l"
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| 403 | * Otherwise, use general registers, specified by constrant "r" */
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| 404 | #if defined (__thumb__) && !defined (__thumb2__)
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| 405 | #define __CMSIS_GCC_OUT_REG(r) "=l" (r)
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| 406 | #define __CMSIS_GCC_USE_REG(r) "l" (r)
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| 407 | #else
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| 408 | #define __CMSIS_GCC_OUT_REG(r) "=r" (r)
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| 409 | #define __CMSIS_GCC_USE_REG(r) "r" (r)
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| 410 | #endif
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| 411 |
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| 412 | /** \brief No Operation
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| 413 |
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| 414 | No Operation does nothing. This instruction can be used for code alignment purposes.
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| 415 | */
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| 416 | __attribute__((always_inline)) __STATIC_INLINE void __NOP(void)
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| 417 | {
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| 418 | __ASM volatile ("nop");
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| 419 | }
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| 420 |
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| 421 |
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| 422 | /** \brief Wait For Interrupt
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| 423 |
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| 424 | Wait For Interrupt is a hint instruction that suspends execution
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| 425 | until one of a number of events occurs.
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| 426 | */
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| 427 | __attribute__((always_inline)) __STATIC_INLINE void __WFI(void)
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| 428 | {
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| 429 | __ASM volatile ("wfi");
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| 430 | }
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| 431 |
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| 432 |
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| 433 | /** \brief Wait For Event
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| 434 |
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| 435 | Wait For Event is a hint instruction that permits the processor to enter
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| 436 | a low-power state until one of a number of events occurs.
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| 437 | */
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| 438 | __attribute__((always_inline)) __STATIC_INLINE void __WFE(void)
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| 439 | {
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| 440 | __ASM volatile ("wfe");
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| 441 | }
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| 442 |
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| 443 |
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| 444 | /** \brief Send Event
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| 445 |
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| 446 | Send Event is a hint instruction. It causes an event to be signaled to the CPU.
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| 447 | */
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| 448 | __attribute__((always_inline)) __STATIC_INLINE void __SEV(void)
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| 449 | {
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| 450 | __ASM volatile ("sev");
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| 451 | }
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| 452 |
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| 453 |
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| 454 | /** \brief Instruction Synchronization Barrier
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| 455 |
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| 456 | Instruction Synchronization Barrier flushes the pipeline in the processor,
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| 457 | so that all instructions following the ISB are fetched from cache or
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| 458 | memory, after the instruction has been completed.
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| 459 | */
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| 460 | __attribute__((always_inline)) __STATIC_INLINE void __ISB(void)
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| 461 | {
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| 462 | __ASM volatile ("isb 0xF":::"memory");
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| 463 | }
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| 464 |
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| 465 |
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| 466 | /** \brief Data Synchronization Barrier
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---|
| 467 |
|
---|
| 468 | This function acts as a special kind of Data Memory Barrier.
|
---|
| 469 | It completes when all explicit memory accesses before this instruction complete.
|
---|
| 470 | */
|
---|
| 471 | __attribute__((always_inline)) __STATIC_INLINE void __DSB(void)
|
---|
| 472 | {
|
---|
| 473 | __ASM volatile ("dsb 0xF":::"memory");
|
---|
| 474 | }
|
---|
| 475 |
|
---|
| 476 |
|
---|
| 477 | /** \brief Data Memory Barrier
|
---|
| 478 |
|
---|
| 479 | This function ensures the apparent order of the explicit memory operations before
|
---|
| 480 | and after the instruction, without ensuring their completion.
|
---|
| 481 | */
|
---|
| 482 | __attribute__((always_inline)) __STATIC_INLINE void __DMB(void)
|
---|
| 483 | {
|
---|
| 484 | __ASM volatile ("dmb 0xF":::"memory");
|
---|
| 485 | }
|
---|
| 486 |
|
---|
| 487 |
|
---|
| 488 | /** \brief Reverse byte order (32 bit)
|
---|
| 489 |
|
---|
| 490 | This function reverses the byte order in integer value.
|
---|
| 491 |
|
---|
| 492 | \param [in] value Value to reverse
|
---|
| 493 | \return Reversed value
|
---|
| 494 | */
|
---|
| 495 | __attribute__((always_inline)) __STATIC_INLINE uint32_t __REV(uint32_t value)
|
---|
| 496 | {
|
---|
| 497 | #if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 5)
|
---|
| 498 | return __builtin_bswap32(value);
|
---|
| 499 | #else
|
---|
| 500 | uint32_t result;
|
---|
| 501 |
|
---|
| 502 | __ASM volatile ("rev %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
|
---|
| 503 | return(result);
|
---|
| 504 | #endif
|
---|
| 505 | }
|
---|
| 506 |
|
---|
| 507 |
|
---|
| 508 | /** \brief Reverse byte order (16 bit)
|
---|
| 509 |
|
---|
| 510 | This function reverses the byte order in two unsigned short values.
|
---|
| 511 |
|
---|
| 512 | \param [in] value Value to reverse
|
---|
| 513 | \return Reversed value
|
---|
| 514 | */
|
---|
| 515 | __attribute__((always_inline)) __STATIC_INLINE uint32_t __REV16(uint32_t value)
|
---|
| 516 | {
|
---|
| 517 | uint32_t result;
|
---|
| 518 |
|
---|
| 519 | __ASM volatile ("rev16 %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
|
---|
| 520 | return(result);
|
---|
| 521 | }
|
---|
| 522 |
|
---|
| 523 |
|
---|
| 524 | /** \brief Reverse byte order in signed short value
|
---|
| 525 |
|
---|
| 526 | This function reverses the byte order in a signed short value with sign extension to integer.
|
---|
| 527 |
|
---|
| 528 | \param [in] value Value to reverse
|
---|
| 529 | \return Reversed value
|
---|
| 530 | */
|
---|
| 531 | __attribute__((always_inline)) __STATIC_INLINE int32_t __REVSH(int32_t value)
|
---|
| 532 | {
|
---|
| 533 | #if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
|
---|
| 534 | return (short)__builtin_bswap16(value);
|
---|
| 535 | #else
|
---|
| 536 | uint32_t result;
|
---|
| 537 |
|
---|
| 538 | __ASM volatile ("revsh %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
|
---|
| 539 | return(result);
|
---|
| 540 | #endif
|
---|
| 541 | }
|
---|
| 542 |
|
---|
| 543 |
|
---|
| 544 | /** \brief Rotate Right in unsigned value (32 bit)
|
---|
| 545 |
|
---|
| 546 | This function Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.
|
---|
| 547 |
|
---|
| 548 | \param [in] value Value to rotate
|
---|
| 549 | \param [in] value Number of Bits to rotate
|
---|
| 550 | \return Rotated value
|
---|
| 551 | */
|
---|
| 552 | __attribute__((always_inline)) __STATIC_INLINE uint32_t __ROR(uint32_t op1, uint32_t op2)
|
---|
| 553 | {
|
---|
| 554 | return (op1 >> op2) | (op1 << (32 - op2));
|
---|
| 555 | }
|
---|
| 556 |
|
---|
| 557 |
|
---|
| 558 | /** \brief Breakpoint
|
---|
| 559 |
|
---|
| 560 | This function causes the processor to enter Debug state.
|
---|
| 561 | Debug tools can use this to investigate system state when the instruction at a particular address is reached.
|
---|
| 562 |
|
---|
| 563 | \param [in] value is ignored by the processor.
|
---|
| 564 | If required, a debugger can use it to store additional information about the breakpoint.
|
---|
| 565 | */
|
---|
| 566 | #define __BKPT(value) __ASM volatile ("bkpt "#value)
|
---|
| 567 |
|
---|
| 568 |
|
---|
| 569 | /** \brief Reverse bit order of value
|
---|
| 570 |
|
---|
| 571 | This function reverses the bit order of the given value.
|
---|
| 572 |
|
---|
| 573 | \param [in] value Value to reverse
|
---|
| 574 | \return Reversed value
|
---|
| 575 | */
|
---|
| 576 | __attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value)
|
---|
| 577 | {
|
---|
| 578 | uint32_t result;
|
---|
| 579 |
|
---|
| 580 | #if (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300)
|
---|
| 581 | __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
|
---|
| 582 | #else
|
---|
| 583 | int32_t s = 4 /*sizeof(v)*/ * 8 - 1; // extra shift needed at end
|
---|
| 584 |
|
---|
| 585 | result = value; // r will be reversed bits of v; first get LSB of v
|
---|
| 586 | for (value >>= 1; value; value >>= 1)
|
---|
| 587 | {
|
---|
| 588 | result <<= 1;
|
---|
| 589 | result |= value & 1;
|
---|
| 590 | s--;
|
---|
| 591 | }
|
---|
| 592 | result <<= s; // shift when v's highest bits are zero
|
---|
| 593 | #endif
|
---|
| 594 | return(result);
|
---|
| 595 | }
|
---|
| 596 |
|
---|
| 597 |
|
---|
| 598 | /** \brief Count leading zeros
|
---|
| 599 |
|
---|
| 600 | This function counts the number of leading zeros of a data value.
|
---|
| 601 |
|
---|
| 602 | \param [in] value Value to count the leading zeros
|
---|
| 603 | \return number of leading zeros in value
|
---|
| 604 | */
|
---|
| 605 | #define __CLZ __builtin_clz
|
---|
| 606 |
|
---|
| 607 |
|
---|
| 608 | #if (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300)
|
---|
| 609 |
|
---|
| 610 | /** \brief LDR Exclusive (8 bit)
|
---|
| 611 |
|
---|
| 612 | This function executes a exclusive LDR instruction for 8 bit value.
|
---|
| 613 |
|
---|
| 614 | \param [in] ptr Pointer to data
|
---|
| 615 | \return value of type uint8_t at (*ptr)
|
---|
| 616 | */
|
---|
| 617 | __attribute__((always_inline)) __STATIC_INLINE uint8_t __LDREXB(volatile uint8_t *addr)
|
---|
| 618 | {
|
---|
| 619 | uint32_t result;
|
---|
| 620 |
|
---|
| 621 | #if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
|
---|
| 622 | __ASM volatile ("ldrexb %0, %1" : "=r" (result) : "Q" (*addr) );
|
---|
| 623 | #else
|
---|
| 624 | /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
|
---|
| 625 | accepted by assembler. So has to use following less efficient pattern.
|
---|
| 626 | */
|
---|
| 627 | __ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) : "memory" );
|
---|
| 628 | #endif
|
---|
| 629 | return ((uint8_t) result); /* Add explicit type cast here */
|
---|
| 630 | }
|
---|
| 631 |
|
---|
| 632 |
|
---|
| 633 | /** \brief LDR Exclusive (16 bit)
|
---|
| 634 |
|
---|
| 635 | This function executes a exclusive LDR instruction for 16 bit values.
|
---|
| 636 |
|
---|
| 637 | \param [in] ptr Pointer to data
|
---|
| 638 | \return value of type uint16_t at (*ptr)
|
---|
| 639 | */
|
---|
| 640 | __attribute__((always_inline)) __STATIC_INLINE uint16_t __LDREXH(volatile uint16_t *addr)
|
---|
| 641 | {
|
---|
| 642 | uint32_t result;
|
---|
| 643 |
|
---|
| 644 | #if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
|
---|
| 645 | __ASM volatile ("ldrexh %0, %1" : "=r" (result) : "Q" (*addr) );
|
---|
| 646 | #else
|
---|
| 647 | /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
|
---|
| 648 | accepted by assembler. So has to use following less efficient pattern.
|
---|
| 649 | */
|
---|
| 650 | __ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) : "memory" );
|
---|
| 651 | #endif
|
---|
| 652 | return ((uint16_t) result); /* Add explicit type cast here */
|
---|
| 653 | }
|
---|
| 654 |
|
---|
| 655 |
|
---|
| 656 | /** \brief LDR Exclusive (32 bit)
|
---|
| 657 |
|
---|
| 658 | This function executes a exclusive LDR instruction for 32 bit values.
|
---|
| 659 |
|
---|
| 660 | \param [in] ptr Pointer to data
|
---|
| 661 | \return value of type uint32_t at (*ptr)
|
---|
| 662 | */
|
---|
| 663 | __attribute__((always_inline)) __STATIC_INLINE uint32_t __LDREXW(volatile uint32_t *addr)
|
---|
| 664 | {
|
---|
| 665 | uint32_t result;
|
---|
| 666 |
|
---|
| 667 | __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
|
---|
| 668 | return(result);
|
---|
| 669 | }
|
---|
| 670 |
|
---|
| 671 |
|
---|
| 672 | /** \brief STR Exclusive (8 bit)
|
---|
| 673 |
|
---|
| 674 | This function executes a exclusive STR instruction for 8 bit values.
|
---|
| 675 |
|
---|
| 676 | \param [in] value Value to store
|
---|
| 677 | \param [in] ptr Pointer to location
|
---|
| 678 | \return 0 Function succeeded
|
---|
| 679 | \return 1 Function failed
|
---|
| 680 | */
|
---|
| 681 | __attribute__((always_inline)) __STATIC_INLINE uint32_t __STREXB(uint8_t value, volatile uint8_t *addr)
|
---|
| 682 | {
|
---|
| 683 | uint32_t result;
|
---|
| 684 |
|
---|
| 685 | __ASM volatile ("strexb %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) );
|
---|
| 686 | return(result);
|
---|
| 687 | }
|
---|
| 688 |
|
---|
| 689 |
|
---|
| 690 | /** \brief STR Exclusive (16 bit)
|
---|
| 691 |
|
---|
| 692 | This function executes a exclusive STR instruction for 16 bit values.
|
---|
| 693 |
|
---|
| 694 | \param [in] value Value to store
|
---|
| 695 | \param [in] ptr Pointer to location
|
---|
| 696 | \return 0 Function succeeded
|
---|
| 697 | \return 1 Function failed
|
---|
| 698 | */
|
---|
| 699 | __attribute__((always_inline)) __STATIC_INLINE uint32_t __STREXH(uint16_t value, volatile uint16_t *addr)
|
---|
| 700 | {
|
---|
| 701 | uint32_t result;
|
---|
| 702 |
|
---|
| 703 | __ASM volatile ("strexh %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) );
|
---|
| 704 | return(result);
|
---|
| 705 | }
|
---|
| 706 |
|
---|
| 707 |
|
---|
| 708 | /** \brief STR Exclusive (32 bit)
|
---|
| 709 |
|
---|
| 710 | This function executes a exclusive STR instruction for 32 bit values.
|
---|
| 711 |
|
---|
| 712 | \param [in] value Value to store
|
---|
| 713 | \param [in] ptr Pointer to location
|
---|
| 714 | \return 0 Function succeeded
|
---|
| 715 | \return 1 Function failed
|
---|
| 716 | */
|
---|
| 717 | __attribute__((always_inline)) __STATIC_INLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr)
|
---|
| 718 | {
|
---|
| 719 | uint32_t result;
|
---|
| 720 |
|
---|
| 721 | __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
|
---|
| 722 | return(result);
|
---|
| 723 | }
|
---|
| 724 |
|
---|
| 725 |
|
---|
| 726 | /** \brief Remove the exclusive lock
|
---|
| 727 |
|
---|
| 728 | This function removes the exclusive lock which is created by LDREX.
|
---|
| 729 |
|
---|
| 730 | */
|
---|
| 731 | __attribute__((always_inline)) __STATIC_INLINE void __CLREX(void)
|
---|
| 732 | {
|
---|
| 733 | __ASM volatile ("clrex" ::: "memory");
|
---|
| 734 | }
|
---|
| 735 |
|
---|
| 736 |
|
---|
| 737 | /** \brief Signed Saturate
|
---|
| 738 |
|
---|
| 739 | This function saturates a signed value.
|
---|
| 740 |
|
---|
| 741 | \param [in] value Value to be saturated
|
---|
| 742 | \param [in] sat Bit position to saturate to (1..32)
|
---|
| 743 | \return Saturated value
|
---|
| 744 | */
|
---|
| 745 | #define __SSAT(ARG1,ARG2) \
|
---|
| 746 | ({ \
|
---|
| 747 | uint32_t __RES, __ARG1 = (ARG1); \
|
---|
| 748 | __ASM ("ssat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \
|
---|
| 749 | __RES; \
|
---|
| 750 | })
|
---|
| 751 |
|
---|
| 752 |
|
---|
| 753 | /** \brief Unsigned Saturate
|
---|
| 754 |
|
---|
| 755 | This function saturates an unsigned value.
|
---|
| 756 |
|
---|
| 757 | \param [in] value Value to be saturated
|
---|
| 758 | \param [in] sat Bit position to saturate to (0..31)
|
---|
| 759 | \return Saturated value
|
---|
| 760 | */
|
---|
| 761 | #define __USAT(ARG1,ARG2) \
|
---|
| 762 | ({ \
|
---|
| 763 | uint32_t __RES, __ARG1 = (ARG1); \
|
---|
| 764 | __ASM ("usat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \
|
---|
| 765 | __RES; \
|
---|
| 766 | })
|
---|
| 767 |
|
---|
| 768 |
|
---|
| 769 | /** \brief Rotate Right with Extend (32 bit)
|
---|
| 770 |
|
---|
| 771 | This function moves each bit of a bitstring right by one bit.
|
---|
| 772 | The carry input is shifted in at the left end of the bitstring.
|
---|
| 773 |
|
---|
| 774 | \param [in] value Value to rotate
|
---|
| 775 | \return Rotated value
|
---|
| 776 | */
|
---|
| 777 | __attribute__((always_inline)) __STATIC_INLINE uint32_t __RRX(uint32_t value)
|
---|
| 778 | {
|
---|
| 779 | uint32_t result;
|
---|
| 780 |
|
---|
| 781 | __ASM volatile ("rrx %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
|
---|
| 782 | return(result);
|
---|
| 783 | }
|
---|
| 784 |
|
---|
| 785 |
|
---|
| 786 | /** \brief LDRT Unprivileged (8 bit)
|
---|
| 787 |
|
---|
| 788 | This function executes a Unprivileged LDRT instruction for 8 bit value.
|
---|
| 789 |
|
---|
| 790 | \param [in] ptr Pointer to data
|
---|
| 791 | \return value of type uint8_t at (*ptr)
|
---|
| 792 | */
|
---|
| 793 | __attribute__((always_inline)) __STATIC_INLINE uint8_t __LDRBT(volatile uint8_t *addr)
|
---|
| 794 | {
|
---|
| 795 | uint32_t result;
|
---|
| 796 |
|
---|
| 797 | #if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
|
---|
| 798 | __ASM volatile ("ldrbt %0, %1" : "=r" (result) : "Q" (*addr) );
|
---|
| 799 | #else
|
---|
| 800 | /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
|
---|
| 801 | accepted by assembler. So has to use following less efficient pattern.
|
---|
| 802 | */
|
---|
| 803 | __ASM volatile ("ldrbt %0, [%1]" : "=r" (result) : "r" (addr) : "memory" );
|
---|
| 804 | #endif
|
---|
| 805 | return ((uint8_t) result); /* Add explicit type cast here */
|
---|
| 806 | }
|
---|
| 807 |
|
---|
| 808 |
|
---|
| 809 | /** \brief LDRT Unprivileged (16 bit)
|
---|
| 810 |
|
---|
| 811 | This function executes a Unprivileged LDRT instruction for 16 bit values.
|
---|
| 812 |
|
---|
| 813 | \param [in] ptr Pointer to data
|
---|
| 814 | \return value of type uint16_t at (*ptr)
|
---|
| 815 | */
|
---|
| 816 | __attribute__((always_inline)) __STATIC_INLINE uint16_t __LDRHT(volatile uint16_t *addr)
|
---|
| 817 | {
|
---|
| 818 | uint32_t result;
|
---|
| 819 |
|
---|
| 820 | #if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
|
---|
| 821 | __ASM volatile ("ldrht %0, %1" : "=r" (result) : "Q" (*addr) );
|
---|
| 822 | #else
|
---|
| 823 | /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
|
---|
| 824 | accepted by assembler. So has to use following less efficient pattern.
|
---|
| 825 | */
|
---|
| 826 | __ASM volatile ("ldrht %0, [%1]" : "=r" (result) : "r" (addr) : "memory" );
|
---|
| 827 | #endif
|
---|
| 828 | return ((uint16_t) result); /* Add explicit type cast here */
|
---|
| 829 | }
|
---|
| 830 |
|
---|
| 831 |
|
---|
| 832 | /** \brief LDRT Unprivileged (32 bit)
|
---|
| 833 |
|
---|
| 834 | This function executes a Unprivileged LDRT instruction for 32 bit values.
|
---|
| 835 |
|
---|
| 836 | \param [in] ptr Pointer to data
|
---|
| 837 | \return value of type uint32_t at (*ptr)
|
---|
| 838 | */
|
---|
| 839 | __attribute__((always_inline)) __STATIC_INLINE uint32_t __LDRT(volatile uint32_t *addr)
|
---|
| 840 | {
|
---|
| 841 | uint32_t result;
|
---|
| 842 |
|
---|
| 843 | __ASM volatile ("ldrt %0, %1" : "=r" (result) : "Q" (*addr) );
|
---|
| 844 | return(result);
|
---|
| 845 | }
|
---|
| 846 |
|
---|
| 847 |
|
---|
| 848 | /** \brief STRT Unprivileged (8 bit)
|
---|
| 849 |
|
---|
| 850 | This function executes a Unprivileged STRT instruction for 8 bit values.
|
---|
| 851 |
|
---|
| 852 | \param [in] value Value to store
|
---|
| 853 | \param [in] ptr Pointer to location
|
---|
| 854 | */
|
---|
| 855 | __attribute__((always_inline)) __STATIC_INLINE void __STRBT(uint8_t value, volatile uint8_t *addr)
|
---|
| 856 | {
|
---|
| 857 | __ASM volatile ("strbt %1, %0" : "=Q" (*addr) : "r" ((uint32_t)value) );
|
---|
| 858 | }
|
---|
| 859 |
|
---|
| 860 |
|
---|
| 861 | /** \brief STRT Unprivileged (16 bit)
|
---|
| 862 |
|
---|
| 863 | This function executes a Unprivileged STRT instruction for 16 bit values.
|
---|
| 864 |
|
---|
| 865 | \param [in] value Value to store
|
---|
| 866 | \param [in] ptr Pointer to location
|
---|
| 867 | */
|
---|
| 868 | __attribute__((always_inline)) __STATIC_INLINE void __STRHT(uint16_t value, volatile uint16_t *addr)
|
---|
| 869 | {
|
---|
| 870 | __ASM volatile ("strht %1, %0" : "=Q" (*addr) : "r" ((uint32_t)value) );
|
---|
| 871 | }
|
---|
| 872 |
|
---|
| 873 |
|
---|
| 874 | /** \brief STRT Unprivileged (32 bit)
|
---|
| 875 |
|
---|
| 876 | This function executes a Unprivileged STRT instruction for 32 bit values.
|
---|
| 877 |
|
---|
| 878 | \param [in] value Value to store
|
---|
| 879 | \param [in] ptr Pointer to location
|
---|
| 880 | */
|
---|
| 881 | __attribute__((always_inline)) __STATIC_INLINE void __STRT(uint32_t value, volatile uint32_t *addr)
|
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| 882 | {
|
---|
| 883 | __ASM volatile ("strt %1, %0" : "=Q" (*addr) : "r" (value) );
|
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| 884 | }
|
---|
| 885 |
|
---|
| 886 | #endif /* (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300) */
|
---|
| 887 |
|
---|
| 888 |
|
---|
| 889 | #elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/
|
---|
| 890 | /* IAR iccarm specific functions */
|
---|
| 891 | #include <cmsis_iar.h>
|
---|
| 892 |
|
---|
| 893 |
|
---|
| 894 | #elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/
|
---|
| 895 | /* TI CCS specific functions */
|
---|
| 896 | #include <cmsis_ccs.h>
|
---|
| 897 |
|
---|
| 898 |
|
---|
| 899 | #elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/
|
---|
| 900 | /* TASKING carm specific functions */
|
---|
| 901 | /*
|
---|
| 902 | * The CMSIS functions have been implemented as intrinsics in the compiler.
|
---|
| 903 | * Please use "carm -?i" to get an up to date list of all intrinsics,
|
---|
| 904 | * Including the CMSIS ones.
|
---|
| 905 | */
|
---|
| 906 |
|
---|
| 907 |
|
---|
| 908 | #elif defined ( __CSMC__ ) /*------------------ COSMIC Compiler -------------------*/
|
---|
| 909 | /* Cosmic specific functions */
|
---|
| 910 | #include <cmsis_csm.h>
|
---|
| 911 |
|
---|
| 912 | #endif
|
---|
| 913 |
|
---|
| 914 | /*@}*/ /* end of group CMSIS_Core_InstructionInterface */
|
---|
| 915 |
|
---|
| 916 | #endif /* __CORE_CMINSTR_H */
|
---|