source: asp3_tinet_ecnl_arm/trunk/asp3_dcre/mbed/cmsis/core_cm7.h@ 352

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1/**************************************************************************//**
2 * @file core_cm7.h
3 * @brief CMSIS Cortex-M7 Core Peripheral Access Layer Header File
4 * @version V4.10
5 * @date 18. March 2015
6 *
7 * @note
8 *
9 ******************************************************************************/
10/* Copyright (c) 2009 - 2015 ARM LIMITED
11
12 All rights reserved.
13 Redistribution and use in source and binary forms, with or without
14 modification, are permitted provided that the following conditions are met:
15 - Redistributions of source code must retain the above copyright
16 notice, this list of conditions and the following disclaimer.
17 - Redistributions in binary form must reproduce the above copyright
18 notice, this list of conditions and the following disclaimer in the
19 documentation and/or other materials provided with the distribution.
20 - Neither the name of ARM nor the names of its contributors may be used
21 to endorse or promote products derived from this software without
22 specific prior written permission.
23 *
24 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
25 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
26 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
27 ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
28 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
29 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
30 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
31 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
32 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
33 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
34 POSSIBILITY OF SUCH DAMAGE.
35 ---------------------------------------------------------------------------*/
36
37
38#if defined ( __ICCARM__ )
39 #pragma system_include /* treat file as system include file for MISRA check */
40#endif
41
42#ifndef __CORE_CM7_H_GENERIC
43#define __CORE_CM7_H_GENERIC
44
45#ifdef __cplusplus
46 extern "C" {
47#endif
48
49/** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
50 CMSIS violates the following MISRA-C:2004 rules:
51
52 \li Required Rule 8.5, object/function definition in header file.<br>
53 Function definitions in header files are used to allow 'inlining'.
54
55 \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
56 Unions are used for effective representation of core registers.
57
58 \li Advisory Rule 19.7, Function-like macro defined.<br>
59 Function-like macros are used to allow more efficient code.
60 */
61
62
63/*******************************************************************************
64 * CMSIS definitions
65 ******************************************************************************/
66/** \ingroup Cortex_M7
67 @{
68 */
69
70/* CMSIS CM7 definitions */
71#define __CM7_CMSIS_VERSION_MAIN (0x04) /*!< [31:16] CMSIS HAL main version */
72#define __CM7_CMSIS_VERSION_SUB (0x00) /*!< [15:0] CMSIS HAL sub version */
73#define __CM7_CMSIS_VERSION ((__CM7_CMSIS_VERSION_MAIN << 16) | \
74 __CM7_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */
75
76#define __CORTEX_M (0x07) /*!< Cortex-M Core */
77
78
79#if defined ( __CC_ARM )
80 #define __ASM __asm /*!< asm keyword for ARM Compiler */
81 #define __INLINE __inline /*!< inline keyword for ARM Compiler */
82 #define __STATIC_INLINE static __inline
83
84#elif defined ( __GNUC__ )
85 #define __ASM __asm /*!< asm keyword for GNU Compiler */
86 #define __INLINE inline /*!< inline keyword for GNU Compiler */
87 #define __STATIC_INLINE static inline
88
89#elif defined ( __ICCARM__ )
90 #define __ASM __asm /*!< asm keyword for IAR Compiler */
91 #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */
92 #define __STATIC_INLINE static inline
93
94#elif defined ( __TMS470__ )
95 #define __ASM __asm /*!< asm keyword for TI CCS Compiler */
96 #define __STATIC_INLINE static inline
97
98#elif defined ( __TASKING__ )
99 #define __ASM __asm /*!< asm keyword for TASKING Compiler */
100 #define __INLINE inline /*!< inline keyword for TASKING Compiler */
101 #define __STATIC_INLINE static inline
102
103#elif defined ( __CSMC__ )
104 #define __packed
105 #define __ASM _asm /*!< asm keyword for COSMIC Compiler */
106 #define __INLINE inline /*use -pc99 on compile line !< inline keyword for COSMIC Compiler */
107 #define __STATIC_INLINE static inline
108
109#endif
110
111/** __FPU_USED indicates whether an FPU is used or not.
112 For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions.
113*/
114#if defined ( __CC_ARM )
115 #if defined __TARGET_FPU_VFP
116 #if (__FPU_PRESENT == 1)
117 #define __FPU_USED 1
118 #else
119 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
120 #define __FPU_USED 0
121 #endif
122 #else
123 #define __FPU_USED 0
124 #endif
125
126#elif defined ( __GNUC__ )
127 #if defined (__VFP_FP__) && !defined(__SOFTFP__)
128 #if (__FPU_PRESENT == 1)
129 #define __FPU_USED 1
130 #else
131 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
132 #define __FPU_USED 0
133 #endif
134 #else
135 #define __FPU_USED 0
136 #endif
137
138#elif defined ( __ICCARM__ )
139 #if defined __ARMVFP__
140 #if (__FPU_PRESENT == 1)
141 #define __FPU_USED 1
142 #else
143 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
144 #define __FPU_USED 0
145 #endif
146 #else
147 #define __FPU_USED 0
148 #endif
149
150#elif defined ( __TMS470__ )
151 #if defined __TI_VFP_SUPPORT__
152 #if (__FPU_PRESENT == 1)
153 #define __FPU_USED 1
154 #else
155 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
156 #define __FPU_USED 0
157 #endif
158 #else
159 #define __FPU_USED 0
160 #endif
161
162#elif defined ( __TASKING__ )
163 #if defined __FPU_VFP__
164 #if (__FPU_PRESENT == 1)
165 #define __FPU_USED 1
166 #else
167 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
168 #define __FPU_USED 0
169 #endif
170 #else
171 #define __FPU_USED 0
172 #endif
173
174#elif defined ( __CSMC__ ) /* Cosmic */
175 #if ( __CSMC__ & 0x400) // FPU present for parser
176 #if (__FPU_PRESENT == 1)
177 #define __FPU_USED 1
178 #else
179 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
180 #define __FPU_USED 0
181 #endif
182 #else
183 #define __FPU_USED 0
184 #endif
185#endif
186
187#include <stdint.h> /* standard types definitions */
188#include <core_cmInstr.h> /* Core Instruction Access */
189#include <core_cmFunc.h> /* Core Function Access */
190#include <core_cmSimd.h> /* Compiler specific SIMD Intrinsics */
191
192#ifdef __cplusplus
193}
194#endif
195
196#endif /* __CORE_CM7_H_GENERIC */
197
198#ifndef __CMSIS_GENERIC
199
200#ifndef __CORE_CM7_H_DEPENDANT
201#define __CORE_CM7_H_DEPENDANT
202
203#ifdef __cplusplus
204 extern "C" {
205#endif
206
207/* check device defines and use defaults */
208#if defined __CHECK_DEVICE_DEFINES
209 #ifndef __CM7_REV
210 #define __CM7_REV 0x0000
211 #warning "__CM7_REV not defined in device header file; using default!"
212 #endif
213
214 #ifndef __FPU_PRESENT
215 #define __FPU_PRESENT 0
216 #warning "__FPU_PRESENT not defined in device header file; using default!"
217 #endif
218
219 #ifndef __MPU_PRESENT
220 #define __MPU_PRESENT 0
221 #warning "__MPU_PRESENT not defined in device header file; using default!"
222 #endif
223
224 #ifndef __ICACHE_PRESENT
225 #define __ICACHE_PRESENT 0
226 #warning "__ICACHE_PRESENT not defined in device header file; using default!"
227 #endif
228
229 #ifndef __DCACHE_PRESENT
230 #define __DCACHE_PRESENT 0
231 #warning "__DCACHE_PRESENT not defined in device header file; using default!"
232 #endif
233
234 #ifndef __DTCM_PRESENT
235 #define __DTCM_PRESENT 0
236 #warning "__DTCM_PRESENT not defined in device header file; using default!"
237 #endif
238
239 #ifndef __NVIC_PRIO_BITS
240 #define __NVIC_PRIO_BITS 3
241 #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
242 #endif
243
244 #ifndef __Vendor_SysTickConfig
245 #define __Vendor_SysTickConfig 0
246 #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
247 #endif
248#endif
249
250/* IO definitions (access restrictions to peripheral registers) */
251/**
252 \defgroup CMSIS_glob_defs CMSIS Global Defines
253
254 <strong>IO Type Qualifiers</strong> are used
255 \li to specify the access to peripheral variables.
256 \li for automatic generation of peripheral register debug information.
257*/
258#ifdef __cplusplus
259 #define __I volatile /*!< Defines 'read only' permissions */
260#else
261 #define __I volatile const /*!< Defines 'read only' permissions */
262#endif
263#define __O volatile /*!< Defines 'write only' permissions */
264#define __IO volatile /*!< Defines 'read / write' permissions */
265
266#ifdef __cplusplus
267 #define __IM volatile /*!< Defines 'read only' permissions */
268#else
269 #define __IM volatile const /*!< Defines 'read only' permissions */
270#endif
271#define __OM volatile /*!< Defines 'write only' permissions */
272#define __IOM volatile /*!< Defines 'read / write' permissions */
273
274/*@} end of group Cortex_M7 */
275
276
277
278/*******************************************************************************
279 * Register Abstraction
280 Core Register contain:
281 - Core Register
282 - Core NVIC Register
283 - Core SCB Register
284 - Core SysTick Register
285 - Core Debug Register
286 - Core MPU Register
287 - Core FPU Register
288 ******************************************************************************/
289/** \defgroup CMSIS_core_register Defines and Type Definitions
290 \brief Type definitions and defines for Cortex-M processor based devices.
291*/
292
293/** \ingroup CMSIS_core_register
294 \defgroup CMSIS_CORE Status and Control Registers
295 \brief Core Register type definitions.
296 @{
297 */
298
299/** \brief Union type to access the Application Program Status Register (APSR).
300 */
301typedef union
302{
303 struct
304 {
305 uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */
306 uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
307 uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */
308 uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
309 uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
310 uint32_t C:1; /*!< bit: 29 Carry condition code flag */
311 uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
312 uint32_t N:1; /*!< bit: 31 Negative condition code flag */
313 } b; /*!< Structure used for bit access */
314 uint32_t w; /*!< Type used for word access */
315} APSR_Type;
316
317/* APSR Register Definitions */
318#define APSR_N_Pos 31 /*!< APSR: N Position */
319#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */
320
321#define APSR_Z_Pos 30 /*!< APSR: Z Position */
322#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */
323
324#define APSR_C_Pos 29 /*!< APSR: C Position */
325#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */
326
327#define APSR_V_Pos 28 /*!< APSR: V Position */
328#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */
329
330#define APSR_Q_Pos 27 /*!< APSR: Q Position */
331#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */
332
333#define APSR_GE_Pos 16 /*!< APSR: GE Position */
334#define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */
335
336
337/** \brief Union type to access the Interrupt Program Status Register (IPSR).
338 */
339typedef union
340{
341 struct
342 {
343 uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
344 uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
345 } b; /*!< Structure used for bit access */
346 uint32_t w; /*!< Type used for word access */
347} IPSR_Type;
348
349/* IPSR Register Definitions */
350#define IPSR_ISR_Pos 0 /*!< IPSR: ISR Position */
351#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */
352
353
354/** \brief Union type to access the Special-Purpose Program Status Registers (xPSR).
355 */
356typedef union
357{
358 struct
359 {
360 uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
361 uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */
362 uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
363 uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */
364 uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */
365 uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */
366 uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
367 uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
368 uint32_t C:1; /*!< bit: 29 Carry condition code flag */
369 uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
370 uint32_t N:1; /*!< bit: 31 Negative condition code flag */
371 } b; /*!< Structure used for bit access */
372 uint32_t w; /*!< Type used for word access */
373} xPSR_Type;
374
375/* xPSR Register Definitions */
376#define xPSR_N_Pos 31 /*!< xPSR: N Position */
377#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */
378
379#define xPSR_Z_Pos 30 /*!< xPSR: Z Position */
380#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */
381
382#define xPSR_C_Pos 29 /*!< xPSR: C Position */
383#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */
384
385#define xPSR_V_Pos 28 /*!< xPSR: V Position */
386#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */
387
388#define xPSR_Q_Pos 27 /*!< xPSR: Q Position */
389#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */
390
391#define xPSR_IT_Pos 25 /*!< xPSR: IT Position */
392#define xPSR_IT_Msk (3UL << xPSR_IT_Pos) /*!< xPSR: IT Mask */
393
394#define xPSR_T_Pos 24 /*!< xPSR: T Position */
395#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */
396
397#define xPSR_GE_Pos 16 /*!< xPSR: GE Position */
398#define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */
399
400#define xPSR_ISR_Pos 0 /*!< xPSR: ISR Position */
401#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */
402
403
404/** \brief Union type to access the Control Registers (CONTROL).
405 */
406typedef union
407{
408 struct
409 {
410 uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */
411 uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */
412 uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */
413 uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */
414 } b; /*!< Structure used for bit access */
415 uint32_t w; /*!< Type used for word access */
416} CONTROL_Type;
417
418/* CONTROL Register Definitions */
419#define CONTROL_FPCA_Pos 2 /*!< CONTROL: FPCA Position */
420#define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */
421
422#define CONTROL_SPSEL_Pos 1 /*!< CONTROL: SPSEL Position */
423#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */
424
425#define CONTROL_nPRIV_Pos 0 /*!< CONTROL: nPRIV Position */
426#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */
427
428/*@} end of group CMSIS_CORE */
429
430
431/** \ingroup CMSIS_core_register
432 \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
433 \brief Type definitions for the NVIC Registers
434 @{
435 */
436
437/** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
438 */
439typedef struct
440{
441 __IO uint32_t ISER[8]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
442 uint32_t RESERVED0[24];
443 __IO uint32_t ICER[8]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
444 uint32_t RSERVED1[24];
445 __IO uint32_t ISPR[8]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
446 uint32_t RESERVED2[24];
447 __IO uint32_t ICPR[8]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
448 uint32_t RESERVED3[24];
449 __IO uint32_t IABR[8]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */
450 uint32_t RESERVED4[56];
451 __IO uint8_t IP[240]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */
452 uint32_t RESERVED5[644];
453 __O uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */
454} NVIC_Type;
455
456/* Software Triggered Interrupt Register Definitions */
457#define NVIC_STIR_INTID_Pos 0 /*!< STIR: INTLINESNUM Position */
458#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */
459
460/*@} end of group CMSIS_NVIC */
461
462
463/** \ingroup CMSIS_core_register
464 \defgroup CMSIS_SCB System Control Block (SCB)
465 \brief Type definitions for the System Control Block Registers
466 @{
467 */
468
469/** \brief Structure type to access the System Control Block (SCB).
470 */
471typedef struct
472{
473 __I uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
474 __IO uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
475 __IO uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */
476 __IO uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
477 __IO uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
478 __IO uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
479 __IO uint8_t SHPR[12]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */
480 __IO uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
481 __IO uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */
482 __IO uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */
483 __IO uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */
484 __IO uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */
485 __IO uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */
486 __IO uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */
487 __I uint32_t ID_PFR[2]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */
488 __I uint32_t ID_DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */
489 __I uint32_t ID_AFR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */
490 __I uint32_t ID_MFR[4]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */
491 __I uint32_t ID_ISAR[5]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */
492 uint32_t RESERVED0[1];
493 __I uint32_t CLIDR; /*!< Offset: 0x078 (R/ ) Cache Level ID register */
494 __I uint32_t CTR; /*!< Offset: 0x07C (R/ ) Cache Type register */
495 __I uint32_t CCSIDR; /*!< Offset: 0x080 (R/ ) Cache Size ID Register */
496 __IO uint32_t CSSELR; /*!< Offset: 0x084 (R/W) Cache Size Selection Register */
497 __IO uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */
498 uint32_t RESERVED3[93];
499 __O uint32_t STIR; /*!< Offset: 0x200 ( /W) Software Triggered Interrupt Register */
500 uint32_t RESERVED4[15];
501 __I uint32_t MVFR0; /*!< Offset: 0x240 (R/ ) Media and VFP Feature Register 0 */
502 __I uint32_t MVFR1; /*!< Offset: 0x244 (R/ ) Media and VFP Feature Register 1 */
503 __I uint32_t MVFR2; /*!< Offset: 0x248 (R/ ) Media and VFP Feature Register 1 */
504 uint32_t RESERVED5[1];
505 __O uint32_t ICIALLU; /*!< Offset: 0x250 ( /W) I-Cache Invalidate All to PoU */
506 uint32_t RESERVED6[1];
507 __O uint32_t ICIMVAU; /*!< Offset: 0x258 ( /W) I-Cache Invalidate by MVA to PoU */
508 __O uint32_t DCIMVAC; /*!< Offset: 0x25C ( /W) D-Cache Invalidate by MVA to PoC */
509 __O uint32_t DCISW; /*!< Offset: 0x260 ( /W) D-Cache Invalidate by Set-way */
510 __O uint32_t DCCMVAU; /*!< Offset: 0x264 ( /W) D-Cache Clean by MVA to PoU */
511 __O uint32_t DCCMVAC; /*!< Offset: 0x268 ( /W) D-Cache Clean by MVA to PoC */
512 __O uint32_t DCCSW; /*!< Offset: 0x26C ( /W) D-Cache Clean by Set-way */
513 __O uint32_t DCCIMVAC; /*!< Offset: 0x270 ( /W) D-Cache Clean and Invalidate by MVA to PoC */
514 __O uint32_t DCCISW; /*!< Offset: 0x274 ( /W) D-Cache Clean and Invalidate by Set-way */
515 uint32_t RESERVED7[6];
516 __IO uint32_t ITCMCR; /*!< Offset: 0x290 (R/W) Instruction Tightly-Coupled Memory Control Register */
517 __IO uint32_t DTCMCR; /*!< Offset: 0x294 (R/W) Data Tightly-Coupled Memory Control Registers */
518 __IO uint32_t AHBPCR; /*!< Offset: 0x298 (R/W) AHBP Control Register */
519 __IO uint32_t CACR; /*!< Offset: 0x29C (R/W) L1 Cache Control Register */
520 __IO uint32_t AHBSCR; /*!< Offset: 0x2A0 (R/W) AHB Slave Control Register */
521 uint32_t RESERVED8[1];
522 __IO uint32_t ABFSR; /*!< Offset: 0x2A8 (R/W) Auxiliary Bus Fault Status Register */
523} SCB_Type;
524
525/* SCB CPUID Register Definitions */
526#define SCB_CPUID_IMPLEMENTER_Pos 24 /*!< SCB CPUID: IMPLEMENTER Position */
527#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
528
529#define SCB_CPUID_VARIANT_Pos 20 /*!< SCB CPUID: VARIANT Position */
530#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
531
532#define SCB_CPUID_ARCHITECTURE_Pos 16 /*!< SCB CPUID: ARCHITECTURE Position */
533#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
534
535#define SCB_CPUID_PARTNO_Pos 4 /*!< SCB CPUID: PARTNO Position */
536#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
537
538#define SCB_CPUID_REVISION_Pos 0 /*!< SCB CPUID: REVISION Position */
539#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */
540
541/* SCB Interrupt Control State Register Definitions */
542#define SCB_ICSR_NMIPENDSET_Pos 31 /*!< SCB ICSR: NMIPENDSET Position */
543#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */
544
545#define SCB_ICSR_PENDSVSET_Pos 28 /*!< SCB ICSR: PENDSVSET Position */
546#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
547
548#define SCB_ICSR_PENDSVCLR_Pos 27 /*!< SCB ICSR: PENDSVCLR Position */
549#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
550
551#define SCB_ICSR_PENDSTSET_Pos 26 /*!< SCB ICSR: PENDSTSET Position */
552#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
553
554#define SCB_ICSR_PENDSTCLR_Pos 25 /*!< SCB ICSR: PENDSTCLR Position */
555#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
556
557#define SCB_ICSR_ISRPREEMPT_Pos 23 /*!< SCB ICSR: ISRPREEMPT Position */
558#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
559
560#define SCB_ICSR_ISRPENDING_Pos 22 /*!< SCB ICSR: ISRPENDING Position */
561#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
562
563#define SCB_ICSR_VECTPENDING_Pos 12 /*!< SCB ICSR: VECTPENDING Position */
564#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
565
566#define SCB_ICSR_RETTOBASE_Pos 11 /*!< SCB ICSR: RETTOBASE Position */
567#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */
568
569#define SCB_ICSR_VECTACTIVE_Pos 0 /*!< SCB ICSR: VECTACTIVE Position */
570#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */
571
572/* SCB Vector Table Offset Register Definitions */
573#define SCB_VTOR_TBLOFF_Pos 7 /*!< SCB VTOR: TBLOFF Position */
574#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */
575
576/* SCB Application Interrupt and Reset Control Register Definitions */
577#define SCB_AIRCR_VECTKEY_Pos 16 /*!< SCB AIRCR: VECTKEY Position */
578#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
579
580#define SCB_AIRCR_VECTKEYSTAT_Pos 16 /*!< SCB AIRCR: VECTKEYSTAT Position */
581#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
582
583#define SCB_AIRCR_ENDIANESS_Pos 15 /*!< SCB AIRCR: ENDIANESS Position */
584#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
585
586#define SCB_AIRCR_PRIGROUP_Pos 8 /*!< SCB AIRCR: PRIGROUP Position */
587#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */
588
589#define SCB_AIRCR_SYSRESETREQ_Pos 2 /*!< SCB AIRCR: SYSRESETREQ Position */
590#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
591
592#define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /*!< SCB AIRCR: VECTCLRACTIVE Position */
593#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
594
595#define SCB_AIRCR_VECTRESET_Pos 0 /*!< SCB AIRCR: VECTRESET Position */
596#define SCB_AIRCR_VECTRESET_Msk (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/) /*!< SCB AIRCR: VECTRESET Mask */
597
598/* SCB System Control Register Definitions */
599#define SCB_SCR_SEVONPEND_Pos 4 /*!< SCB SCR: SEVONPEND Position */
600#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
601
602#define SCB_SCR_SLEEPDEEP_Pos 2 /*!< SCB SCR: SLEEPDEEP Position */
603#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
604
605#define SCB_SCR_SLEEPONEXIT_Pos 1 /*!< SCB SCR: SLEEPONEXIT Position */
606#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
607
608/* SCB Configuration Control Register Definitions */
609#define SCB_CCR_BP_Pos 18 /*!< SCB CCR: Branch prediction enable bit Position */
610#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: Branch prediction enable bit Mask */
611
612#define SCB_CCR_IC_Pos 17 /*!< SCB CCR: Instruction cache enable bit Position */
613#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: Instruction cache enable bit Mask */
614
615#define SCB_CCR_DC_Pos 16 /*!< SCB CCR: Cache enable bit Position */
616#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: Cache enable bit Mask */
617
618#define SCB_CCR_STKALIGN_Pos 9 /*!< SCB CCR: STKALIGN Position */
619#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */
620
621#define SCB_CCR_BFHFNMIGN_Pos 8 /*!< SCB CCR: BFHFNMIGN Position */
622#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */
623
624#define SCB_CCR_DIV_0_TRP_Pos 4 /*!< SCB CCR: DIV_0_TRP Position */
625#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */
626
627#define SCB_CCR_UNALIGN_TRP_Pos 3 /*!< SCB CCR: UNALIGN_TRP Position */
628#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
629
630#define SCB_CCR_USERSETMPEND_Pos 1 /*!< SCB CCR: USERSETMPEND Position */
631#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */
632
633#define SCB_CCR_NONBASETHRDENA_Pos 0 /*!< SCB CCR: NONBASETHRDENA Position */
634#define SCB_CCR_NONBASETHRDENA_Msk (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/) /*!< SCB CCR: NONBASETHRDENA Mask */
635
636/* SCB System Handler Control and State Register Definitions */
637#define SCB_SHCSR_USGFAULTENA_Pos 18 /*!< SCB SHCSR: USGFAULTENA Position */
638#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */
639
640#define SCB_SHCSR_BUSFAULTENA_Pos 17 /*!< SCB SHCSR: BUSFAULTENA Position */
641#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */
642
643#define SCB_SHCSR_MEMFAULTENA_Pos 16 /*!< SCB SHCSR: MEMFAULTENA Position */
644#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */
645
646#define SCB_SHCSR_SVCALLPENDED_Pos 15 /*!< SCB SHCSR: SVCALLPENDED Position */
647#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
648
649#define SCB_SHCSR_BUSFAULTPENDED_Pos 14 /*!< SCB SHCSR: BUSFAULTPENDED Position */
650#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */
651
652#define SCB_SHCSR_MEMFAULTPENDED_Pos 13 /*!< SCB SHCSR: MEMFAULTPENDED Position */
653#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */
654
655#define SCB_SHCSR_USGFAULTPENDED_Pos 12 /*!< SCB SHCSR: USGFAULTPENDED Position */
656#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */
657
658#define SCB_SHCSR_SYSTICKACT_Pos 11 /*!< SCB SHCSR: SYSTICKACT Position */
659#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */
660
661#define SCB_SHCSR_PENDSVACT_Pos 10 /*!< SCB SHCSR: PENDSVACT Position */
662#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */
663
664#define SCB_SHCSR_MONITORACT_Pos 8 /*!< SCB SHCSR: MONITORACT Position */
665#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */
666
667#define SCB_SHCSR_SVCALLACT_Pos 7 /*!< SCB SHCSR: SVCALLACT Position */
668#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */
669
670#define SCB_SHCSR_USGFAULTACT_Pos 3 /*!< SCB SHCSR: USGFAULTACT Position */
671#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */
672
673#define SCB_SHCSR_BUSFAULTACT_Pos 1 /*!< SCB SHCSR: BUSFAULTACT Position */
674#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */
675
676#define SCB_SHCSR_MEMFAULTACT_Pos 0 /*!< SCB SHCSR: MEMFAULTACT Position */
677#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */
678
679/* SCB Configurable Fault Status Registers Definitions */
680#define SCB_CFSR_USGFAULTSR_Pos 16 /*!< SCB CFSR: Usage Fault Status Register Position */
681#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */
682
683#define SCB_CFSR_BUSFAULTSR_Pos 8 /*!< SCB CFSR: Bus Fault Status Register Position */
684#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */
685
686#define SCB_CFSR_MEMFAULTSR_Pos 0 /*!< SCB CFSR: Memory Manage Fault Status Register Position */
687#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */
688
689/* SCB Hard Fault Status Registers Definitions */
690#define SCB_HFSR_DEBUGEVT_Pos 31 /*!< SCB HFSR: DEBUGEVT Position */
691#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */
692
693#define SCB_HFSR_FORCED_Pos 30 /*!< SCB HFSR: FORCED Position */
694#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */
695
696#define SCB_HFSR_VECTTBL_Pos 1 /*!< SCB HFSR: VECTTBL Position */
697#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */
698
699/* SCB Debug Fault Status Register Definitions */
700#define SCB_DFSR_EXTERNAL_Pos 4 /*!< SCB DFSR: EXTERNAL Position */
701#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */
702
703#define SCB_DFSR_VCATCH_Pos 3 /*!< SCB DFSR: VCATCH Position */
704#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */
705
706#define SCB_DFSR_DWTTRAP_Pos 2 /*!< SCB DFSR: DWTTRAP Position */
707#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */
708
709#define SCB_DFSR_BKPT_Pos 1 /*!< SCB DFSR: BKPT Position */
710#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */
711
712#define SCB_DFSR_HALTED_Pos 0 /*!< SCB DFSR: HALTED Position */
713#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */
714
715/* Cache Level ID register */
716#define SCB_CLIDR_LOUU_Pos 27 /*!< SCB CLIDR: LoUU Position */
717#define SCB_CLIDR_LOUU_Msk (7UL << SCB_CLIDR_LOUU_Pos) /*!< SCB CLIDR: LoUU Mask */
718
719#define SCB_CLIDR_LOC_Pos 24 /*!< SCB CLIDR: LoC Position */
720#define SCB_CLIDR_LOC_Msk (7UL << SCB_CLIDR_FORMAT_Pos) /*!< SCB CLIDR: LoC Mask */
721
722/* Cache Type register */
723#define SCB_CTR_FORMAT_Pos 29 /*!< SCB CTR: Format Position */
724#define SCB_CTR_FORMAT_Msk (7UL << SCB_CTR_FORMAT_Pos) /*!< SCB CTR: Format Mask */
725
726#define SCB_CTR_CWG_Pos 24 /*!< SCB CTR: CWG Position */
727#define SCB_CTR_CWG_Msk (0xFUL << SCB_CTR_CWG_Pos) /*!< SCB CTR: CWG Mask */
728
729#define SCB_CTR_ERG_Pos 20 /*!< SCB CTR: ERG Position */
730#define SCB_CTR_ERG_Msk (0xFUL << SCB_CTR_ERG_Pos) /*!< SCB CTR: ERG Mask */
731
732#define SCB_CTR_DMINLINE_Pos 16 /*!< SCB CTR: DminLine Position */
733#define SCB_CTR_DMINLINE_Msk (0xFUL << SCB_CTR_DMINLINE_Pos) /*!< SCB CTR: DminLine Mask */
734
735#define SCB_CTR_IMINLINE_Pos 0 /*!< SCB CTR: ImInLine Position */
736#define SCB_CTR_IMINLINE_Msk (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/) /*!< SCB CTR: ImInLine Mask */
737
738/* Cache Size ID Register */
739#define SCB_CCSIDR_WT_Pos 31 /*!< SCB CCSIDR: WT Position */
740#define SCB_CCSIDR_WT_Msk (7UL << SCB_CCSIDR_WT_Pos) /*!< SCB CCSIDR: WT Mask */
741
742#define SCB_CCSIDR_WB_Pos 30 /*!< SCB CCSIDR: WB Position */
743#define SCB_CCSIDR_WB_Msk (7UL << SCB_CCSIDR_WB_Pos) /*!< SCB CCSIDR: WB Mask */
744
745#define SCB_CCSIDR_RA_Pos 29 /*!< SCB CCSIDR: RA Position */
746#define SCB_CCSIDR_RA_Msk (7UL << SCB_CCSIDR_RA_Pos) /*!< SCB CCSIDR: RA Mask */
747
748#define SCB_CCSIDR_WA_Pos 28 /*!< SCB CCSIDR: WA Position */
749#define SCB_CCSIDR_WA_Msk (7UL << SCB_CCSIDR_WA_Pos) /*!< SCB CCSIDR: WA Mask */
750
751#define SCB_CCSIDR_NUMSETS_Pos 13 /*!< SCB CCSIDR: NumSets Position */
752#define SCB_CCSIDR_NUMSETS_Msk (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos) /*!< SCB CCSIDR: NumSets Mask */
753
754#define SCB_CCSIDR_ASSOCIATIVITY_Pos 3 /*!< SCB CCSIDR: Associativity Position */
755#define SCB_CCSIDR_ASSOCIATIVITY_Msk (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos) /*!< SCB CCSIDR: Associativity Mask */
756
757#define SCB_CCSIDR_LINESIZE_Pos 0 /*!< SCB CCSIDR: LineSize Position */
758#define SCB_CCSIDR_LINESIZE_Msk (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/) /*!< SCB CCSIDR: LineSize Mask */
759
760/* Cache Size Selection Register */
761#define SCB_CSSELR_LEVEL_Pos 1 /*!< SCB CSSELR: Level Position */
762#define SCB_CSSELR_LEVEL_Msk (7UL << SCB_CSSELR_LEVEL_Pos) /*!< SCB CSSELR: Level Mask */
763
764#define SCB_CSSELR_IND_Pos 0 /*!< SCB CSSELR: InD Position */
765#define SCB_CSSELR_IND_Msk (1UL /*<< SCB_CSSELR_IND_Pos*/) /*!< SCB CSSELR: InD Mask */
766
767/* SCB Software Triggered Interrupt Register */
768#define SCB_STIR_INTID_Pos 0 /*!< SCB STIR: INTID Position */
769#define SCB_STIR_INTID_Msk (0x1FFUL /*<< SCB_STIR_INTID_Pos*/) /*!< SCB STIR: INTID Mask */
770
771/* Instruction Tightly-Coupled Memory Control Register*/
772#define SCB_ITCMCR_SZ_Pos 3 /*!< SCB ITCMCR: SZ Position */
773#define SCB_ITCMCR_SZ_Msk (0xFUL << SCB_ITCMCR_SZ_Pos) /*!< SCB ITCMCR: SZ Mask */
774
775#define SCB_ITCMCR_RETEN_Pos 2 /*!< SCB ITCMCR: RETEN Position */
776#define SCB_ITCMCR_RETEN_Msk (1UL << SCB_ITCMCR_RETEN_Pos) /*!< SCB ITCMCR: RETEN Mask */
777
778#define SCB_ITCMCR_RMW_Pos 1 /*!< SCB ITCMCR: RMW Position */
779#define SCB_ITCMCR_RMW_Msk (1UL << SCB_ITCMCR_RMW_Pos) /*!< SCB ITCMCR: RMW Mask */
780
781#define SCB_ITCMCR_EN_Pos 0 /*!< SCB ITCMCR: EN Position */
782#define SCB_ITCMCR_EN_Msk (1UL /*<< SCB_ITCMCR_EN_Pos*/) /*!< SCB ITCMCR: EN Mask */
783
784/* Data Tightly-Coupled Memory Control Registers */
785#define SCB_DTCMCR_SZ_Pos 3 /*!< SCB DTCMCR: SZ Position */
786#define SCB_DTCMCR_SZ_Msk (0xFUL << SCB_DTCMCR_SZ_Pos) /*!< SCB DTCMCR: SZ Mask */
787
788#define SCB_DTCMCR_RETEN_Pos 2 /*!< SCB DTCMCR: RETEN Position */
789#define SCB_DTCMCR_RETEN_Msk (1UL << SCB_DTCMCR_RETEN_Pos) /*!< SCB DTCMCR: RETEN Mask */
790
791#define SCB_DTCMCR_RMW_Pos 1 /*!< SCB DTCMCR: RMW Position */
792#define SCB_DTCMCR_RMW_Msk (1UL << SCB_DTCMCR_RMW_Pos) /*!< SCB DTCMCR: RMW Mask */
793
794#define SCB_DTCMCR_EN_Pos 0 /*!< SCB DTCMCR: EN Position */
795#define SCB_DTCMCR_EN_Msk (1UL /*<< SCB_DTCMCR_EN_Pos*/) /*!< SCB DTCMCR: EN Mask */
796
797/* AHBP Control Register */
798#define SCB_AHBPCR_SZ_Pos 1 /*!< SCB AHBPCR: SZ Position */
799#define SCB_AHBPCR_SZ_Msk (7UL << SCB_AHBPCR_SZ_Pos) /*!< SCB AHBPCR: SZ Mask */
800
801#define SCB_AHBPCR_EN_Pos 0 /*!< SCB AHBPCR: EN Position */
802#define SCB_AHBPCR_EN_Msk (1UL /*<< SCB_AHBPCR_EN_Pos*/) /*!< SCB AHBPCR: EN Mask */
803
804/* L1 Cache Control Register */
805#define SCB_CACR_FORCEWT_Pos 2 /*!< SCB CACR: FORCEWT Position */
806#define SCB_CACR_FORCEWT_Msk (1UL << SCB_CACR_FORCEWT_Pos) /*!< SCB CACR: FORCEWT Mask */
807
808#define SCB_CACR_ECCEN_Pos 1 /*!< SCB CACR: ECCEN Position */
809#define SCB_CACR_ECCEN_Msk (1UL << SCB_CACR_ECCEN_Pos) /*!< SCB CACR: ECCEN Mask */
810
811#define SCB_CACR_SIWT_Pos 0 /*!< SCB CACR: SIWT Position */
812#define SCB_CACR_SIWT_Msk (1UL /*<< SCB_CACR_SIWT_Pos*/) /*!< SCB CACR: SIWT Mask */
813
814/* AHBS control register */
815#define SCB_AHBSCR_INITCOUNT_Pos 11 /*!< SCB AHBSCR: INITCOUNT Position */
816#define SCB_AHBSCR_INITCOUNT_Msk (0x1FUL << SCB_AHBPCR_INITCOUNT_Pos) /*!< SCB AHBSCR: INITCOUNT Mask */
817
818#define SCB_AHBSCR_TPRI_Pos 2 /*!< SCB AHBSCR: TPRI Position */
819#define SCB_AHBSCR_TPRI_Msk (0x1FFUL << SCB_AHBPCR_TPRI_Pos) /*!< SCB AHBSCR: TPRI Mask */
820
821#define SCB_AHBSCR_CTL_Pos 0 /*!< SCB AHBSCR: CTL Position*/
822#define SCB_AHBSCR_CTL_Msk (3UL /*<< SCB_AHBPCR_CTL_Pos*/) /*!< SCB AHBSCR: CTL Mask */
823
824/* Auxiliary Bus Fault Status Register */
825#define SCB_ABFSR_AXIMTYPE_Pos 8 /*!< SCB ABFSR: AXIMTYPE Position*/
826#define SCB_ABFSR_AXIMTYPE_Msk (3UL << SCB_ABFSR_AXIMTYPE_Pos) /*!< SCB ABFSR: AXIMTYPE Mask */
827
828#define SCB_ABFSR_EPPB_Pos 4 /*!< SCB ABFSR: EPPB Position*/
829#define SCB_ABFSR_EPPB_Msk (1UL << SCB_ABFSR_EPPB_Pos) /*!< SCB ABFSR: EPPB Mask */
830
831#define SCB_ABFSR_AXIM_Pos 3 /*!< SCB ABFSR: AXIM Position*/
832#define SCB_ABFSR_AXIM_Msk (1UL << SCB_ABFSR_AXIM_Pos) /*!< SCB ABFSR: AXIM Mask */
833
834#define SCB_ABFSR_AHBP_Pos 2 /*!< SCB ABFSR: AHBP Position*/
835#define SCB_ABFSR_AHBP_Msk (1UL << SCB_ABFSR_AHBP_Pos) /*!< SCB ABFSR: AHBP Mask */
836
837#define SCB_ABFSR_DTCM_Pos 1 /*!< SCB ABFSR: DTCM Position*/
838#define SCB_ABFSR_DTCM_Msk (1UL << SCB_ABFSR_DTCM_Pos) /*!< SCB ABFSR: DTCM Mask */
839
840#define SCB_ABFSR_ITCM_Pos 0 /*!< SCB ABFSR: ITCM Position*/
841#define SCB_ABFSR_ITCM_Msk (1UL /*<< SCB_ABFSR_ITCM_Pos*/) /*!< SCB ABFSR: ITCM Mask */
842
843/*@} end of group CMSIS_SCB */
844
845
846/** \ingroup CMSIS_core_register
847 \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
848 \brief Type definitions for the System Control and ID Register not in the SCB
849 @{
850 */
851
852/** \brief Structure type to access the System Control and ID Register not in the SCB.
853 */
854typedef struct
855{
856 uint32_t RESERVED0[1];
857 __I uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */
858 __IO uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */
859} SCnSCB_Type;
860
861/* Interrupt Controller Type Register Definitions */
862#define SCnSCB_ICTR_INTLINESNUM_Pos 0 /*!< ICTR: INTLINESNUM Position */
863#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */
864
865/* Auxiliary Control Register Definitions */
866#define SCnSCB_ACTLR_DISITMATBFLUSH_Pos 12 /*!< ACTLR: DISITMATBFLUSH Position */
867#define SCnSCB_ACTLR_DISITMATBFLUSH_Msk (1UL << SCnSCB_ACTLR_DISITMATBFLUSH_Pos) /*!< ACTLR: DISITMATBFLUSH Mask */
868
869#define SCnSCB_ACTLR_DISRAMODE_Pos 11 /*!< ACTLR: DISRAMODE Position */
870#define SCnSCB_ACTLR_DISRAMODE_Msk (1UL << SCnSCB_ACTLR_DISRAMODE_Pos) /*!< ACTLR: DISRAMODE Mask */
871
872#define SCnSCB_ACTLR_FPEXCODIS_Pos 10 /*!< ACTLR: FPEXCODIS Position */
873#define SCnSCB_ACTLR_FPEXCODIS_Msk (1UL << SCnSCB_ACTLR_FPEXCODIS_Pos) /*!< ACTLR: FPEXCODIS Mask */
874
875#define SCnSCB_ACTLR_DISFOLD_Pos 2 /*!< ACTLR: DISFOLD Position */
876#define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */
877
878#define SCnSCB_ACTLR_DISMCYCINT_Pos 0 /*!< ACTLR: DISMCYCINT Position */
879#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */
880
881/*@} end of group CMSIS_SCnotSCB */
882
883
884/** \ingroup CMSIS_core_register
885 \defgroup CMSIS_SysTick System Tick Timer (SysTick)
886 \brief Type definitions for the System Timer Registers.
887 @{
888 */
889
890/** \brief Structure type to access the System Timer (SysTick).
891 */
892typedef struct
893{
894 __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
895 __IO uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
896 __IO uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
897 __I uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
898} SysTick_Type;
899
900/* SysTick Control / Status Register Definitions */
901#define SysTick_CTRL_COUNTFLAG_Pos 16 /*!< SysTick CTRL: COUNTFLAG Position */
902#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
903
904#define SysTick_CTRL_CLKSOURCE_Pos 2 /*!< SysTick CTRL: CLKSOURCE Position */
905#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
906
907#define SysTick_CTRL_TICKINT_Pos 1 /*!< SysTick CTRL: TICKINT Position */
908#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
909
910#define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */
911#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */
912
913/* SysTick Reload Register Definitions */
914#define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */
915#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */
916
917/* SysTick Current Register Definitions */
918#define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */
919#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */
920
921/* SysTick Calibration Register Definitions */
922#define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */
923#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
924
925#define SysTick_CALIB_SKEW_Pos 30 /*!< SysTick CALIB: SKEW Position */
926#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
927
928#define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */
929#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */
930
931/*@} end of group CMSIS_SysTick */
932
933
934/** \ingroup CMSIS_core_register
935 \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM)
936 \brief Type definitions for the Instrumentation Trace Macrocell (ITM)
937 @{
938 */
939
940/** \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM).
941 */
942typedef struct
943{
944 __O union
945 {
946 __O uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */
947 __O uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */
948 __O uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */
949 } PORT [32]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */
950 uint32_t RESERVED0[864];
951 __IO uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */
952 uint32_t RESERVED1[15];
953 __IO uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */
954 uint32_t RESERVED2[15];
955 __IO uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */
956 uint32_t RESERVED3[29];
957 __O uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */
958 __I uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */
959 __IO uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */
960 uint32_t RESERVED4[43];
961 __O uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */
962 __I uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */
963 uint32_t RESERVED5[6];
964 __I uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */
965 __I uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */
966 __I uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */
967 __I uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */
968 __I uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */
969 __I uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */
970 __I uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */
971 __I uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */
972 __I uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */
973 __I uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */
974 __I uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */
975 __I uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */
976} ITM_Type;
977
978/* ITM Trace Privilege Register Definitions */
979#define ITM_TPR_PRIVMASK_Pos 0 /*!< ITM TPR: PRIVMASK Position */
980#define ITM_TPR_PRIVMASK_Msk (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */
981
982/* ITM Trace Control Register Definitions */
983#define ITM_TCR_BUSY_Pos 23 /*!< ITM TCR: BUSY Position */
984#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */
985
986#define ITM_TCR_TraceBusID_Pos 16 /*!< ITM TCR: ATBID Position */
987#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */
988
989#define ITM_TCR_GTSFREQ_Pos 10 /*!< ITM TCR: Global timestamp frequency Position */
990#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */
991
992#define ITM_TCR_TSPrescale_Pos 8 /*!< ITM TCR: TSPrescale Position */
993#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */
994
995#define ITM_TCR_SWOENA_Pos 4 /*!< ITM TCR: SWOENA Position */
996#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */
997
998#define ITM_TCR_DWTENA_Pos 3 /*!< ITM TCR: DWTENA Position */
999#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */
1000
1001#define ITM_TCR_SYNCENA_Pos 2 /*!< ITM TCR: SYNCENA Position */
1002#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */
1003
1004#define ITM_TCR_TSENA_Pos 1 /*!< ITM TCR: TSENA Position */
1005#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */
1006
1007#define ITM_TCR_ITMENA_Pos 0 /*!< ITM TCR: ITM Enable bit Position */
1008#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */
1009
1010/* ITM Integration Write Register Definitions */
1011#define ITM_IWR_ATVALIDM_Pos 0 /*!< ITM IWR: ATVALIDM Position */
1012#define ITM_IWR_ATVALIDM_Msk (1UL /*<< ITM_IWR_ATVALIDM_Pos*/) /*!< ITM IWR: ATVALIDM Mask */
1013
1014/* ITM Integration Read Register Definitions */
1015#define ITM_IRR_ATREADYM_Pos 0 /*!< ITM IRR: ATREADYM Position */
1016#define ITM_IRR_ATREADYM_Msk (1UL /*<< ITM_IRR_ATREADYM_Pos*/) /*!< ITM IRR: ATREADYM Mask */
1017
1018/* ITM Integration Mode Control Register Definitions */
1019#define ITM_IMCR_INTEGRATION_Pos 0 /*!< ITM IMCR: INTEGRATION Position */
1020#define ITM_IMCR_INTEGRATION_Msk (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/) /*!< ITM IMCR: INTEGRATION Mask */
1021
1022/* ITM Lock Status Register Definitions */
1023#define ITM_LSR_ByteAcc_Pos 2 /*!< ITM LSR: ByteAcc Position */
1024#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */
1025
1026#define ITM_LSR_Access_Pos 1 /*!< ITM LSR: Access Position */
1027#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */
1028
1029#define ITM_LSR_Present_Pos 0 /*!< ITM LSR: Present Position */
1030#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */
1031
1032/*@}*/ /* end of group CMSIS_ITM */
1033
1034
1035/** \ingroup CMSIS_core_register
1036 \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT)
1037 \brief Type definitions for the Data Watchpoint and Trace (DWT)
1038 @{
1039 */
1040
1041/** \brief Structure type to access the Data Watchpoint and Trace Register (DWT).
1042 */
1043typedef struct
1044{
1045 __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */
1046 __IO uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */
1047 __IO uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */
1048 __IO uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */
1049 __IO uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */
1050 __IO uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */
1051 __IO uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */
1052 __I uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */
1053 __IO uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */
1054 __IO uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */
1055 __IO uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */
1056 uint32_t RESERVED0[1];
1057 __IO uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */
1058 __IO uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */
1059 __IO uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */
1060 uint32_t RESERVED1[1];
1061 __IO uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */
1062 __IO uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */
1063 __IO uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */
1064 uint32_t RESERVED2[1];
1065 __IO uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */
1066 __IO uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */
1067 __IO uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */
1068 uint32_t RESERVED3[981];
1069 __O uint32_t LAR; /*!< Offset: 0xFB0 ( W) Lock Access Register */
1070 __I uint32_t LSR; /*!< Offset: 0xFB4 (R ) Lock Status Register */
1071} DWT_Type;
1072
1073/* DWT Control Register Definitions */
1074#define DWT_CTRL_NUMCOMP_Pos 28 /*!< DWT CTRL: NUMCOMP Position */
1075#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */
1076
1077#define DWT_CTRL_NOTRCPKT_Pos 27 /*!< DWT CTRL: NOTRCPKT Position */
1078#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */
1079
1080#define DWT_CTRL_NOEXTTRIG_Pos 26 /*!< DWT CTRL: NOEXTTRIG Position */
1081#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */
1082
1083#define DWT_CTRL_NOCYCCNT_Pos 25 /*!< DWT CTRL: NOCYCCNT Position */
1084#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */
1085
1086#define DWT_CTRL_NOPRFCNT_Pos 24 /*!< DWT CTRL: NOPRFCNT Position */
1087#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */
1088
1089#define DWT_CTRL_CYCEVTENA_Pos 22 /*!< DWT CTRL: CYCEVTENA Position */
1090#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */
1091
1092#define DWT_CTRL_FOLDEVTENA_Pos 21 /*!< DWT CTRL: FOLDEVTENA Position */
1093#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */
1094
1095#define DWT_CTRL_LSUEVTENA_Pos 20 /*!< DWT CTRL: LSUEVTENA Position */
1096#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */
1097
1098#define DWT_CTRL_SLEEPEVTENA_Pos 19 /*!< DWT CTRL: SLEEPEVTENA Position */
1099#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */
1100
1101#define DWT_CTRL_EXCEVTENA_Pos 18 /*!< DWT CTRL: EXCEVTENA Position */
1102#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */
1103
1104#define DWT_CTRL_CPIEVTENA_Pos 17 /*!< DWT CTRL: CPIEVTENA Position */
1105#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */
1106
1107#define DWT_CTRL_EXCTRCENA_Pos 16 /*!< DWT CTRL: EXCTRCENA Position */
1108#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */
1109
1110#define DWT_CTRL_PCSAMPLENA_Pos 12 /*!< DWT CTRL: PCSAMPLENA Position */
1111#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */
1112
1113#define DWT_CTRL_SYNCTAP_Pos 10 /*!< DWT CTRL: SYNCTAP Position */
1114#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */
1115
1116#define DWT_CTRL_CYCTAP_Pos 9 /*!< DWT CTRL: CYCTAP Position */
1117#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */
1118
1119#define DWT_CTRL_POSTINIT_Pos 5 /*!< DWT CTRL: POSTINIT Position */
1120#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */
1121
1122#define DWT_CTRL_POSTPRESET_Pos 1 /*!< DWT CTRL: POSTPRESET Position */
1123#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */
1124
1125#define DWT_CTRL_CYCCNTENA_Pos 0 /*!< DWT CTRL: CYCCNTENA Position */
1126#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */
1127
1128/* DWT CPI Count Register Definitions */
1129#define DWT_CPICNT_CPICNT_Pos 0 /*!< DWT CPICNT: CPICNT Position */
1130#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */
1131
1132/* DWT Exception Overhead Count Register Definitions */
1133#define DWT_EXCCNT_EXCCNT_Pos 0 /*!< DWT EXCCNT: EXCCNT Position */
1134#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */
1135
1136/* DWT Sleep Count Register Definitions */
1137#define DWT_SLEEPCNT_SLEEPCNT_Pos 0 /*!< DWT SLEEPCNT: SLEEPCNT Position */
1138#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */
1139
1140/* DWT LSU Count Register Definitions */
1141#define DWT_LSUCNT_LSUCNT_Pos 0 /*!< DWT LSUCNT: LSUCNT Position */
1142#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */
1143
1144/* DWT Folded-instruction Count Register Definitions */
1145#define DWT_FOLDCNT_FOLDCNT_Pos 0 /*!< DWT FOLDCNT: FOLDCNT Position */
1146#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */
1147
1148/* DWT Comparator Mask Register Definitions */
1149#define DWT_MASK_MASK_Pos 0 /*!< DWT MASK: MASK Position */
1150#define DWT_MASK_MASK_Msk (0x1FUL /*<< DWT_MASK_MASK_Pos*/) /*!< DWT MASK: MASK Mask */
1151
1152/* DWT Comparator Function Register Definitions */
1153#define DWT_FUNCTION_MATCHED_Pos 24 /*!< DWT FUNCTION: MATCHED Position */
1154#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */
1155
1156#define DWT_FUNCTION_DATAVADDR1_Pos 16 /*!< DWT FUNCTION: DATAVADDR1 Position */
1157#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */
1158
1159#define DWT_FUNCTION_DATAVADDR0_Pos 12 /*!< DWT FUNCTION: DATAVADDR0 Position */
1160#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */
1161
1162#define DWT_FUNCTION_DATAVSIZE_Pos 10 /*!< DWT FUNCTION: DATAVSIZE Position */
1163#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */
1164
1165#define DWT_FUNCTION_LNK1ENA_Pos 9 /*!< DWT FUNCTION: LNK1ENA Position */
1166#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */
1167
1168#define DWT_FUNCTION_DATAVMATCH_Pos 8 /*!< DWT FUNCTION: DATAVMATCH Position */
1169#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */
1170
1171#define DWT_FUNCTION_CYCMATCH_Pos 7 /*!< DWT FUNCTION: CYCMATCH Position */
1172#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */
1173
1174#define DWT_FUNCTION_EMITRANGE_Pos 5 /*!< DWT FUNCTION: EMITRANGE Position */
1175#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */
1176
1177#define DWT_FUNCTION_FUNCTION_Pos 0 /*!< DWT FUNCTION: FUNCTION Position */
1178#define DWT_FUNCTION_FUNCTION_Msk (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/) /*!< DWT FUNCTION: FUNCTION Mask */
1179
1180/*@}*/ /* end of group CMSIS_DWT */
1181
1182
1183/** \ingroup CMSIS_core_register
1184 \defgroup CMSIS_TPI Trace Port Interface (TPI)
1185 \brief Type definitions for the Trace Port Interface (TPI)
1186 @{
1187 */
1188
1189/** \brief Structure type to access the Trace Port Interface Register (TPI).
1190 */
1191typedef struct
1192{
1193 __IO uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */
1194 __IO uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */
1195 uint32_t RESERVED0[2];
1196 __IO uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */
1197 uint32_t RESERVED1[55];
1198 __IO uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */
1199 uint32_t RESERVED2[131];
1200 __I uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */
1201 __IO uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */
1202 __I uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */
1203 uint32_t RESERVED3[759];
1204 __I uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER */
1205 __I uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */
1206 __I uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */
1207 uint32_t RESERVED4[1];
1208 __I uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */
1209 __I uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */
1210 __IO uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */
1211 uint32_t RESERVED5[39];
1212 __IO uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */
1213 __IO uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */
1214 uint32_t RESERVED7[8];
1215 __I uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */
1216 __I uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */
1217} TPI_Type;
1218
1219/* TPI Asynchronous Clock Prescaler Register Definitions */
1220#define TPI_ACPR_PRESCALER_Pos 0 /*!< TPI ACPR: PRESCALER Position */
1221#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */
1222
1223/* TPI Selected Pin Protocol Register Definitions */
1224#define TPI_SPPR_TXMODE_Pos 0 /*!< TPI SPPR: TXMODE Position */
1225#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */
1226
1227/* TPI Formatter and Flush Status Register Definitions */
1228#define TPI_FFSR_FtNonStop_Pos 3 /*!< TPI FFSR: FtNonStop Position */
1229#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */
1230
1231#define TPI_FFSR_TCPresent_Pos 2 /*!< TPI FFSR: TCPresent Position */
1232#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */
1233
1234#define TPI_FFSR_FtStopped_Pos 1 /*!< TPI FFSR: FtStopped Position */
1235#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */
1236
1237#define TPI_FFSR_FlInProg_Pos 0 /*!< TPI FFSR: FlInProg Position */
1238#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */
1239
1240/* TPI Formatter and Flush Control Register Definitions */
1241#define TPI_FFCR_TrigIn_Pos 8 /*!< TPI FFCR: TrigIn Position */
1242#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */
1243
1244#define TPI_FFCR_EnFCont_Pos 1 /*!< TPI FFCR: EnFCont Position */
1245#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */
1246
1247/* TPI TRIGGER Register Definitions */
1248#define TPI_TRIGGER_TRIGGER_Pos 0 /*!< TPI TRIGGER: TRIGGER Position */
1249#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */
1250
1251/* TPI Integration ETM Data Register Definitions (FIFO0) */
1252#define TPI_FIFO0_ITM_ATVALID_Pos 29 /*!< TPI FIFO0: ITM_ATVALID Position */
1253#define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */
1254
1255#define TPI_FIFO0_ITM_bytecount_Pos 27 /*!< TPI FIFO0: ITM_bytecount Position */
1256#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */
1257
1258#define TPI_FIFO0_ETM_ATVALID_Pos 26 /*!< TPI FIFO0: ETM_ATVALID Position */
1259#define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */
1260
1261#define TPI_FIFO0_ETM_bytecount_Pos 24 /*!< TPI FIFO0: ETM_bytecount Position */
1262#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */
1263
1264#define TPI_FIFO0_ETM2_Pos 16 /*!< TPI FIFO0: ETM2 Position */
1265#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */
1266
1267#define TPI_FIFO0_ETM1_Pos 8 /*!< TPI FIFO0: ETM1 Position */
1268#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */
1269
1270#define TPI_FIFO0_ETM0_Pos 0 /*!< TPI FIFO0: ETM0 Position */
1271#define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */
1272
1273/* TPI ITATBCTR2 Register Definitions */
1274#define TPI_ITATBCTR2_ATREADY_Pos 0 /*!< TPI ITATBCTR2: ATREADY Position */
1275#define TPI_ITATBCTR2_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY_Pos*/) /*!< TPI ITATBCTR2: ATREADY Mask */
1276
1277/* TPI Integration ITM Data Register Definitions (FIFO1) */
1278#define TPI_FIFO1_ITM_ATVALID_Pos 29 /*!< TPI FIFO1: ITM_ATVALID Position */
1279#define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */
1280
1281#define TPI_FIFO1_ITM_bytecount_Pos 27 /*!< TPI FIFO1: ITM_bytecount Position */
1282#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */
1283
1284#define TPI_FIFO1_ETM_ATVALID_Pos 26 /*!< TPI FIFO1: ETM_ATVALID Position */
1285#define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */
1286
1287#define TPI_FIFO1_ETM_bytecount_Pos 24 /*!< TPI FIFO1: ETM_bytecount Position */
1288#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */
1289
1290#define TPI_FIFO1_ITM2_Pos 16 /*!< TPI FIFO1: ITM2 Position */
1291#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */
1292
1293#define TPI_FIFO1_ITM1_Pos 8 /*!< TPI FIFO1: ITM1 Position */
1294#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */
1295
1296#define TPI_FIFO1_ITM0_Pos 0 /*!< TPI FIFO1: ITM0 Position */
1297#define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */
1298
1299/* TPI ITATBCTR0 Register Definitions */
1300#define TPI_ITATBCTR0_ATREADY_Pos 0 /*!< TPI ITATBCTR0: ATREADY Position */
1301#define TPI_ITATBCTR0_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY_Pos*/) /*!< TPI ITATBCTR0: ATREADY Mask */
1302
1303/* TPI Integration Mode Control Register Definitions */
1304#define TPI_ITCTRL_Mode_Pos 0 /*!< TPI ITCTRL: Mode Position */
1305#define TPI_ITCTRL_Mode_Msk (0x1UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */
1306
1307/* TPI DEVID Register Definitions */
1308#define TPI_DEVID_NRZVALID_Pos 11 /*!< TPI DEVID: NRZVALID Position */
1309#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */
1310
1311#define TPI_DEVID_MANCVALID_Pos 10 /*!< TPI DEVID: MANCVALID Position */
1312#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */
1313
1314#define TPI_DEVID_PTINVALID_Pos 9 /*!< TPI DEVID: PTINVALID Position */
1315#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */
1316
1317#define TPI_DEVID_MinBufSz_Pos 6 /*!< TPI DEVID: MinBufSz Position */
1318#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */
1319
1320#define TPI_DEVID_AsynClkIn_Pos 5 /*!< TPI DEVID: AsynClkIn Position */
1321#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */
1322
1323#define TPI_DEVID_NrTraceInput_Pos 0 /*!< TPI DEVID: NrTraceInput Position */
1324#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */
1325
1326/* TPI DEVTYPE Register Definitions */
1327#define TPI_DEVTYPE_MajorType_Pos 4 /*!< TPI DEVTYPE: MajorType Position */
1328#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */
1329
1330#define TPI_DEVTYPE_SubType_Pos 0 /*!< TPI DEVTYPE: SubType Position */
1331#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */
1332
1333/*@}*/ /* end of group CMSIS_TPI */
1334
1335
1336#if (__MPU_PRESENT == 1)
1337/** \ingroup CMSIS_core_register
1338 \defgroup CMSIS_MPU Memory Protection Unit (MPU)
1339 \brief Type definitions for the Memory Protection Unit (MPU)
1340 @{
1341 */
1342
1343/** \brief Structure type to access the Memory Protection Unit (MPU).
1344 */
1345typedef struct
1346{
1347 __I uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */
1348 __IO uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */
1349 __IO uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */
1350 __IO uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */
1351 __IO uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */
1352 __IO uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */
1353 __IO uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */
1354 __IO uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */
1355 __IO uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */
1356 __IO uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */
1357 __IO uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */
1358} MPU_Type;
1359
1360/* MPU Type Register */
1361#define MPU_TYPE_IREGION_Pos 16 /*!< MPU TYPE: IREGION Position */
1362#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */
1363
1364#define MPU_TYPE_DREGION_Pos 8 /*!< MPU TYPE: DREGION Position */
1365#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */
1366
1367#define MPU_TYPE_SEPARATE_Pos 0 /*!< MPU TYPE: SEPARATE Position */
1368#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */
1369
1370/* MPU Control Register */
1371#define MPU_CTRL_PRIVDEFENA_Pos 2 /*!< MPU CTRL: PRIVDEFENA Position */
1372#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */
1373
1374#define MPU_CTRL_HFNMIENA_Pos 1 /*!< MPU CTRL: HFNMIENA Position */
1375#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */
1376
1377#define MPU_CTRL_ENABLE_Pos 0 /*!< MPU CTRL: ENABLE Position */
1378#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */
1379
1380/* MPU Region Number Register */
1381#define MPU_RNR_REGION_Pos 0 /*!< MPU RNR: REGION Position */
1382#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */
1383
1384/* MPU Region Base Address Register */
1385#define MPU_RBAR_ADDR_Pos 5 /*!< MPU RBAR: ADDR Position */
1386#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */
1387
1388#define MPU_RBAR_VALID_Pos 4 /*!< MPU RBAR: VALID Position */
1389#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */
1390
1391#define MPU_RBAR_REGION_Pos 0 /*!< MPU RBAR: REGION Position */
1392#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */
1393
1394/* MPU Region Attribute and Size Register */
1395#define MPU_RASR_ATTRS_Pos 16 /*!< MPU RASR: MPU Region Attribute field Position */
1396#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */
1397
1398#define MPU_RASR_XN_Pos 28 /*!< MPU RASR: ATTRS.XN Position */
1399#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */
1400
1401#define MPU_RASR_AP_Pos 24 /*!< MPU RASR: ATTRS.AP Position */
1402#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */
1403
1404#define MPU_RASR_TEX_Pos 19 /*!< MPU RASR: ATTRS.TEX Position */
1405#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */
1406
1407#define MPU_RASR_S_Pos 18 /*!< MPU RASR: ATTRS.S Position */
1408#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */
1409
1410#define MPU_RASR_C_Pos 17 /*!< MPU RASR: ATTRS.C Position */
1411#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */
1412
1413#define MPU_RASR_B_Pos 16 /*!< MPU RASR: ATTRS.B Position */
1414#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */
1415
1416#define MPU_RASR_SRD_Pos 8 /*!< MPU RASR: Sub-Region Disable Position */
1417#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */
1418
1419#define MPU_RASR_SIZE_Pos 1 /*!< MPU RASR: Region Size Field Position */
1420#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */
1421
1422#define MPU_RASR_ENABLE_Pos 0 /*!< MPU RASR: Region enable bit Position */
1423#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */
1424
1425/*@} end of group CMSIS_MPU */
1426#endif
1427
1428
1429#if (__FPU_PRESENT == 1)
1430/** \ingroup CMSIS_core_register
1431 \defgroup CMSIS_FPU Floating Point Unit (FPU)
1432 \brief Type definitions for the Floating Point Unit (FPU)
1433 @{
1434 */
1435
1436/** \brief Structure type to access the Floating Point Unit (FPU).
1437 */
1438typedef struct
1439{
1440 uint32_t RESERVED0[1];
1441 __IO uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */
1442 __IO uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */
1443 __IO uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */
1444 __I uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and FP Feature Register 0 */
1445 __I uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and FP Feature Register 1 */
1446 __I uint32_t MVFR2; /*!< Offset: 0x018 (R/ ) Media and FP Feature Register 2 */
1447} FPU_Type;
1448
1449/* Floating-Point Context Control Register */
1450#define FPU_FPCCR_ASPEN_Pos 31 /*!< FPCCR: ASPEN bit Position */
1451#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */
1452
1453#define FPU_FPCCR_LSPEN_Pos 30 /*!< FPCCR: LSPEN Position */
1454#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */
1455
1456#define FPU_FPCCR_MONRDY_Pos 8 /*!< FPCCR: MONRDY Position */
1457#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */
1458
1459#define FPU_FPCCR_BFRDY_Pos 6 /*!< FPCCR: BFRDY Position */
1460#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */
1461
1462#define FPU_FPCCR_MMRDY_Pos 5 /*!< FPCCR: MMRDY Position */
1463#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */
1464
1465#define FPU_FPCCR_HFRDY_Pos 4 /*!< FPCCR: HFRDY Position */
1466#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */
1467
1468#define FPU_FPCCR_THREAD_Pos 3 /*!< FPCCR: processor mode bit Position */
1469#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */
1470
1471#define FPU_FPCCR_USER_Pos 1 /*!< FPCCR: privilege level bit Position */
1472#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */
1473
1474#define FPU_FPCCR_LSPACT_Pos 0 /*!< FPCCR: Lazy state preservation active bit Position */
1475#define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */
1476
1477/* Floating-Point Context Address Register */
1478#define FPU_FPCAR_ADDRESS_Pos 3 /*!< FPCAR: ADDRESS bit Position */
1479#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */
1480
1481/* Floating-Point Default Status Control Register */
1482#define FPU_FPDSCR_AHP_Pos 26 /*!< FPDSCR: AHP bit Position */
1483#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */
1484
1485#define FPU_FPDSCR_DN_Pos 25 /*!< FPDSCR: DN bit Position */
1486#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */
1487
1488#define FPU_FPDSCR_FZ_Pos 24 /*!< FPDSCR: FZ bit Position */
1489#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */
1490
1491#define FPU_FPDSCR_RMode_Pos 22 /*!< FPDSCR: RMode bit Position */
1492#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */
1493
1494/* Media and FP Feature Register 0 */
1495#define FPU_MVFR0_FP_rounding_modes_Pos 28 /*!< MVFR0: FP rounding modes bits Position */
1496#define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */
1497
1498#define FPU_MVFR0_Short_vectors_Pos 24 /*!< MVFR0: Short vectors bits Position */
1499#define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */
1500
1501#define FPU_MVFR0_Square_root_Pos 20 /*!< MVFR0: Square root bits Position */
1502#define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */
1503
1504#define FPU_MVFR0_Divide_Pos 16 /*!< MVFR0: Divide bits Position */
1505#define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */
1506
1507#define FPU_MVFR0_FP_excep_trapping_Pos 12 /*!< MVFR0: FP exception trapping bits Position */
1508#define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */
1509
1510#define FPU_MVFR0_Double_precision_Pos 8 /*!< MVFR0: Double-precision bits Position */
1511#define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */
1512
1513#define FPU_MVFR0_Single_precision_Pos 4 /*!< MVFR0: Single-precision bits Position */
1514#define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */
1515
1516#define FPU_MVFR0_A_SIMD_registers_Pos 0 /*!< MVFR0: A_SIMD registers bits Position */
1517#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/) /*!< MVFR0: A_SIMD registers bits Mask */
1518
1519/* Media and FP Feature Register 1 */
1520#define FPU_MVFR1_FP_fused_MAC_Pos 28 /*!< MVFR1: FP fused MAC bits Position */
1521#define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */
1522
1523#define FPU_MVFR1_FP_HPFP_Pos 24 /*!< MVFR1: FP HPFP bits Position */
1524#define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */
1525
1526#define FPU_MVFR1_D_NaN_mode_Pos 4 /*!< MVFR1: D_NaN mode bits Position */
1527#define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */
1528
1529#define FPU_MVFR1_FtZ_mode_Pos 0 /*!< MVFR1: FtZ mode bits Position */
1530#define FPU_MVFR1_FtZ_mode_Msk (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/) /*!< MVFR1: FtZ mode bits Mask */
1531
1532/* Media and FP Feature Register 2 */
1533
1534/*@} end of group CMSIS_FPU */
1535#endif
1536
1537
1538/** \ingroup CMSIS_core_register
1539 \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
1540 \brief Type definitions for the Core Debug Registers
1541 @{
1542 */
1543
1544/** \brief Structure type to access the Core Debug Register (CoreDebug).
1545 */
1546typedef struct
1547{
1548 __IO uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */
1549 __O uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */
1550 __IO uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */
1551 __IO uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */
1552} CoreDebug_Type;
1553
1554/* Debug Halting Control and Status Register */
1555#define CoreDebug_DHCSR_DBGKEY_Pos 16 /*!< CoreDebug DHCSR: DBGKEY Position */
1556#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */
1557
1558#define CoreDebug_DHCSR_S_RESET_ST_Pos 25 /*!< CoreDebug DHCSR: S_RESET_ST Position */
1559#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */
1560
1561#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24 /*!< CoreDebug DHCSR: S_RETIRE_ST Position */
1562#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */
1563
1564#define CoreDebug_DHCSR_S_LOCKUP_Pos 19 /*!< CoreDebug DHCSR: S_LOCKUP Position */
1565#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */
1566
1567#define CoreDebug_DHCSR_S_SLEEP_Pos 18 /*!< CoreDebug DHCSR: S_SLEEP Position */
1568#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */
1569
1570#define CoreDebug_DHCSR_S_HALT_Pos 17 /*!< CoreDebug DHCSR: S_HALT Position */
1571#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */
1572
1573#define CoreDebug_DHCSR_S_REGRDY_Pos 16 /*!< CoreDebug DHCSR: S_REGRDY Position */
1574#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */
1575
1576#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5 /*!< CoreDebug DHCSR: C_SNAPSTALL Position */
1577#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */
1578
1579#define CoreDebug_DHCSR_C_MASKINTS_Pos 3 /*!< CoreDebug DHCSR: C_MASKINTS Position */
1580#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */
1581
1582#define CoreDebug_DHCSR_C_STEP_Pos 2 /*!< CoreDebug DHCSR: C_STEP Position */
1583#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */
1584
1585#define CoreDebug_DHCSR_C_HALT_Pos 1 /*!< CoreDebug DHCSR: C_HALT Position */
1586#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */
1587
1588#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0 /*!< CoreDebug DHCSR: C_DEBUGEN Position */
1589#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */
1590
1591/* Debug Core Register Selector Register */
1592#define CoreDebug_DCRSR_REGWnR_Pos 16 /*!< CoreDebug DCRSR: REGWnR Position */
1593#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */
1594
1595#define CoreDebug_DCRSR_REGSEL_Pos 0 /*!< CoreDebug DCRSR: REGSEL Position */
1596#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */
1597
1598/* Debug Exception and Monitor Control Register */
1599#define CoreDebug_DEMCR_TRCENA_Pos 24 /*!< CoreDebug DEMCR: TRCENA Position */
1600#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */
1601
1602#define CoreDebug_DEMCR_MON_REQ_Pos 19 /*!< CoreDebug DEMCR: MON_REQ Position */
1603#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */
1604
1605#define CoreDebug_DEMCR_MON_STEP_Pos 18 /*!< CoreDebug DEMCR: MON_STEP Position */
1606#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */
1607
1608#define CoreDebug_DEMCR_MON_PEND_Pos 17 /*!< CoreDebug DEMCR: MON_PEND Position */
1609#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */
1610
1611#define CoreDebug_DEMCR_MON_EN_Pos 16 /*!< CoreDebug DEMCR: MON_EN Position */
1612#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */
1613
1614#define CoreDebug_DEMCR_VC_HARDERR_Pos 10 /*!< CoreDebug DEMCR: VC_HARDERR Position */
1615#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */
1616
1617#define CoreDebug_DEMCR_VC_INTERR_Pos 9 /*!< CoreDebug DEMCR: VC_INTERR Position */
1618#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */
1619
1620#define CoreDebug_DEMCR_VC_BUSERR_Pos 8 /*!< CoreDebug DEMCR: VC_BUSERR Position */
1621#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */
1622
1623#define CoreDebug_DEMCR_VC_STATERR_Pos 7 /*!< CoreDebug DEMCR: VC_STATERR Position */
1624#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */
1625
1626#define CoreDebug_DEMCR_VC_CHKERR_Pos 6 /*!< CoreDebug DEMCR: VC_CHKERR Position */
1627#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */
1628
1629#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5 /*!< CoreDebug DEMCR: VC_NOCPERR Position */
1630#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */
1631
1632#define CoreDebug_DEMCR_VC_MMERR_Pos 4 /*!< CoreDebug DEMCR: VC_MMERR Position */
1633#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */
1634
1635#define CoreDebug_DEMCR_VC_CORERESET_Pos 0 /*!< CoreDebug DEMCR: VC_CORERESET Position */
1636#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */
1637
1638/*@} end of group CMSIS_CoreDebug */
1639
1640
1641/** \ingroup CMSIS_core_register
1642 \defgroup CMSIS_core_base Core Definitions
1643 \brief Definitions for base addresses, unions, and structures.
1644 @{
1645 */
1646
1647/* Memory mapping of Cortex-M4 Hardware */
1648#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
1649#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */
1650#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */
1651#define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */
1652#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */
1653#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
1654#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
1655#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
1656
1657#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */
1658#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
1659#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
1660#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
1661#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */
1662#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */
1663#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */
1664#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */
1665
1666#if (__MPU_PRESENT == 1)
1667 #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */
1668 #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */
1669#endif
1670
1671#if (__FPU_PRESENT == 1)
1672 #define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */
1673 #define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */
1674#endif
1675
1676/*@} */
1677
1678
1679
1680/*******************************************************************************
1681 * Hardware Abstraction Layer
1682 Core Function Interface contains:
1683 - Core NVIC Functions
1684 - Core SysTick Functions
1685 - Core Debug Functions
1686 - Core Register Access Functions
1687 ******************************************************************************/
1688/** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
1689*/
1690
1691
1692
1693/* ########################## NVIC functions #################################### */
1694/** \ingroup CMSIS_Core_FunctionInterface
1695 \defgroup CMSIS_Core_NVICFunctions NVIC Functions
1696 \brief Functions that manage interrupts and exceptions via the NVIC.
1697 @{
1698 */
1699
1700/** \brief Set Priority Grouping
1701
1702 The function sets the priority grouping field using the required unlock sequence.
1703 The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
1704 Only values from 0..7 are used.
1705 In case of a conflict between priority grouping and available
1706 priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
1707
1708 \param [in] PriorityGroup Priority grouping field.
1709 */
1710__STATIC_INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
1711{
1712 uint32_t reg_value;
1713 uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
1714
1715 reg_value = SCB->AIRCR; /* read old register configuration */
1716 reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */
1717 reg_value = (reg_value |
1718 ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
1719 (PriorityGroupTmp << 8) ); /* Insert write key and priorty group */
1720 SCB->AIRCR = reg_value;
1721}
1722
1723
1724/** \brief Get Priority Grouping
1725
1726 The function reads the priority grouping field from the NVIC Interrupt Controller.
1727
1728 \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
1729 */
1730__STATIC_INLINE uint32_t NVIC_GetPriorityGrouping(void)
1731{
1732 return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
1733}
1734
1735
1736/** \brief Enable External Interrupt
1737
1738 The function enables a device-specific interrupt in the NVIC interrupt controller.
1739
1740 \param [in] IRQn External interrupt number. Value cannot be negative.
1741 */
1742__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
1743{
1744 NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
1745}
1746
1747
1748/** \brief Disable External Interrupt
1749
1750 The function disables a device-specific interrupt in the NVIC interrupt controller.
1751
1752 \param [in] IRQn External interrupt number. Value cannot be negative.
1753 */
1754__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
1755{
1756 NVIC->ICER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
1757 __DSB();
1758 __ISB();
1759}
1760
1761
1762/** \brief Get Pending Interrupt
1763
1764 The function reads the pending register in the NVIC and returns the pending bit
1765 for the specified interrupt.
1766
1767 \param [in] IRQn Interrupt number.
1768
1769 \return 0 Interrupt status is not pending.
1770 \return 1 Interrupt status is pending.
1771 */
1772__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
1773{
1774 return((uint32_t)(((NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
1775}
1776
1777
1778/** \brief Set Pending Interrupt
1779
1780 The function sets the pending bit of an external interrupt.
1781
1782 \param [in] IRQn Interrupt number. Value cannot be negative.
1783 */
1784__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
1785{
1786 NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
1787}
1788
1789
1790/** \brief Clear Pending Interrupt
1791
1792 The function clears the pending bit of an external interrupt.
1793
1794 \param [in] IRQn External interrupt number. Value cannot be negative.
1795 */
1796__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
1797{
1798 NVIC->ICPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
1799}
1800
1801
1802/** \brief Get Active Interrupt
1803
1804 The function reads the active register in NVIC and returns the active bit.
1805
1806 \param [in] IRQn Interrupt number.
1807
1808 \return 0 Interrupt status is not active.
1809 \return 1 Interrupt status is active.
1810 */
1811__STATIC_INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn)
1812{
1813 return((uint32_t)(((NVIC->IABR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
1814}
1815
1816
1817/** \brief Set Interrupt Priority
1818
1819 The function sets the priority of an interrupt.
1820
1821 \note The priority cannot be set for every core interrupt.
1822
1823 \param [in] IRQn Interrupt number.
1824 \param [in] priority Priority to set.
1825 */
1826__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
1827{
1828 if((int32_t)IRQn < 0) {
1829 SCB->SHPR[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8 - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
1830 }
1831 else {
1832 NVIC->IP[((uint32_t)(int32_t)IRQn)] = (uint8_t)((priority << (8 - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
1833 }
1834}
1835
1836
1837/** \brief Get Interrupt Priority
1838
1839 The function reads the priority of an interrupt. The interrupt
1840 number can be positive to specify an external (device specific)
1841 interrupt, or negative to specify an internal (core) interrupt.
1842
1843
1844 \param [in] IRQn Interrupt number.
1845 \return Interrupt Priority. Value is aligned automatically to the implemented
1846 priority bits of the microcontroller.
1847 */
1848__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
1849{
1850
1851 if((int32_t)IRQn < 0) {
1852 return(((uint32_t)SCB->SHPR[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] >> (8 - __NVIC_PRIO_BITS)));
1853 }
1854 else {
1855 return(((uint32_t)NVIC->IP[((uint32_t)(int32_t)IRQn)] >> (8 - __NVIC_PRIO_BITS)));
1856 }
1857}
1858
1859
1860/** \brief Encode Priority
1861
1862 The function encodes the priority for an interrupt with the given priority group,
1863 preemptive priority value, and subpriority value.
1864 In case of a conflict between priority grouping and available
1865 priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
1866
1867 \param [in] PriorityGroup Used priority group.
1868 \param [in] PreemptPriority Preemptive priority value (starting from 0).
1869 \param [in] SubPriority Subpriority value (starting from 0).
1870 \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
1871 */
1872__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
1873{
1874 uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
1875 uint32_t PreemptPriorityBits;
1876 uint32_t SubPriorityBits;
1877
1878 PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
1879 SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
1880
1881 return (
1882 ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
1883 ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL)))
1884 );
1885}
1886
1887
1888/** \brief Decode Priority
1889
1890 The function decodes an interrupt priority value with a given priority group to
1891 preemptive priority value and subpriority value.
1892 In case of a conflict between priority grouping and available
1893 priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
1894
1895 \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
1896 \param [in] PriorityGroup Used priority group.
1897 \param [out] pPreemptPriority Preemptive priority value (starting from 0).
1898 \param [out] pSubPriority Subpriority value (starting from 0).
1899 */
1900__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority)
1901{
1902 uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
1903 uint32_t PreemptPriorityBits;
1904 uint32_t SubPriorityBits;
1905
1906 PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
1907 SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
1908
1909 *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);
1910 *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL);
1911}
1912
1913
1914/** \brief System Reset
1915
1916 The function initiates a system reset request to reset the MCU.
1917 */
1918__STATIC_INLINE void NVIC_SystemReset(void)
1919{
1920 __DSB(); /* Ensure all outstanding memory accesses included
1921 buffered write are completed before reset */
1922 SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
1923 (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |
1924 SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */
1925 __DSB(); /* Ensure completion of memory access */
1926 while(1) { __NOP(); } /* wait until reset */
1927}
1928
1929/*@} end of CMSIS_Core_NVICFunctions */
1930
1931
1932/* ########################## FPU functions #################################### */
1933/** \ingroup CMSIS_Core_FunctionInterface
1934 \defgroup CMSIS_Core_FpuFunctions FPU Functions
1935 \brief Function that provides FPU type.
1936 @{
1937 */
1938
1939/**
1940 \fn uint32_t SCB_GetFPUType(void)
1941 \brief get FPU type
1942 \returns
1943 - \b 0: No FPU
1944 - \b 1: Single precision FPU
1945 - \b 2: Double + Single precision FPU
1946 */
1947__STATIC_INLINE uint32_t SCB_GetFPUType(void)
1948{
1949 uint32_t mvfr0;
1950
1951 mvfr0 = SCB->MVFR0;
1952 if ((mvfr0 & 0x00000FF0UL) == 0x220UL) {
1953 return 2UL; // Double + Single precision FPU
1954 } else if ((mvfr0 & 0x00000FF0UL) == 0x020UL) {
1955 return 1UL; // Single precision FPU
1956 } else {
1957 return 0UL; // No FPU
1958 }
1959}
1960
1961
1962/*@} end of CMSIS_Core_FpuFunctions */
1963
1964
1965
1966/* ########################## Cache functions #################################### */
1967/** \ingroup CMSIS_Core_FunctionInterface
1968 \defgroup CMSIS_Core_CacheFunctions Cache Functions
1969 \brief Functions that configure Instruction and Data cache.
1970 @{
1971 */
1972
1973/* Cache Size ID Register Macros */
1974#define CCSIDR_WAYS(x) (((x) & SCB_CCSIDR_ASSOCIATIVITY_Msk) >> SCB_CCSIDR_ASSOCIATIVITY_Pos)
1975#define CCSIDR_SETS(x) (((x) & SCB_CCSIDR_NUMSETS_Msk ) >> SCB_CCSIDR_NUMSETS_Pos )
1976#define CCSIDR_LSSHIFT(x) (((x) & SCB_CCSIDR_LINESIZE_Msk ) /*>> SCB_CCSIDR_LINESIZE_Pos*/ )
1977
1978
1979/** \brief Enable I-Cache
1980
1981 The function turns on I-Cache
1982 */
1983__STATIC_INLINE void SCB_EnableICache (void)
1984{
1985 #if (__ICACHE_PRESENT == 1)
1986 __DSB();
1987 __ISB();
1988 SCB->ICIALLU = 0UL; // invalidate I-Cache
1989 SCB->CCR |= (uint32_t)SCB_CCR_IC_Msk; // enable I-Cache
1990 __DSB();
1991 __ISB();
1992 #endif
1993}
1994
1995
1996/** \brief Disable I-Cache
1997
1998 The function turns off I-Cache
1999 */
2000__STATIC_INLINE void SCB_DisableICache (void)
2001{
2002 #if (__ICACHE_PRESENT == 1)
2003 __DSB();
2004 __ISB();
2005 SCB->CCR &= ~(uint32_t)SCB_CCR_IC_Msk; // disable I-Cache
2006 SCB->ICIALLU = 0UL; // invalidate I-Cache
2007 __DSB();
2008 __ISB();
2009 #endif
2010}
2011
2012
2013/** \brief Invalidate I-Cache
2014
2015 The function invalidates I-Cache
2016 */
2017__STATIC_INLINE void SCB_InvalidateICache (void)
2018{
2019 #if (__ICACHE_PRESENT == 1)
2020 __DSB();
2021 __ISB();
2022 SCB->ICIALLU = 0UL;
2023 __DSB();
2024 __ISB();
2025 #endif
2026}
2027
2028
2029/** \brief Enable D-Cache
2030
2031 The function turns on D-Cache
2032 */
2033__STATIC_INLINE void SCB_EnableDCache (void)
2034{
2035 #if (__DCACHE_PRESENT == 1)
2036 uint32_t ccsidr, sshift, wshift, sw;
2037 uint32_t sets, ways;
2038
2039 SCB->CSSELR = (0UL << 1) | 0UL; // Level 1 data cache
2040 ccsidr = SCB->CCSIDR;
2041 sets = (uint32_t)(CCSIDR_SETS(ccsidr));
2042 sshift = (uint32_t)(CCSIDR_LSSHIFT(ccsidr) + 4UL);
2043 ways = (uint32_t)(CCSIDR_WAYS(ccsidr));
2044 wshift = (uint32_t)((uint32_t)__CLZ(ways) & 0x1FUL);
2045
2046 __DSB();
2047
2048 do { // invalidate D-Cache
2049 uint32_t tmpways = ways;
2050 do {
2051 sw = ((tmpways << wshift) | (sets << sshift));
2052 SCB->DCISW = sw;
2053 } while(tmpways--);
2054 } while(sets--);
2055 __DSB();
2056
2057 SCB->CCR |= (uint32_t)SCB_CCR_DC_Msk; // enable D-Cache
2058
2059 __DSB();
2060 __ISB();
2061 #endif
2062}
2063
2064
2065/** \brief Disable D-Cache
2066
2067 The function turns off D-Cache
2068 */
2069__STATIC_INLINE void SCB_DisableDCache (void)
2070{
2071 #if (__DCACHE_PRESENT == 1)
2072 uint32_t ccsidr, sshift, wshift, sw;
2073 uint32_t sets, ways;
2074
2075 SCB->CSSELR = (0UL << 1) | 0UL; // Level 1 data cache
2076 ccsidr = SCB->CCSIDR;
2077 sets = (uint32_t)(CCSIDR_SETS(ccsidr));
2078 sshift = (uint32_t)(CCSIDR_LSSHIFT(ccsidr) + 4UL);
2079 ways = (uint32_t)(CCSIDR_WAYS(ccsidr));
2080 wshift = (uint32_t)((uint32_t)__CLZ(ways) & 0x1FUL);
2081
2082 __DSB();
2083
2084 SCB->CCR &= ~(uint32_t)SCB_CCR_DC_Msk; // disable D-Cache
2085
2086 do { // clean & invalidate D-Cache
2087 uint32_t tmpways = ways;
2088 do {
2089 sw = ((tmpways << wshift) | (sets << sshift));
2090 SCB->DCCISW = sw;
2091 } while(tmpways--);
2092 } while(sets--);
2093
2094
2095 __DSB();
2096 __ISB();
2097 #endif
2098}
2099
2100
2101/** \brief Invalidate D-Cache
2102
2103 The function invalidates D-Cache
2104 */
2105__STATIC_INLINE void SCB_InvalidateDCache (void)
2106{
2107 #if (__DCACHE_PRESENT == 1)
2108 uint32_t ccsidr, sshift, wshift, sw;
2109 uint32_t sets, ways;
2110
2111 SCB->CSSELR = (0UL << 1) | 0UL; // Level 1 data cache
2112 ccsidr = SCB->CCSIDR;
2113 sets = (uint32_t)(CCSIDR_SETS(ccsidr));
2114 sshift = (uint32_t)(CCSIDR_LSSHIFT(ccsidr) + 4UL);
2115 ways = (uint32_t)(CCSIDR_WAYS(ccsidr));
2116 wshift = (uint32_t)((uint32_t)__CLZ(ways) & 0x1FUL);
2117
2118 __DSB();
2119
2120 do { // invalidate D-Cache
2121 uint32_t tmpways = ways;
2122 do {
2123 sw = ((tmpways << wshift) | (sets << sshift));
2124 SCB->DCISW = sw;
2125 } while(tmpways--);
2126 } while(sets--);
2127
2128 __DSB();
2129 __ISB();
2130 #endif
2131}
2132
2133
2134/** \brief Clean D-Cache
2135
2136 The function cleans D-Cache
2137 */
2138__STATIC_INLINE void SCB_CleanDCache (void)
2139{
2140 #if (__DCACHE_PRESENT == 1)
2141 uint32_t ccsidr, sshift, wshift, sw;
2142 uint32_t sets, ways;
2143
2144 SCB->CSSELR = (0UL << 1) | 0UL; // Level 1 data cache
2145 ccsidr = SCB->CCSIDR;
2146 sets = (uint32_t)(CCSIDR_SETS(ccsidr));
2147 sshift = (uint32_t)(CCSIDR_LSSHIFT(ccsidr) + 4UL);
2148 ways = (uint32_t)(CCSIDR_WAYS(ccsidr));
2149 wshift = (uint32_t)((uint32_t)__CLZ(ways) & 0x1FUL);
2150
2151 __DSB();
2152
2153 do { // clean D-Cache
2154 uint32_t tmpways = ways;
2155 do {
2156 sw = ((tmpways << wshift) | (sets << sshift));
2157 SCB->DCCSW = sw;
2158 } while(tmpways--);
2159 } while(sets--);
2160
2161 __DSB();
2162 __ISB();
2163 #endif
2164}
2165
2166
2167/** \brief Clean & Invalidate D-Cache
2168
2169 The function cleans and Invalidates D-Cache
2170 */
2171__STATIC_INLINE void SCB_CleanInvalidateDCache (void)
2172{
2173 #if (__DCACHE_PRESENT == 1)
2174 uint32_t ccsidr, sshift, wshift, sw;
2175 uint32_t sets, ways;
2176
2177 SCB->CSSELR = (0UL << 1) | 0UL; // Level 1 data cache
2178 ccsidr = SCB->CCSIDR;
2179 sets = (uint32_t)(CCSIDR_SETS(ccsidr));
2180 sshift = (uint32_t)(CCSIDR_LSSHIFT(ccsidr) + 4UL);
2181 ways = (uint32_t)(CCSIDR_WAYS(ccsidr));
2182 wshift = (uint32_t)((uint32_t)__CLZ(ways) & 0x1FUL);
2183
2184 __DSB();
2185
2186 do { // clean & invalidate D-Cache
2187 uint32_t tmpways = ways;
2188 do {
2189 sw = ((tmpways << wshift) | (sets << sshift));
2190 SCB->DCCISW = sw;
2191 } while(tmpways--);
2192 } while(sets--);
2193
2194 __DSB();
2195 __ISB();
2196 #endif
2197}
2198
2199
2200/**
2201 \fn void SCB_InvalidateDCache_by_Addr(volatile uint32_t *addr, int32_t dsize)
2202 \brief D-Cache Invalidate by address
2203 \param[in] addr address (aligned to 32-byte boundary)
2204 \param[in] dsize size of memory block (in number of bytes)
2205*/
2206__STATIC_INLINE void SCB_InvalidateDCache_by_Addr (uint32_t *addr, int32_t dsize)
2207{
2208 #if (__DCACHE_PRESENT == 1)
2209 int32_t op_size = dsize;
2210 uint32_t op_addr = (uint32_t)addr;
2211 uint32_t linesize = 32UL; // in Cortex-M7 size of cache line is fixed to 8 words (32 bytes)
2212
2213 __DSB();
2214
2215 while (op_size > 0) {
2216 SCB->DCIMVAC = op_addr;
2217 op_addr += linesize;
2218 op_size -= (int32_t)linesize;
2219 }
2220
2221 __DSB();
2222 __ISB();
2223 #endif
2224}
2225
2226
2227/**
2228 \fn void SCB_CleanDCache_by_Addr(volatile uint32_t *addr, int32_t dsize)
2229 \brief D-Cache Clean by address
2230 \param[in] addr address (aligned to 32-byte boundary)
2231 \param[in] dsize size of memory block (in number of bytes)
2232*/
2233__STATIC_INLINE void SCB_CleanDCache_by_Addr (uint32_t *addr, int32_t dsize)
2234{
2235 #if (__DCACHE_PRESENT == 1)
2236 int32_t op_size = dsize;
2237 uint32_t op_addr = (uint32_t) addr;
2238 uint32_t linesize = 32UL; // in Cortex-M7 size of cache line is fixed to 8 words (32 bytes)
2239
2240 __DSB();
2241
2242 while (op_size > 0) {
2243 SCB->DCCMVAC = op_addr;
2244 op_addr += linesize;
2245 op_size -= (int32_t)linesize;
2246 }
2247
2248 __DSB();
2249 __ISB();
2250 #endif
2251}
2252
2253
2254/**
2255 \fn void SCB_CleanInvalidateDCache_by_Addr(volatile uint32_t *addr, int32_t dsize)
2256 \brief D-Cache Clean and Invalidate by address
2257 \param[in] addr address (aligned to 32-byte boundary)
2258 \param[in] dsize size of memory block (in number of bytes)
2259*/
2260__STATIC_INLINE void SCB_CleanInvalidateDCache_by_Addr (uint32_t *addr, int32_t dsize)
2261{
2262 #if (__DCACHE_PRESENT == 1)
2263 int32_t op_size = dsize;
2264 uint32_t op_addr = (uint32_t) addr;
2265 uint32_t linesize = 32UL; // in Cortex-M7 size of cache line is fixed to 8 words (32 bytes)
2266
2267 __DSB();
2268
2269 while (op_size > 0) {
2270 SCB->DCCIMVAC = op_addr;
2271 op_addr += linesize;
2272 op_size -= (int32_t)linesize;
2273 }
2274
2275 __DSB();
2276 __ISB();
2277 #endif
2278}
2279
2280
2281/*@} end of CMSIS_Core_CacheFunctions */
2282
2283
2284
2285/* ################################## SysTick function ############################################ */
2286/** \ingroup CMSIS_Core_FunctionInterface
2287 \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
2288 \brief Functions that configure the System.
2289 @{
2290 */
2291
2292#if (__Vendor_SysTickConfig == 0)
2293
2294/** \brief System Tick Configuration
2295
2296 The function initializes the System Timer and its interrupt, and starts the System Tick Timer.
2297 Counter is in free running mode to generate periodic interrupts.
2298
2299 \param [in] ticks Number of ticks between two interrupts.
2300
2301 \return 0 Function succeeded.
2302 \return 1 Function failed.
2303
2304 \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
2305 function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
2306 must contain a vendor-specific implementation of this function.
2307
2308 */
2309__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
2310{
2311 if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) { return (1UL); } /* Reload value impossible */
2312
2313 SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
2314 NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
2315 SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
2316 SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
2317 SysTick_CTRL_TICKINT_Msk |
2318 SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
2319 return (0UL); /* Function successful */
2320}
2321
2322#endif
2323
2324/*@} end of CMSIS_Core_SysTickFunctions */
2325
2326
2327
2328/* ##################################### Debug In/Output function ########################################### */
2329/** \ingroup CMSIS_Core_FunctionInterface
2330 \defgroup CMSIS_core_DebugFunctions ITM Functions
2331 \brief Functions that access the ITM debug interface.
2332 @{
2333 */
2334
2335extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */
2336#define ITM_RXBUFFER_EMPTY 0x5AA55AA5 /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */
2337
2338
2339/** \brief ITM Send Character
2340
2341 The function transmits a character via the ITM channel 0, and
2342 \li Just returns when no debugger is connected that has booked the output.
2343 \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted.
2344
2345 \param [in] ch Character to transmit.
2346
2347 \returns Character to transmit.
2348 */
2349__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)
2350{
2351 if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */
2352 ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */
2353 {
2354 while (ITM->PORT[0].u32 == 0UL) { __NOP(); }
2355 ITM->PORT[0].u8 = (uint8_t)ch;
2356 }
2357 return (ch);
2358}
2359
2360
2361/** \brief ITM Receive Character
2362
2363 The function inputs a character via the external variable \ref ITM_RxBuffer.
2364
2365 \return Received character.
2366 \return -1 No character pending.
2367 */
2368__STATIC_INLINE int32_t ITM_ReceiveChar (void) {
2369 int32_t ch = -1; /* no character available */
2370
2371 if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) {
2372 ch = ITM_RxBuffer;
2373 ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */
2374 }
2375
2376 return (ch);
2377}
2378
2379
2380/** \brief ITM Check Character
2381
2382 The function checks whether a character is pending for reading in the variable \ref ITM_RxBuffer.
2383
2384 \return 0 No character available.
2385 \return 1 Character available.
2386 */
2387__STATIC_INLINE int32_t ITM_CheckChar (void) {
2388
2389 if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) {
2390 return (0); /* no character available */
2391 } else {
2392 return (1); /* character available */
2393 }
2394}
2395
2396/*@} end of CMSIS_core_DebugFunctions */
2397
2398
2399
2400
2401#ifdef __cplusplus
2402}
2403#endif
2404
2405#endif /* __CORE_CM7_H_DEPENDANT */
2406
2407#endif /* __CMSIS_GENERIC */
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