source: asp3_tinet_ecnl_arm/trunk/asp3_dcre/mbed/cmsis/core_cm4_simd.h@ 352

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arm向けASP3版ECNLを追加
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1/**************************************************************************//**
2 * @file core_cm4_simd.h
3 * @brief CMSIS Cortex-M4 SIMD Header File
4 * @version V3.20
5 * @date 25. February 2013
6 *
7 * @note
8 *
9 ******************************************************************************/
10/* Copyright (c) 2009 - 2013 ARM LIMITED
11
12 All rights reserved.
13 Redistribution and use in source and binary forms, with or without
14 modification, are permitted provided that the following conditions are met:
15 - Redistributions of source code must retain the above copyright
16 notice, this list of conditions and the following disclaimer.
17 - Redistributions in binary form must reproduce the above copyright
18 notice, this list of conditions and the following disclaimer in the
19 documentation and/or other materials provided with the distribution.
20 - Neither the name of ARM nor the names of its contributors may be used
21 to endorse or promote products derived from this software without
22 specific prior written permission.
23 *
24 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
25 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
26 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
27 ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
28 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
29 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
30 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
31 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
32 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
33 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
34 POSSIBILITY OF SUCH DAMAGE.
35 ---------------------------------------------------------------------------*/
36
37
38#ifdef __cplusplus
39 extern "C" {
40#endif
41
42#ifndef __CORE_CM4_SIMD_H
43#define __CORE_CM4_SIMD_H
44
45
46/*******************************************************************************
47 * Hardware Abstraction Layer
48 ******************************************************************************/
49
50
51/* ################### Compiler specific Intrinsics ########################### */
52/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics
53 Access to dedicated SIMD instructions
54 @{
55*/
56
57#if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/
58/* ARM armcc specific functions */
59
60/*------ CM4 SIMD Intrinsics -----------------------------------------------------*/
61#define __SADD8 __sadd8
62#define __QADD8 __qadd8
63#define __SHADD8 __shadd8
64#define __UADD8 __uadd8
65#define __UQADD8 __uqadd8
66#define __UHADD8 __uhadd8
67#define __SSUB8 __ssub8
68#define __QSUB8 __qsub8
69#define __SHSUB8 __shsub8
70#define __USUB8 __usub8
71#define __UQSUB8 __uqsub8
72#define __UHSUB8 __uhsub8
73#define __SADD16 __sadd16
74#define __QADD16 __qadd16
75#define __SHADD16 __shadd16
76#define __UADD16 __uadd16
77#define __UQADD16 __uqadd16
78#define __UHADD16 __uhadd16
79#define __SSUB16 __ssub16
80#define __QSUB16 __qsub16
81#define __SHSUB16 __shsub16
82#define __USUB16 __usub16
83#define __UQSUB16 __uqsub16
84#define __UHSUB16 __uhsub16
85#define __SASX __sasx
86#define __QASX __qasx
87#define __SHASX __shasx
88#define __UASX __uasx
89#define __UQASX __uqasx
90#define __UHASX __uhasx
91#define __SSAX __ssax
92#define __QSAX __qsax
93#define __SHSAX __shsax
94#define __USAX __usax
95#define __UQSAX __uqsax
96#define __UHSAX __uhsax
97#define __USAD8 __usad8
98#define __USADA8 __usada8
99#define __SSAT16 __ssat16
100#define __USAT16 __usat16
101#define __UXTB16 __uxtb16
102#define __UXTAB16 __uxtab16
103#define __SXTB16 __sxtb16
104#define __SXTAB16 __sxtab16
105#define __SMUAD __smuad
106#define __SMUADX __smuadx
107#define __SMLAD __smlad
108#define __SMLADX __smladx
109#define __SMLALD __smlald
110#define __SMLALDX __smlaldx
111#define __SMUSD __smusd
112#define __SMUSDX __smusdx
113#define __SMLSD __smlsd
114#define __SMLSDX __smlsdx
115#define __SMLSLD __smlsld
116#define __SMLSLDX __smlsldx
117#define __SEL __sel
118#define __QADD __qadd
119#define __QSUB __qsub
120
121#define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \
122 ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) )
123
124#define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \
125 ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) )
126
127#define __SMMLA(ARG1,ARG2,ARG3) ( (int32_t)((((int64_t)(ARG1) * (ARG2)) + \
128 ((int64_t)(ARG3) << 32) ) >> 32))
129
130/*-- End CM4 SIMD Intrinsics -----------------------------------------------------*/
131
132
133
134#elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/
135/* IAR iccarm specific functions */
136
137/*------ CM4 SIMD Intrinsics -----------------------------------------------------*/
138#include <cmsis_iar.h>
139
140/*-- End CM4 SIMD Intrinsics -----------------------------------------------------*/
141
142
143
144#elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/
145/* TI CCS specific functions */
146
147/*------ CM4 SIMD Intrinsics -----------------------------------------------------*/
148#include <cmsis_ccs.h>
149
150/*-- End CM4 SIMD Intrinsics -----------------------------------------------------*/
151
152
153
154#elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/
155/* GNU gcc specific functions */
156
157/*------ CM4 SIMD Intrinsics -----------------------------------------------------*/
158__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SADD8(uint32_t op1, uint32_t op2)
159{
160 uint32_t result;
161
162 __ASM volatile ("sadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
163 return(result);
164}
165
166__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QADD8(uint32_t op1, uint32_t op2)
167{
168 uint32_t result;
169
170 __ASM volatile ("qadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
171 return(result);
172}
173
174__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHADD8(uint32_t op1, uint32_t op2)
175{
176 uint32_t result;
177
178 __ASM volatile ("shadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
179 return(result);
180}
181
182__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UADD8(uint32_t op1, uint32_t op2)
183{
184 uint32_t result;
185
186 __ASM volatile ("uadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
187 return(result);
188}
189
190__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQADD8(uint32_t op1, uint32_t op2)
191{
192 uint32_t result;
193
194 __ASM volatile ("uqadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
195 return(result);
196}
197
198__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHADD8(uint32_t op1, uint32_t op2)
199{
200 uint32_t result;
201
202 __ASM volatile ("uhadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
203 return(result);
204}
205
206
207__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SSUB8(uint32_t op1, uint32_t op2)
208{
209 uint32_t result;
210
211 __ASM volatile ("ssub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
212 return(result);
213}
214
215__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSUB8(uint32_t op1, uint32_t op2)
216{
217 uint32_t result;
218
219 __ASM volatile ("qsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
220 return(result);
221}
222
223__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHSUB8(uint32_t op1, uint32_t op2)
224{
225 uint32_t result;
226
227 __ASM volatile ("shsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
228 return(result);
229}
230
231__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USUB8(uint32_t op1, uint32_t op2)
232{
233 uint32_t result;
234
235 __ASM volatile ("usub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
236 return(result);
237}
238
239__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQSUB8(uint32_t op1, uint32_t op2)
240{
241 uint32_t result;
242
243 __ASM volatile ("uqsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
244 return(result);
245}
246
247__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHSUB8(uint32_t op1, uint32_t op2)
248{
249 uint32_t result;
250
251 __ASM volatile ("uhsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
252 return(result);
253}
254
255
256__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SADD16(uint32_t op1, uint32_t op2)
257{
258 uint32_t result;
259
260 __ASM volatile ("sadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
261 return(result);
262}
263
264__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QADD16(uint32_t op1, uint32_t op2)
265{
266 uint32_t result;
267
268 __ASM volatile ("qadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
269 return(result);
270}
271
272__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHADD16(uint32_t op1, uint32_t op2)
273{
274 uint32_t result;
275
276 __ASM volatile ("shadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
277 return(result);
278}
279
280__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UADD16(uint32_t op1, uint32_t op2)
281{
282 uint32_t result;
283
284 __ASM volatile ("uadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
285 return(result);
286}
287
288__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQADD16(uint32_t op1, uint32_t op2)
289{
290 uint32_t result;
291
292 __ASM volatile ("uqadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
293 return(result);
294}
295
296__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHADD16(uint32_t op1, uint32_t op2)
297{
298 uint32_t result;
299
300 __ASM volatile ("uhadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
301 return(result);
302}
303
304__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SSUB16(uint32_t op1, uint32_t op2)
305{
306 uint32_t result;
307
308 __ASM volatile ("ssub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
309 return(result);
310}
311
312__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSUB16(uint32_t op1, uint32_t op2)
313{
314 uint32_t result;
315
316 __ASM volatile ("qsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
317 return(result);
318}
319
320__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHSUB16(uint32_t op1, uint32_t op2)
321{
322 uint32_t result;
323
324 __ASM volatile ("shsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
325 return(result);
326}
327
328__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USUB16(uint32_t op1, uint32_t op2)
329{
330 uint32_t result;
331
332 __ASM volatile ("usub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
333 return(result);
334}
335
336__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQSUB16(uint32_t op1, uint32_t op2)
337{
338 uint32_t result;
339
340 __ASM volatile ("uqsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
341 return(result);
342}
343
344__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHSUB16(uint32_t op1, uint32_t op2)
345{
346 uint32_t result;
347
348 __ASM volatile ("uhsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
349 return(result);
350}
351
352__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SASX(uint32_t op1, uint32_t op2)
353{
354 uint32_t result;
355
356 __ASM volatile ("sasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
357 return(result);
358}
359
360__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QASX(uint32_t op1, uint32_t op2)
361{
362 uint32_t result;
363
364 __ASM volatile ("qasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
365 return(result);
366}
367
368__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHASX(uint32_t op1, uint32_t op2)
369{
370 uint32_t result;
371
372 __ASM volatile ("shasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
373 return(result);
374}
375
376__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UASX(uint32_t op1, uint32_t op2)
377{
378 uint32_t result;
379
380 __ASM volatile ("uasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
381 return(result);
382}
383
384__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQASX(uint32_t op1, uint32_t op2)
385{
386 uint32_t result;
387
388 __ASM volatile ("uqasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
389 return(result);
390}
391
392__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHASX(uint32_t op1, uint32_t op2)
393{
394 uint32_t result;
395
396 __ASM volatile ("uhasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
397 return(result);
398}
399
400__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SSAX(uint32_t op1, uint32_t op2)
401{
402 uint32_t result;
403
404 __ASM volatile ("ssax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
405 return(result);
406}
407
408__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSAX(uint32_t op1, uint32_t op2)
409{
410 uint32_t result;
411
412 __ASM volatile ("qsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
413 return(result);
414}
415
416__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHSAX(uint32_t op1, uint32_t op2)
417{
418 uint32_t result;
419
420 __ASM volatile ("shsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
421 return(result);
422}
423
424__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USAX(uint32_t op1, uint32_t op2)
425{
426 uint32_t result;
427
428 __ASM volatile ("usax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
429 return(result);
430}
431
432__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQSAX(uint32_t op1, uint32_t op2)
433{
434 uint32_t result;
435
436 __ASM volatile ("uqsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
437 return(result);
438}
439
440__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHSAX(uint32_t op1, uint32_t op2)
441{
442 uint32_t result;
443
444 __ASM volatile ("uhsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
445 return(result);
446}
447
448__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USAD8(uint32_t op1, uint32_t op2)
449{
450 uint32_t result;
451
452 __ASM volatile ("usad8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
453 return(result);
454}
455
456__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USADA8(uint32_t op1, uint32_t op2, uint32_t op3)
457{
458 uint32_t result;
459
460 __ASM volatile ("usada8 %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
461 return(result);
462}
463
464#define __SSAT16(ARG1,ARG2) \
465({ \
466 uint32_t __RES, __ARG1 = (ARG1); \
467 __ASM ("ssat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \
468 __RES; \
469 })
470
471#define __USAT16(ARG1,ARG2) \
472({ \
473 uint32_t __RES, __ARG1 = (ARG1); \
474 __ASM ("usat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \
475 __RES; \
476 })
477
478__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UXTB16(uint32_t op1)
479{
480 uint32_t result;
481
482 __ASM volatile ("uxtb16 %0, %1" : "=r" (result) : "r" (op1));
483 return(result);
484}
485
486__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UXTAB16(uint32_t op1, uint32_t op2)
487{
488 uint32_t result;
489
490 __ASM volatile ("uxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
491 return(result);
492}
493
494__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SXTB16(uint32_t op1)
495{
496 uint32_t result;
497
498 __ASM volatile ("sxtb16 %0, %1" : "=r" (result) : "r" (op1));
499 return(result);
500}
501
502__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SXTAB16(uint32_t op1, uint32_t op2)
503{
504 uint32_t result;
505
506 __ASM volatile ("sxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
507 return(result);
508}
509
510__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUAD (uint32_t op1, uint32_t op2)
511{
512 uint32_t result;
513
514 __ASM volatile ("smuad %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
515 return(result);
516}
517
518__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUADX (uint32_t op1, uint32_t op2)
519{
520 uint32_t result;
521
522 __ASM volatile ("smuadx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
523 return(result);
524}
525
526__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLAD (uint32_t op1, uint32_t op2, uint32_t op3)
527{
528 uint32_t result;
529
530 __ASM volatile ("smlad %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
531 return(result);
532}
533
534__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLADX (uint32_t op1, uint32_t op2, uint32_t op3)
535{
536 uint32_t result;
537
538 __ASM volatile ("smladx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
539 return(result);
540}
541
542#define __SMLALD(ARG1,ARG2,ARG3) \
543({ \
544 uint32_t __ARG1 = (ARG1), __ARG2 = (ARG2), __ARG3_H = (uint32_t)((uint64_t)(ARG3) >> 32), __ARG3_L = (uint32_t)((uint64_t)(ARG3) & 0xFFFFFFFFUL); \
545 __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (__ARG3_L), "=r" (__ARG3_H) : "r" (__ARG1), "r" (__ARG2), "0" (__ARG3_L), "1" (__ARG3_H) ); \
546 (uint64_t)(((uint64_t)__ARG3_H << 32) | __ARG3_L); \
547 })
548
549#define __SMLALDX(ARG1,ARG2,ARG3) \
550({ \
551 uint32_t __ARG1 = (ARG1), __ARG2 = (ARG2), __ARG3_H = (uint32_t)((uint64_t)(ARG3) >> 32), __ARG3_L = (uint32_t)((uint64_t)(ARG3) & 0xFFFFFFFFUL); \
552 __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (__ARG3_L), "=r" (__ARG3_H) : "r" (__ARG1), "r" (__ARG2), "0" (__ARG3_L), "1" (__ARG3_H) ); \
553 (uint64_t)(((uint64_t)__ARG3_H << 32) | __ARG3_L); \
554 })
555
556__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUSD (uint32_t op1, uint32_t op2)
557{
558 uint32_t result;
559
560 __ASM volatile ("smusd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
561 return(result);
562}
563
564__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUSDX (uint32_t op1, uint32_t op2)
565{
566 uint32_t result;
567
568 __ASM volatile ("smusdx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
569 return(result);
570}
571
572__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLSD (uint32_t op1, uint32_t op2, uint32_t op3)
573{
574 uint32_t result;
575
576 __ASM volatile ("smlsd %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
577 return(result);
578}
579
580__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLSDX (uint32_t op1, uint32_t op2, uint32_t op3)
581{
582 uint32_t result;
583
584 __ASM volatile ("smlsdx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
585 return(result);
586}
587
588#define __SMLSLD(ARG1,ARG2,ARG3) \
589({ \
590 uint32_t __ARG1 = (ARG1), __ARG2 = (ARG2), __ARG3_H = (uint32_t)((ARG3) >> 32), __ARG3_L = (uint32_t)((ARG3) & 0xFFFFFFFFUL); \
591 __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (__ARG3_L), "=r" (__ARG3_H) : "r" (__ARG1), "r" (__ARG2), "0" (__ARG3_L), "1" (__ARG3_H) ); \
592 (uint64_t)(((uint64_t)__ARG3_H << 32) | __ARG3_L); \
593 })
594
595#define __SMLSLDX(ARG1,ARG2,ARG3) \
596({ \
597 uint32_t __ARG1 = (ARG1), __ARG2 = (ARG2), __ARG3_H = (uint32_t)((ARG3) >> 32), __ARG3_L = (uint32_t)((ARG3) & 0xFFFFFFFFUL); \
598 __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (__ARG3_L), "=r" (__ARG3_H) : "r" (__ARG1), "r" (__ARG2), "0" (__ARG3_L), "1" (__ARG3_H) ); \
599 (uint64_t)(((uint64_t)__ARG3_H << 32) | __ARG3_L); \
600 })
601
602__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SEL (uint32_t op1, uint32_t op2)
603{
604 uint32_t result;
605
606 __ASM volatile ("sel %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
607 return(result);
608}
609
610__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QADD(uint32_t op1, uint32_t op2)
611{
612 uint32_t result;
613
614 __ASM volatile ("qadd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
615 return(result);
616}
617
618__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSUB(uint32_t op1, uint32_t op2)
619{
620 uint32_t result;
621
622 __ASM volatile ("qsub %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
623 return(result);
624}
625
626#define __PKHBT(ARG1,ARG2,ARG3) \
627({ \
628 uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \
629 __ASM ("pkhbt %0, %1, %2, lsl %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \
630 __RES; \
631 })
632
633#define __PKHTB(ARG1,ARG2,ARG3) \
634({ \
635 uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \
636 if (ARG3 == 0) \
637 __ASM ("pkhtb %0, %1, %2" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2) ); \
638 else \
639 __ASM ("pkhtb %0, %1, %2, asr %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \
640 __RES; \
641 })
642
643__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3)
644{
645 int32_t result;
646
647 __ASM volatile ("smmla %0, %1, %2, %3" : "=r" (result): "r" (op1), "r" (op2), "r" (op3) );
648 return(result);
649}
650
651/*-- End CM4 SIMD Intrinsics -----------------------------------------------------*/
652
653
654
655#elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/
656/* TASKING carm specific functions */
657
658
659/*------ CM4 SIMD Intrinsics -----------------------------------------------------*/
660/* not yet supported */
661/*-- End CM4 SIMD Intrinsics -----------------------------------------------------*/
662
663
664#endif
665
666/*@} end of group CMSIS_SIMD_intrinsics */
667
668
669#endif /* __CORE_CM4_SIMD_H */
670
671#ifdef __cplusplus
672}
673#endif
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