[352] | 1 | /**************************************************************************//**
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| 2 | * @file core_cm3.h
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| 3 | * @brief CMSIS Cortex-M3 Core Peripheral Access Layer Header File
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| 4 | * @version V4.10
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| 5 | * @date 18. March 2015
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| 6 | *
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| 7 | * @note
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| 8 | *
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| 9 | ******************************************************************************/
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| 10 | /* Copyright (c) 2009 - 2015 ARM LIMITED
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| 11 |
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| 12 | All rights reserved.
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| 13 | Redistribution and use in source and binary forms, with or without
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| 14 | modification, are permitted provided that the following conditions are met:
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| 15 | - Redistributions of source code must retain the above copyright
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| 16 | notice, this list of conditions and the following disclaimer.
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| 17 | - Redistributions in binary form must reproduce the above copyright
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| 18 | notice, this list of conditions and the following disclaimer in the
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| 19 | documentation and/or other materials provided with the distribution.
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| 20 | - Neither the name of ARM nor the names of its contributors may be used
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| 21 | to endorse or promote products derived from this software without
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| 22 | specific prior written permission.
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| 23 | *
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| 24 | THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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| 25 | AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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| 26 | IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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| 27 | ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
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| 28 | LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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| 29 | CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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| 30 | SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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| 31 | INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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| 32 | CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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| 33 | ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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| 34 | POSSIBILITY OF SUCH DAMAGE.
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| 35 | ---------------------------------------------------------------------------*/
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| 36 |
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| 37 |
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| 38 | #if defined ( __ICCARM__ )
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| 39 | #pragma system_include /* treat file as system include file for MISRA check */
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| 40 | #endif
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| 41 |
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| 42 | #ifndef __CORE_CM3_H_GENERIC
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| 43 | #define __CORE_CM3_H_GENERIC
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| 44 |
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| 45 | #ifdef __cplusplus
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| 46 | extern "C" {
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| 47 | #endif
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| 48 |
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| 49 | /** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
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| 50 | CMSIS violates the following MISRA-C:2004 rules:
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| 51 |
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| 52 | \li Required Rule 8.5, object/function definition in header file.<br>
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| 53 | Function definitions in header files are used to allow 'inlining'.
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| 54 |
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| 55 | \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
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| 56 | Unions are used for effective representation of core registers.
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| 57 |
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| 58 | \li Advisory Rule 19.7, Function-like macro defined.<br>
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| 59 | Function-like macros are used to allow more efficient code.
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| 60 | */
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| 61 |
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| 62 |
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| 63 | /*******************************************************************************
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| 64 | * CMSIS definitions
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| 65 | ******************************************************************************/
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| 66 | /** \ingroup Cortex_M3
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| 67 | @{
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| 68 | */
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| 69 |
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| 70 | /* CMSIS CM3 definitions */
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| 71 | #define __CM3_CMSIS_VERSION_MAIN (0x04) /*!< [31:16] CMSIS HAL main version */
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| 72 | #define __CM3_CMSIS_VERSION_SUB (0x00) /*!< [15:0] CMSIS HAL sub version */
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| 73 | #define __CM3_CMSIS_VERSION ((__CM3_CMSIS_VERSION_MAIN << 16) | \
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| 74 | __CM3_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */
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| 75 |
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| 76 | #define __CORTEX_M (0x03) /*!< Cortex-M Core */
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| 77 |
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| 78 |
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| 79 | #if defined ( __CC_ARM )
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| 80 | #define __ASM __asm /*!< asm keyword for ARM Compiler */
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| 81 | #define __INLINE __inline /*!< inline keyword for ARM Compiler */
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| 82 | #define __STATIC_INLINE static __inline
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| 83 |
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| 84 | #elif defined ( __GNUC__ )
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| 85 | #define __ASM __asm /*!< asm keyword for GNU Compiler */
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| 86 | #define __INLINE inline /*!< inline keyword for GNU Compiler */
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| 87 | #define __STATIC_INLINE static inline
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| 88 |
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| 89 | #elif defined ( __ICCARM__ )
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| 90 | #define __ASM __asm /*!< asm keyword for IAR Compiler */
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| 91 | #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */
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| 92 | #define __STATIC_INLINE static inline
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| 93 |
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| 94 | #elif defined ( __TMS470__ )
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| 95 | #define __ASM __asm /*!< asm keyword for TI CCS Compiler */
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| 96 | #define __STATIC_INLINE static inline
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| 97 |
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| 98 | #elif defined ( __TASKING__ )
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| 99 | #define __ASM __asm /*!< asm keyword for TASKING Compiler */
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| 100 | #define __INLINE inline /*!< inline keyword for TASKING Compiler */
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| 101 | #define __STATIC_INLINE static inline
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| 102 |
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| 103 | #elif defined ( __CSMC__ )
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| 104 | #define __packed
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| 105 | #define __ASM _asm /*!< asm keyword for COSMIC Compiler */
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| 106 | #define __INLINE inline /*use -pc99 on compile line !< inline keyword for COSMIC Compiler */
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| 107 | #define __STATIC_INLINE static inline
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| 108 |
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| 109 | #endif
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| 110 |
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| 111 | /** __FPU_USED indicates whether an FPU is used or not.
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| 112 | This core does not support an FPU at all
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| 113 | */
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| 114 | #define __FPU_USED 0
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| 115 |
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| 116 | #if defined ( __CC_ARM )
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| 117 | #if defined __TARGET_FPU_VFP
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| 118 | #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
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| 119 | #endif
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| 120 |
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| 121 | #elif defined ( __GNUC__ )
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| 122 | #if defined (__VFP_FP__) && !defined(__SOFTFP__)
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| 123 | #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
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| 124 | #endif
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| 125 |
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| 126 | #elif defined ( __ICCARM__ )
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| 127 | #if defined __ARMVFP__
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| 128 | #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
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| 129 | #endif
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| 130 |
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| 131 | #elif defined ( __TMS470__ )
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| 132 | #if defined __TI__VFP_SUPPORT____
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| 133 | #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
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| 134 | #endif
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| 135 |
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| 136 | #elif defined ( __TASKING__ )
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| 137 | #if defined __FPU_VFP__
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| 138 | #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
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| 139 | #endif
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| 140 |
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| 141 | #elif defined ( __CSMC__ ) /* Cosmic */
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| 142 | #if ( __CSMC__ & 0x400) // FPU present for parser
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| 143 | #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
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| 144 | #endif
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| 145 | #endif
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| 146 |
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| 147 | #include <stdint.h> /* standard types definitions */
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| 148 | #include <core_cmInstr.h> /* Core Instruction Access */
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| 149 | #include <core_cmFunc.h> /* Core Function Access */
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| 150 |
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| 151 | #ifdef __cplusplus
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| 152 | }
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| 153 | #endif
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| 154 |
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| 155 | #endif /* __CORE_CM3_H_GENERIC */
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| 156 |
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| 157 | #ifndef __CMSIS_GENERIC
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| 158 |
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| 159 | #ifndef __CORE_CM3_H_DEPENDANT
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| 160 | #define __CORE_CM3_H_DEPENDANT
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| 161 |
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| 162 | #ifdef __cplusplus
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| 163 | extern "C" {
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| 164 | #endif
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| 165 |
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| 166 | /* check device defines and use defaults */
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| 167 | #if defined __CHECK_DEVICE_DEFINES
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| 168 | #ifndef __CM3_REV
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| 169 | #define __CM3_REV 0x0200
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| 170 | #warning "__CM3_REV not defined in device header file; using default!"
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| 171 | #endif
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| 172 |
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| 173 | #ifndef __MPU_PRESENT
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| 174 | #define __MPU_PRESENT 0
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| 175 | #warning "__MPU_PRESENT not defined in device header file; using default!"
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| 176 | #endif
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| 177 |
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| 178 | #ifndef __NVIC_PRIO_BITS
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| 179 | #define __NVIC_PRIO_BITS 4
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| 180 | #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
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| 181 | #endif
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| 182 |
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| 183 | #ifndef __Vendor_SysTickConfig
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| 184 | #define __Vendor_SysTickConfig 0
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| 185 | #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
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| 186 | #endif
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| 187 | #endif
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| 188 |
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| 189 | /* IO definitions (access restrictions to peripheral registers) */
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| 190 | /**
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| 191 | \defgroup CMSIS_glob_defs CMSIS Global Defines
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| 192 |
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| 193 | <strong>IO Type Qualifiers</strong> are used
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| 194 | \li to specify the access to peripheral variables.
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| 195 | \li for automatic generation of peripheral register debug information.
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| 196 | */
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| 197 | #ifdef __cplusplus
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| 198 | #define __I volatile /*!< Defines 'read only' permissions */
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| 199 | #else
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| 200 | #define __I volatile const /*!< Defines 'read only' permissions */
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| 201 | #endif
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| 202 | #define __O volatile /*!< Defines 'write only' permissions */
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| 203 | #define __IO volatile /*!< Defines 'read / write' permissions */
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| 204 |
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| 205 | #ifdef __cplusplus
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| 206 | #define __IM volatile /*!< Defines 'read only' permissions */
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| 207 | #else
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| 208 | #define __IM volatile const /*!< Defines 'read only' permissions */
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| 209 | #endif
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| 210 | #define __OM volatile /*!< Defines 'write only' permissions */
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| 211 | #define __IOM volatile /*!< Defines 'read / write' permissions */
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| 212 |
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| 213 | /*@} end of group Cortex_M3 */
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| 214 |
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| 215 |
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| 216 |
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| 217 | /*******************************************************************************
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| 218 | * Register Abstraction
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| 219 | Core Register contain:
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| 220 | - Core Register
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| 221 | - Core NVIC Register
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| 222 | - Core SCB Register
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| 223 | - Core SysTick Register
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| 224 | - Core Debug Register
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| 225 | - Core MPU Register
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| 226 | ******************************************************************************/
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| 227 | /** \defgroup CMSIS_core_register Defines and Type Definitions
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| 228 | \brief Type definitions and defines for Cortex-M processor based devices.
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| 229 | */
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| 230 |
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| 231 | /** \ingroup CMSIS_core_register
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| 232 | \defgroup CMSIS_CORE Status and Control Registers
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| 233 | \brief Core Register type definitions.
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| 234 | @{
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| 235 | */
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| 236 |
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| 237 | /** \brief Union type to access the Application Program Status Register (APSR).
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| 238 | */
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| 239 | typedef union
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| 240 | {
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| 241 | struct
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| 242 | {
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| 243 | uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */
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| 244 | uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
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| 245 | uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
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| 246 | uint32_t C:1; /*!< bit: 29 Carry condition code flag */
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| 247 | uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
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| 248 | uint32_t N:1; /*!< bit: 31 Negative condition code flag */
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| 249 | } b; /*!< Structure used for bit access */
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| 250 | uint32_t w; /*!< Type used for word access */
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| 251 | } APSR_Type;
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| 252 |
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| 253 | /* APSR Register Definitions */
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| 254 | #define APSR_N_Pos 31 /*!< APSR: N Position */
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| 255 | #define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */
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| 256 |
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| 257 | #define APSR_Z_Pos 30 /*!< APSR: Z Position */
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| 258 | #define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */
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| 259 |
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| 260 | #define APSR_C_Pos 29 /*!< APSR: C Position */
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| 261 | #define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */
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| 262 |
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| 263 | #define APSR_V_Pos 28 /*!< APSR: V Position */
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| 264 | #define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */
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| 265 |
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| 266 | #define APSR_Q_Pos 27 /*!< APSR: Q Position */
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| 267 | #define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */
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| 268 |
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| 269 |
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| 270 | /** \brief Union type to access the Interrupt Program Status Register (IPSR).
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| 271 | */
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| 272 | typedef union
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| 273 | {
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| 274 | struct
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| 275 | {
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| 276 | uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
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| 277 | uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
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| 278 | } b; /*!< Structure used for bit access */
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| 279 | uint32_t w; /*!< Type used for word access */
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| 280 | } IPSR_Type;
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| 281 |
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| 282 | /* IPSR Register Definitions */
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| 283 | #define IPSR_ISR_Pos 0 /*!< IPSR: ISR Position */
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| 284 | #define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */
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| 285 |
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| 286 |
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| 287 | /** \brief Union type to access the Special-Purpose Program Status Registers (xPSR).
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| 288 | */
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| 289 | typedef union
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| 290 | {
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| 291 | struct
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| 292 | {
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| 293 | uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
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| 294 | uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */
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| 295 | uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */
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| 296 | uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */
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| 297 | uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
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| 298 | uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
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| 299 | uint32_t C:1; /*!< bit: 29 Carry condition code flag */
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| 300 | uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
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| 301 | uint32_t N:1; /*!< bit: 31 Negative condition code flag */
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| 302 | } b; /*!< Structure used for bit access */
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| 303 | uint32_t w; /*!< Type used for word access */
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| 304 | } xPSR_Type;
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| 305 |
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| 306 | /* xPSR Register Definitions */
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| 307 | #define xPSR_N_Pos 31 /*!< xPSR: N Position */
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| 308 | #define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */
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| 309 |
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| 310 | #define xPSR_Z_Pos 30 /*!< xPSR: Z Position */
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| 311 | #define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */
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| 312 |
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| 313 | #define xPSR_C_Pos 29 /*!< xPSR: C Position */
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| 314 | #define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */
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| 315 |
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| 316 | #define xPSR_V_Pos 28 /*!< xPSR: V Position */
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| 317 | #define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */
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| 318 |
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| 319 | #define xPSR_Q_Pos 27 /*!< xPSR: Q Position */
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| 320 | #define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */
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| 321 |
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| 322 | #define xPSR_IT_Pos 25 /*!< xPSR: IT Position */
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| 323 | #define xPSR_IT_Msk (3UL << xPSR_IT_Pos) /*!< xPSR: IT Mask */
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| 324 |
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| 325 | #define xPSR_T_Pos 24 /*!< xPSR: T Position */
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| 326 | #define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */
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| 327 |
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| 328 | #define xPSR_ISR_Pos 0 /*!< xPSR: ISR Position */
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| 329 | #define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */
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| 330 |
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| 331 |
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| 332 | /** \brief Union type to access the Control Registers (CONTROL).
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| 333 | */
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| 334 | typedef union
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| 335 | {
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| 336 | struct
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| 337 | {
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| 338 | uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */
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| 339 | uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */
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| 340 | uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */
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| 341 | } b; /*!< Structure used for bit access */
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| 342 | uint32_t w; /*!< Type used for word access */
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| 343 | } CONTROL_Type;
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| 344 |
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| 345 | /* CONTROL Register Definitions */
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| 346 | #define CONTROL_SPSEL_Pos 1 /*!< CONTROL: SPSEL Position */
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| 347 | #define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */
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| 348 |
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| 349 | #define CONTROL_nPRIV_Pos 0 /*!< CONTROL: nPRIV Position */
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| 350 | #define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */
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| 351 |
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| 352 | /*@} end of group CMSIS_CORE */
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| 353 |
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| 354 |
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| 355 | /** \ingroup CMSIS_core_register
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| 356 | \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
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| 357 | \brief Type definitions for the NVIC Registers
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| 358 | @{
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| 359 | */
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| 360 |
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| 361 | /** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
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| 362 | */
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| 363 | typedef struct
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| 364 | {
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| 365 | __IO uint32_t ISER[8]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
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| 366 | uint32_t RESERVED0[24];
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| 367 | __IO uint32_t ICER[8]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
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| 368 | uint32_t RSERVED1[24];
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| 369 | __IO uint32_t ISPR[8]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
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| 370 | uint32_t RESERVED2[24];
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| 371 | __IO uint32_t ICPR[8]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
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| 372 | uint32_t RESERVED3[24];
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| 373 | __IO uint32_t IABR[8]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */
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| 374 | uint32_t RESERVED4[56];
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| 375 | __IO uint8_t IP[240]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */
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| 376 | uint32_t RESERVED5[644];
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| 377 | __O uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */
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| 378 | } NVIC_Type;
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| 379 |
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| 380 | /* Software Triggered Interrupt Register Definitions */
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| 381 | #define NVIC_STIR_INTID_Pos 0 /*!< STIR: INTLINESNUM Position */
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| 382 | #define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */
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| 383 |
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| 384 | /*@} end of group CMSIS_NVIC */
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| 385 |
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| 386 |
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| 387 | /** \ingroup CMSIS_core_register
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| 388 | \defgroup CMSIS_SCB System Control Block (SCB)
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| 389 | \brief Type definitions for the System Control Block Registers
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| 390 | @{
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| 391 | */
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| 392 |
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| 393 | /** \brief Structure type to access the System Control Block (SCB).
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| 394 | */
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| 395 | typedef struct
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| 396 | {
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| 397 | __I uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
|
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| 398 | __IO uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
|
---|
| 399 | __IO uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */
|
---|
| 400 | __IO uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
|
---|
| 401 | __IO uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
|
---|
| 402 | __IO uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
|
---|
| 403 | __IO uint8_t SHP[12]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */
|
---|
| 404 | __IO uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
|
---|
| 405 | __IO uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */
|
---|
| 406 | __IO uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */
|
---|
| 407 | __IO uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */
|
---|
| 408 | __IO uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */
|
---|
| 409 | __IO uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */
|
---|
| 410 | __IO uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */
|
---|
| 411 | __I uint32_t PFR[2]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */
|
---|
| 412 | __I uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */
|
---|
| 413 | __I uint32_t ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */
|
---|
| 414 | __I uint32_t MMFR[4]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */
|
---|
| 415 | __I uint32_t ISAR[5]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */
|
---|
| 416 | uint32_t RESERVED0[5];
|
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| 417 | __IO uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */
|
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| 418 | } SCB_Type;
|
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| 419 |
|
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| 420 | /* SCB CPUID Register Definitions */
|
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| 421 | #define SCB_CPUID_IMPLEMENTER_Pos 24 /*!< SCB CPUID: IMPLEMENTER Position */
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| 422 | #define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
|
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| 423 |
|
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| 424 | #define SCB_CPUID_VARIANT_Pos 20 /*!< SCB CPUID: VARIANT Position */
|
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| 425 | #define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
|
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| 426 |
|
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| 427 | #define SCB_CPUID_ARCHITECTURE_Pos 16 /*!< SCB CPUID: ARCHITECTURE Position */
|
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| 428 | #define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
|
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| 429 |
|
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| 430 | #define SCB_CPUID_PARTNO_Pos 4 /*!< SCB CPUID: PARTNO Position */
|
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| 431 | #define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
|
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| 432 |
|
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| 433 | #define SCB_CPUID_REVISION_Pos 0 /*!< SCB CPUID: REVISION Position */
|
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| 434 | #define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */
|
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| 435 |
|
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| 436 | /* SCB Interrupt Control State Register Definitions */
|
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| 437 | #define SCB_ICSR_NMIPENDSET_Pos 31 /*!< SCB ICSR: NMIPENDSET Position */
|
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| 438 | #define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */
|
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| 439 |
|
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| 440 | #define SCB_ICSR_PENDSVSET_Pos 28 /*!< SCB ICSR: PENDSVSET Position */
|
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| 441 | #define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
|
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| 442 |
|
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| 443 | #define SCB_ICSR_PENDSVCLR_Pos 27 /*!< SCB ICSR: PENDSVCLR Position */
|
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| 444 | #define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
|
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| 445 |
|
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| 446 | #define SCB_ICSR_PENDSTSET_Pos 26 /*!< SCB ICSR: PENDSTSET Position */
|
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| 447 | #define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
|
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| 448 |
|
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| 449 | #define SCB_ICSR_PENDSTCLR_Pos 25 /*!< SCB ICSR: PENDSTCLR Position */
|
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| 450 | #define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
|
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| 451 |
|
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| 452 | #define SCB_ICSR_ISRPREEMPT_Pos 23 /*!< SCB ICSR: ISRPREEMPT Position */
|
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| 453 | #define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
|
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| 454 |
|
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| 455 | #define SCB_ICSR_ISRPENDING_Pos 22 /*!< SCB ICSR: ISRPENDING Position */
|
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| 456 | #define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
|
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| 457 |
|
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| 458 | #define SCB_ICSR_VECTPENDING_Pos 12 /*!< SCB ICSR: VECTPENDING Position */
|
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| 459 | #define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
|
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| 460 |
|
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| 461 | #define SCB_ICSR_RETTOBASE_Pos 11 /*!< SCB ICSR: RETTOBASE Position */
|
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| 462 | #define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */
|
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| 463 |
|
---|
| 464 | #define SCB_ICSR_VECTACTIVE_Pos 0 /*!< SCB ICSR: VECTACTIVE Position */
|
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| 465 | #define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */
|
---|
| 466 |
|
---|
| 467 | /* SCB Vector Table Offset Register Definitions */
|
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| 468 | #if (__CM3_REV < 0x0201) /* core r2p1 */
|
---|
| 469 | #define SCB_VTOR_TBLBASE_Pos 29 /*!< SCB VTOR: TBLBASE Position */
|
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| 470 | #define SCB_VTOR_TBLBASE_Msk (1UL << SCB_VTOR_TBLBASE_Pos) /*!< SCB VTOR: TBLBASE Mask */
|
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| 471 |
|
---|
| 472 | #define SCB_VTOR_TBLOFF_Pos 7 /*!< SCB VTOR: TBLOFF Position */
|
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| 473 | #define SCB_VTOR_TBLOFF_Msk (0x3FFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */
|
---|
| 474 | #else
|
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| 475 | #define SCB_VTOR_TBLOFF_Pos 7 /*!< SCB VTOR: TBLOFF Position */
|
---|
| 476 | #define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */
|
---|
| 477 | #endif
|
---|
| 478 |
|
---|
| 479 | /* SCB Application Interrupt and Reset Control Register Definitions */
|
---|
| 480 | #define SCB_AIRCR_VECTKEY_Pos 16 /*!< SCB AIRCR: VECTKEY Position */
|
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| 481 | #define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
|
---|
| 482 |
|
---|
| 483 | #define SCB_AIRCR_VECTKEYSTAT_Pos 16 /*!< SCB AIRCR: VECTKEYSTAT Position */
|
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| 484 | #define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
|
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| 485 |
|
---|
| 486 | #define SCB_AIRCR_ENDIANESS_Pos 15 /*!< SCB AIRCR: ENDIANESS Position */
|
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| 487 | #define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
|
---|
| 488 |
|
---|
| 489 | #define SCB_AIRCR_PRIGROUP_Pos 8 /*!< SCB AIRCR: PRIGROUP Position */
|
---|
| 490 | #define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */
|
---|
| 491 |
|
---|
| 492 | #define SCB_AIRCR_SYSRESETREQ_Pos 2 /*!< SCB AIRCR: SYSRESETREQ Position */
|
---|
| 493 | #define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
|
---|
| 494 |
|
---|
| 495 | #define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /*!< SCB AIRCR: VECTCLRACTIVE Position */
|
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| 496 | #define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
|
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| 497 |
|
---|
| 498 | #define SCB_AIRCR_VECTRESET_Pos 0 /*!< SCB AIRCR: VECTRESET Position */
|
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| 499 | #define SCB_AIRCR_VECTRESET_Msk (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/) /*!< SCB AIRCR: VECTRESET Mask */
|
---|
| 500 |
|
---|
| 501 | /* SCB System Control Register Definitions */
|
---|
| 502 | #define SCB_SCR_SEVONPEND_Pos 4 /*!< SCB SCR: SEVONPEND Position */
|
---|
| 503 | #define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
|
---|
| 504 |
|
---|
| 505 | #define SCB_SCR_SLEEPDEEP_Pos 2 /*!< SCB SCR: SLEEPDEEP Position */
|
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| 506 | #define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
|
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| 507 |
|
---|
| 508 | #define SCB_SCR_SLEEPONEXIT_Pos 1 /*!< SCB SCR: SLEEPONEXIT Position */
|
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| 509 | #define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
|
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| 510 |
|
---|
| 511 | /* SCB Configuration Control Register Definitions */
|
---|
| 512 | #define SCB_CCR_STKALIGN_Pos 9 /*!< SCB CCR: STKALIGN Position */
|
---|
| 513 | #define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */
|
---|
| 514 |
|
---|
| 515 | #define SCB_CCR_BFHFNMIGN_Pos 8 /*!< SCB CCR: BFHFNMIGN Position */
|
---|
| 516 | #define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */
|
---|
| 517 |
|
---|
| 518 | #define SCB_CCR_DIV_0_TRP_Pos 4 /*!< SCB CCR: DIV_0_TRP Position */
|
---|
| 519 | #define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */
|
---|
| 520 |
|
---|
| 521 | #define SCB_CCR_UNALIGN_TRP_Pos 3 /*!< SCB CCR: UNALIGN_TRP Position */
|
---|
| 522 | #define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
|
---|
| 523 |
|
---|
| 524 | #define SCB_CCR_USERSETMPEND_Pos 1 /*!< SCB CCR: USERSETMPEND Position */
|
---|
| 525 | #define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */
|
---|
| 526 |
|
---|
| 527 | #define SCB_CCR_NONBASETHRDENA_Pos 0 /*!< SCB CCR: NONBASETHRDENA Position */
|
---|
| 528 | #define SCB_CCR_NONBASETHRDENA_Msk (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/) /*!< SCB CCR: NONBASETHRDENA Mask */
|
---|
| 529 |
|
---|
| 530 | /* SCB System Handler Control and State Register Definitions */
|
---|
| 531 | #define SCB_SHCSR_USGFAULTENA_Pos 18 /*!< SCB SHCSR: USGFAULTENA Position */
|
---|
| 532 | #define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */
|
---|
| 533 |
|
---|
| 534 | #define SCB_SHCSR_BUSFAULTENA_Pos 17 /*!< SCB SHCSR: BUSFAULTENA Position */
|
---|
| 535 | #define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */
|
---|
| 536 |
|
---|
| 537 | #define SCB_SHCSR_MEMFAULTENA_Pos 16 /*!< SCB SHCSR: MEMFAULTENA Position */
|
---|
| 538 | #define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */
|
---|
| 539 |
|
---|
| 540 | #define SCB_SHCSR_SVCALLPENDED_Pos 15 /*!< SCB SHCSR: SVCALLPENDED Position */
|
---|
| 541 | #define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
|
---|
| 542 |
|
---|
| 543 | #define SCB_SHCSR_BUSFAULTPENDED_Pos 14 /*!< SCB SHCSR: BUSFAULTPENDED Position */
|
---|
| 544 | #define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */
|
---|
| 545 |
|
---|
| 546 | #define SCB_SHCSR_MEMFAULTPENDED_Pos 13 /*!< SCB SHCSR: MEMFAULTPENDED Position */
|
---|
| 547 | #define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */
|
---|
| 548 |
|
---|
| 549 | #define SCB_SHCSR_USGFAULTPENDED_Pos 12 /*!< SCB SHCSR: USGFAULTPENDED Position */
|
---|
| 550 | #define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */
|
---|
| 551 |
|
---|
| 552 | #define SCB_SHCSR_SYSTICKACT_Pos 11 /*!< SCB SHCSR: SYSTICKACT Position */
|
---|
| 553 | #define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */
|
---|
| 554 |
|
---|
| 555 | #define SCB_SHCSR_PENDSVACT_Pos 10 /*!< SCB SHCSR: PENDSVACT Position */
|
---|
| 556 | #define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */
|
---|
| 557 |
|
---|
| 558 | #define SCB_SHCSR_MONITORACT_Pos 8 /*!< SCB SHCSR: MONITORACT Position */
|
---|
| 559 | #define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */
|
---|
| 560 |
|
---|
| 561 | #define SCB_SHCSR_SVCALLACT_Pos 7 /*!< SCB SHCSR: SVCALLACT Position */
|
---|
| 562 | #define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */
|
---|
| 563 |
|
---|
| 564 | #define SCB_SHCSR_USGFAULTACT_Pos 3 /*!< SCB SHCSR: USGFAULTACT Position */
|
---|
| 565 | #define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */
|
---|
| 566 |
|
---|
| 567 | #define SCB_SHCSR_BUSFAULTACT_Pos 1 /*!< SCB SHCSR: BUSFAULTACT Position */
|
---|
| 568 | #define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */
|
---|
| 569 |
|
---|
| 570 | #define SCB_SHCSR_MEMFAULTACT_Pos 0 /*!< SCB SHCSR: MEMFAULTACT Position */
|
---|
| 571 | #define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */
|
---|
| 572 |
|
---|
| 573 | /* SCB Configurable Fault Status Registers Definitions */
|
---|
| 574 | #define SCB_CFSR_USGFAULTSR_Pos 16 /*!< SCB CFSR: Usage Fault Status Register Position */
|
---|
| 575 | #define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */
|
---|
| 576 |
|
---|
| 577 | #define SCB_CFSR_BUSFAULTSR_Pos 8 /*!< SCB CFSR: Bus Fault Status Register Position */
|
---|
| 578 | #define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */
|
---|
| 579 |
|
---|
| 580 | #define SCB_CFSR_MEMFAULTSR_Pos 0 /*!< SCB CFSR: Memory Manage Fault Status Register Position */
|
---|
| 581 | #define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */
|
---|
| 582 |
|
---|
| 583 | /* SCB Hard Fault Status Registers Definitions */
|
---|
| 584 | #define SCB_HFSR_DEBUGEVT_Pos 31 /*!< SCB HFSR: DEBUGEVT Position */
|
---|
| 585 | #define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */
|
---|
| 586 |
|
---|
| 587 | #define SCB_HFSR_FORCED_Pos 30 /*!< SCB HFSR: FORCED Position */
|
---|
| 588 | #define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */
|
---|
| 589 |
|
---|
| 590 | #define SCB_HFSR_VECTTBL_Pos 1 /*!< SCB HFSR: VECTTBL Position */
|
---|
| 591 | #define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */
|
---|
| 592 |
|
---|
| 593 | /* SCB Debug Fault Status Register Definitions */
|
---|
| 594 | #define SCB_DFSR_EXTERNAL_Pos 4 /*!< SCB DFSR: EXTERNAL Position */
|
---|
| 595 | #define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */
|
---|
| 596 |
|
---|
| 597 | #define SCB_DFSR_VCATCH_Pos 3 /*!< SCB DFSR: VCATCH Position */
|
---|
| 598 | #define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */
|
---|
| 599 |
|
---|
| 600 | #define SCB_DFSR_DWTTRAP_Pos 2 /*!< SCB DFSR: DWTTRAP Position */
|
---|
| 601 | #define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */
|
---|
| 602 |
|
---|
| 603 | #define SCB_DFSR_BKPT_Pos 1 /*!< SCB DFSR: BKPT Position */
|
---|
| 604 | #define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */
|
---|
| 605 |
|
---|
| 606 | #define SCB_DFSR_HALTED_Pos 0 /*!< SCB DFSR: HALTED Position */
|
---|
| 607 | #define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */
|
---|
| 608 |
|
---|
| 609 | /*@} end of group CMSIS_SCB */
|
---|
| 610 |
|
---|
| 611 |
|
---|
| 612 | /** \ingroup CMSIS_core_register
|
---|
| 613 | \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
|
---|
| 614 | \brief Type definitions for the System Control and ID Register not in the SCB
|
---|
| 615 | @{
|
---|
| 616 | */
|
---|
| 617 |
|
---|
| 618 | /** \brief Structure type to access the System Control and ID Register not in the SCB.
|
---|
| 619 | */
|
---|
| 620 | typedef struct
|
---|
| 621 | {
|
---|
| 622 | uint32_t RESERVED0[1];
|
---|
| 623 | __I uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */
|
---|
| 624 | #if ((defined __CM3_REV) && (__CM3_REV >= 0x200))
|
---|
| 625 | __IO uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */
|
---|
| 626 | #else
|
---|
| 627 | uint32_t RESERVED1[1];
|
---|
| 628 | #endif
|
---|
| 629 | } SCnSCB_Type;
|
---|
| 630 |
|
---|
| 631 | /* Interrupt Controller Type Register Definitions */
|
---|
| 632 | #define SCnSCB_ICTR_INTLINESNUM_Pos 0 /*!< ICTR: INTLINESNUM Position */
|
---|
| 633 | #define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */
|
---|
| 634 |
|
---|
| 635 | /* Auxiliary Control Register Definitions */
|
---|
| 636 |
|
---|
| 637 | #define SCnSCB_ACTLR_DISFOLD_Pos 2 /*!< ACTLR: DISFOLD Position */
|
---|
| 638 | #define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */
|
---|
| 639 |
|
---|
| 640 | #define SCnSCB_ACTLR_DISDEFWBUF_Pos 1 /*!< ACTLR: DISDEFWBUF Position */
|
---|
| 641 | #define SCnSCB_ACTLR_DISDEFWBUF_Msk (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos) /*!< ACTLR: DISDEFWBUF Mask */
|
---|
| 642 |
|
---|
| 643 | #define SCnSCB_ACTLR_DISMCYCINT_Pos 0 /*!< ACTLR: DISMCYCINT Position */
|
---|
| 644 | #define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */
|
---|
| 645 |
|
---|
| 646 | /*@} end of group CMSIS_SCnotSCB */
|
---|
| 647 |
|
---|
| 648 |
|
---|
| 649 | /** \ingroup CMSIS_core_register
|
---|
| 650 | \defgroup CMSIS_SysTick System Tick Timer (SysTick)
|
---|
| 651 | \brief Type definitions for the System Timer Registers.
|
---|
| 652 | @{
|
---|
| 653 | */
|
---|
| 654 |
|
---|
| 655 | /** \brief Structure type to access the System Timer (SysTick).
|
---|
| 656 | */
|
---|
| 657 | typedef struct
|
---|
| 658 | {
|
---|
| 659 | __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
|
---|
| 660 | __IO uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
|
---|
| 661 | __IO uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
|
---|
| 662 | __I uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
|
---|
| 663 | } SysTick_Type;
|
---|
| 664 |
|
---|
| 665 | /* SysTick Control / Status Register Definitions */
|
---|
| 666 | #define SysTick_CTRL_COUNTFLAG_Pos 16 /*!< SysTick CTRL: COUNTFLAG Position */
|
---|
| 667 | #define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
|
---|
| 668 |
|
---|
| 669 | #define SysTick_CTRL_CLKSOURCE_Pos 2 /*!< SysTick CTRL: CLKSOURCE Position */
|
---|
| 670 | #define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
|
---|
| 671 |
|
---|
| 672 | #define SysTick_CTRL_TICKINT_Pos 1 /*!< SysTick CTRL: TICKINT Position */
|
---|
| 673 | #define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
|
---|
| 674 |
|
---|
| 675 | #define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */
|
---|
| 676 | #define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */
|
---|
| 677 |
|
---|
| 678 | /* SysTick Reload Register Definitions */
|
---|
| 679 | #define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */
|
---|
| 680 | #define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */
|
---|
| 681 |
|
---|
| 682 | /* SysTick Current Register Definitions */
|
---|
| 683 | #define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */
|
---|
| 684 | #define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */
|
---|
| 685 |
|
---|
| 686 | /* SysTick Calibration Register Definitions */
|
---|
| 687 | #define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */
|
---|
| 688 | #define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
|
---|
| 689 |
|
---|
| 690 | #define SysTick_CALIB_SKEW_Pos 30 /*!< SysTick CALIB: SKEW Position */
|
---|
| 691 | #define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
|
---|
| 692 |
|
---|
| 693 | #define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */
|
---|
| 694 | #define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */
|
---|
| 695 |
|
---|
| 696 | /*@} end of group CMSIS_SysTick */
|
---|
| 697 |
|
---|
| 698 |
|
---|
| 699 | /** \ingroup CMSIS_core_register
|
---|
| 700 | \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM)
|
---|
| 701 | \brief Type definitions for the Instrumentation Trace Macrocell (ITM)
|
---|
| 702 | @{
|
---|
| 703 | */
|
---|
| 704 |
|
---|
| 705 | /** \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM).
|
---|
| 706 | */
|
---|
| 707 | typedef struct
|
---|
| 708 | {
|
---|
| 709 | __O union
|
---|
| 710 | {
|
---|
| 711 | __O uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */
|
---|
| 712 | __O uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */
|
---|
| 713 | __O uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */
|
---|
| 714 | } PORT [32]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */
|
---|
| 715 | uint32_t RESERVED0[864];
|
---|
| 716 | __IO uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */
|
---|
| 717 | uint32_t RESERVED1[15];
|
---|
| 718 | __IO uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */
|
---|
| 719 | uint32_t RESERVED2[15];
|
---|
| 720 | __IO uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */
|
---|
| 721 | uint32_t RESERVED3[29];
|
---|
| 722 | __O uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */
|
---|
| 723 | __I uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */
|
---|
| 724 | __IO uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */
|
---|
| 725 | uint32_t RESERVED4[43];
|
---|
| 726 | __O uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */
|
---|
| 727 | __I uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */
|
---|
| 728 | uint32_t RESERVED5[6];
|
---|
| 729 | __I uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */
|
---|
| 730 | __I uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */
|
---|
| 731 | __I uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */
|
---|
| 732 | __I uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */
|
---|
| 733 | __I uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */
|
---|
| 734 | __I uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */
|
---|
| 735 | __I uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */
|
---|
| 736 | __I uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */
|
---|
| 737 | __I uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */
|
---|
| 738 | __I uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */
|
---|
| 739 | __I uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */
|
---|
| 740 | __I uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */
|
---|
| 741 | } ITM_Type;
|
---|
| 742 |
|
---|
| 743 | /* ITM Trace Privilege Register Definitions */
|
---|
| 744 | #define ITM_TPR_PRIVMASK_Pos 0 /*!< ITM TPR: PRIVMASK Position */
|
---|
| 745 | #define ITM_TPR_PRIVMASK_Msk (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */
|
---|
| 746 |
|
---|
| 747 | /* ITM Trace Control Register Definitions */
|
---|
| 748 | #define ITM_TCR_BUSY_Pos 23 /*!< ITM TCR: BUSY Position */
|
---|
| 749 | #define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */
|
---|
| 750 |
|
---|
| 751 | #define ITM_TCR_TraceBusID_Pos 16 /*!< ITM TCR: ATBID Position */
|
---|
| 752 | #define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */
|
---|
| 753 |
|
---|
| 754 | #define ITM_TCR_GTSFREQ_Pos 10 /*!< ITM TCR: Global timestamp frequency Position */
|
---|
| 755 | #define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */
|
---|
| 756 |
|
---|
| 757 | #define ITM_TCR_TSPrescale_Pos 8 /*!< ITM TCR: TSPrescale Position */
|
---|
| 758 | #define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */
|
---|
| 759 |
|
---|
| 760 | #define ITM_TCR_SWOENA_Pos 4 /*!< ITM TCR: SWOENA Position */
|
---|
| 761 | #define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */
|
---|
| 762 |
|
---|
| 763 | #define ITM_TCR_DWTENA_Pos 3 /*!< ITM TCR: DWTENA Position */
|
---|
| 764 | #define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */
|
---|
| 765 |
|
---|
| 766 | #define ITM_TCR_SYNCENA_Pos 2 /*!< ITM TCR: SYNCENA Position */
|
---|
| 767 | #define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */
|
---|
| 768 |
|
---|
| 769 | #define ITM_TCR_TSENA_Pos 1 /*!< ITM TCR: TSENA Position */
|
---|
| 770 | #define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */
|
---|
| 771 |
|
---|
| 772 | #define ITM_TCR_ITMENA_Pos 0 /*!< ITM TCR: ITM Enable bit Position */
|
---|
| 773 | #define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */
|
---|
| 774 |
|
---|
| 775 | /* ITM Integration Write Register Definitions */
|
---|
| 776 | #define ITM_IWR_ATVALIDM_Pos 0 /*!< ITM IWR: ATVALIDM Position */
|
---|
| 777 | #define ITM_IWR_ATVALIDM_Msk (1UL /*<< ITM_IWR_ATVALIDM_Pos*/) /*!< ITM IWR: ATVALIDM Mask */
|
---|
| 778 |
|
---|
| 779 | /* ITM Integration Read Register Definitions */
|
---|
| 780 | #define ITM_IRR_ATREADYM_Pos 0 /*!< ITM IRR: ATREADYM Position */
|
---|
| 781 | #define ITM_IRR_ATREADYM_Msk (1UL /*<< ITM_IRR_ATREADYM_Pos*/) /*!< ITM IRR: ATREADYM Mask */
|
---|
| 782 |
|
---|
| 783 | /* ITM Integration Mode Control Register Definitions */
|
---|
| 784 | #define ITM_IMCR_INTEGRATION_Pos 0 /*!< ITM IMCR: INTEGRATION Position */
|
---|
| 785 | #define ITM_IMCR_INTEGRATION_Msk (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/) /*!< ITM IMCR: INTEGRATION Mask */
|
---|
| 786 |
|
---|
| 787 | /* ITM Lock Status Register Definitions */
|
---|
| 788 | #define ITM_LSR_ByteAcc_Pos 2 /*!< ITM LSR: ByteAcc Position */
|
---|
| 789 | #define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */
|
---|
| 790 |
|
---|
| 791 | #define ITM_LSR_Access_Pos 1 /*!< ITM LSR: Access Position */
|
---|
| 792 | #define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */
|
---|
| 793 |
|
---|
| 794 | #define ITM_LSR_Present_Pos 0 /*!< ITM LSR: Present Position */
|
---|
| 795 | #define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */
|
---|
| 796 |
|
---|
| 797 | /*@}*/ /* end of group CMSIS_ITM */
|
---|
| 798 |
|
---|
| 799 |
|
---|
| 800 | /** \ingroup CMSIS_core_register
|
---|
| 801 | \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT)
|
---|
| 802 | \brief Type definitions for the Data Watchpoint and Trace (DWT)
|
---|
| 803 | @{
|
---|
| 804 | */
|
---|
| 805 |
|
---|
| 806 | /** \brief Structure type to access the Data Watchpoint and Trace Register (DWT).
|
---|
| 807 | */
|
---|
| 808 | typedef struct
|
---|
| 809 | {
|
---|
| 810 | __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */
|
---|
| 811 | __IO uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */
|
---|
| 812 | __IO uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */
|
---|
| 813 | __IO uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */
|
---|
| 814 | __IO uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */
|
---|
| 815 | __IO uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */
|
---|
| 816 | __IO uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */
|
---|
| 817 | __I uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */
|
---|
| 818 | __IO uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */
|
---|
| 819 | __IO uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */
|
---|
| 820 | __IO uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */
|
---|
| 821 | uint32_t RESERVED0[1];
|
---|
| 822 | __IO uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */
|
---|
| 823 | __IO uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */
|
---|
| 824 | __IO uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */
|
---|
| 825 | uint32_t RESERVED1[1];
|
---|
| 826 | __IO uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */
|
---|
| 827 | __IO uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */
|
---|
| 828 | __IO uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */
|
---|
| 829 | uint32_t RESERVED2[1];
|
---|
| 830 | __IO uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */
|
---|
| 831 | __IO uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */
|
---|
| 832 | __IO uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */
|
---|
| 833 | } DWT_Type;
|
---|
| 834 |
|
---|
| 835 | /* DWT Control Register Definitions */
|
---|
| 836 | #define DWT_CTRL_NUMCOMP_Pos 28 /*!< DWT CTRL: NUMCOMP Position */
|
---|
| 837 | #define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */
|
---|
| 838 |
|
---|
| 839 | #define DWT_CTRL_NOTRCPKT_Pos 27 /*!< DWT CTRL: NOTRCPKT Position */
|
---|
| 840 | #define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */
|
---|
| 841 |
|
---|
| 842 | #define DWT_CTRL_NOEXTTRIG_Pos 26 /*!< DWT CTRL: NOEXTTRIG Position */
|
---|
| 843 | #define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */
|
---|
| 844 |
|
---|
| 845 | #define DWT_CTRL_NOCYCCNT_Pos 25 /*!< DWT CTRL: NOCYCCNT Position */
|
---|
| 846 | #define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */
|
---|
| 847 |
|
---|
| 848 | #define DWT_CTRL_NOPRFCNT_Pos 24 /*!< DWT CTRL: NOPRFCNT Position */
|
---|
| 849 | #define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */
|
---|
| 850 |
|
---|
| 851 | #define DWT_CTRL_CYCEVTENA_Pos 22 /*!< DWT CTRL: CYCEVTENA Position */
|
---|
| 852 | #define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */
|
---|
| 853 |
|
---|
| 854 | #define DWT_CTRL_FOLDEVTENA_Pos 21 /*!< DWT CTRL: FOLDEVTENA Position */
|
---|
| 855 | #define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */
|
---|
| 856 |
|
---|
| 857 | #define DWT_CTRL_LSUEVTENA_Pos 20 /*!< DWT CTRL: LSUEVTENA Position */
|
---|
| 858 | #define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */
|
---|
| 859 |
|
---|
| 860 | #define DWT_CTRL_SLEEPEVTENA_Pos 19 /*!< DWT CTRL: SLEEPEVTENA Position */
|
---|
| 861 | #define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */
|
---|
| 862 |
|
---|
| 863 | #define DWT_CTRL_EXCEVTENA_Pos 18 /*!< DWT CTRL: EXCEVTENA Position */
|
---|
| 864 | #define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */
|
---|
| 865 |
|
---|
| 866 | #define DWT_CTRL_CPIEVTENA_Pos 17 /*!< DWT CTRL: CPIEVTENA Position */
|
---|
| 867 | #define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */
|
---|
| 868 |
|
---|
| 869 | #define DWT_CTRL_EXCTRCENA_Pos 16 /*!< DWT CTRL: EXCTRCENA Position */
|
---|
| 870 | #define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */
|
---|
| 871 |
|
---|
| 872 | #define DWT_CTRL_PCSAMPLENA_Pos 12 /*!< DWT CTRL: PCSAMPLENA Position */
|
---|
| 873 | #define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */
|
---|
| 874 |
|
---|
| 875 | #define DWT_CTRL_SYNCTAP_Pos 10 /*!< DWT CTRL: SYNCTAP Position */
|
---|
| 876 | #define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */
|
---|
| 877 |
|
---|
| 878 | #define DWT_CTRL_CYCTAP_Pos 9 /*!< DWT CTRL: CYCTAP Position */
|
---|
| 879 | #define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */
|
---|
| 880 |
|
---|
| 881 | #define DWT_CTRL_POSTINIT_Pos 5 /*!< DWT CTRL: POSTINIT Position */
|
---|
| 882 | #define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */
|
---|
| 883 |
|
---|
| 884 | #define DWT_CTRL_POSTPRESET_Pos 1 /*!< DWT CTRL: POSTPRESET Position */
|
---|
| 885 | #define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */
|
---|
| 886 |
|
---|
| 887 | #define DWT_CTRL_CYCCNTENA_Pos 0 /*!< DWT CTRL: CYCCNTENA Position */
|
---|
| 888 | #define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */
|
---|
| 889 |
|
---|
| 890 | /* DWT CPI Count Register Definitions */
|
---|
| 891 | #define DWT_CPICNT_CPICNT_Pos 0 /*!< DWT CPICNT: CPICNT Position */
|
---|
| 892 | #define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */
|
---|
| 893 |
|
---|
| 894 | /* DWT Exception Overhead Count Register Definitions */
|
---|
| 895 | #define DWT_EXCCNT_EXCCNT_Pos 0 /*!< DWT EXCCNT: EXCCNT Position */
|
---|
| 896 | #define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */
|
---|
| 897 |
|
---|
| 898 | /* DWT Sleep Count Register Definitions */
|
---|
| 899 | #define DWT_SLEEPCNT_SLEEPCNT_Pos 0 /*!< DWT SLEEPCNT: SLEEPCNT Position */
|
---|
| 900 | #define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */
|
---|
| 901 |
|
---|
| 902 | /* DWT LSU Count Register Definitions */
|
---|
| 903 | #define DWT_LSUCNT_LSUCNT_Pos 0 /*!< DWT LSUCNT: LSUCNT Position */
|
---|
| 904 | #define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */
|
---|
| 905 |
|
---|
| 906 | /* DWT Folded-instruction Count Register Definitions */
|
---|
| 907 | #define DWT_FOLDCNT_FOLDCNT_Pos 0 /*!< DWT FOLDCNT: FOLDCNT Position */
|
---|
| 908 | #define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */
|
---|
| 909 |
|
---|
| 910 | /* DWT Comparator Mask Register Definitions */
|
---|
| 911 | #define DWT_MASK_MASK_Pos 0 /*!< DWT MASK: MASK Position */
|
---|
| 912 | #define DWT_MASK_MASK_Msk (0x1FUL /*<< DWT_MASK_MASK_Pos*/) /*!< DWT MASK: MASK Mask */
|
---|
| 913 |
|
---|
| 914 | /* DWT Comparator Function Register Definitions */
|
---|
| 915 | #define DWT_FUNCTION_MATCHED_Pos 24 /*!< DWT FUNCTION: MATCHED Position */
|
---|
| 916 | #define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */
|
---|
| 917 |
|
---|
| 918 | #define DWT_FUNCTION_DATAVADDR1_Pos 16 /*!< DWT FUNCTION: DATAVADDR1 Position */
|
---|
| 919 | #define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */
|
---|
| 920 |
|
---|
| 921 | #define DWT_FUNCTION_DATAVADDR0_Pos 12 /*!< DWT FUNCTION: DATAVADDR0 Position */
|
---|
| 922 | #define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */
|
---|
| 923 |
|
---|
| 924 | #define DWT_FUNCTION_DATAVSIZE_Pos 10 /*!< DWT FUNCTION: DATAVSIZE Position */
|
---|
| 925 | #define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */
|
---|
| 926 |
|
---|
| 927 | #define DWT_FUNCTION_LNK1ENA_Pos 9 /*!< DWT FUNCTION: LNK1ENA Position */
|
---|
| 928 | #define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */
|
---|
| 929 |
|
---|
| 930 | #define DWT_FUNCTION_DATAVMATCH_Pos 8 /*!< DWT FUNCTION: DATAVMATCH Position */
|
---|
| 931 | #define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */
|
---|
| 932 |
|
---|
| 933 | #define DWT_FUNCTION_CYCMATCH_Pos 7 /*!< DWT FUNCTION: CYCMATCH Position */
|
---|
| 934 | #define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */
|
---|
| 935 |
|
---|
| 936 | #define DWT_FUNCTION_EMITRANGE_Pos 5 /*!< DWT FUNCTION: EMITRANGE Position */
|
---|
| 937 | #define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */
|
---|
| 938 |
|
---|
| 939 | #define DWT_FUNCTION_FUNCTION_Pos 0 /*!< DWT FUNCTION: FUNCTION Position */
|
---|
| 940 | #define DWT_FUNCTION_FUNCTION_Msk (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/) /*!< DWT FUNCTION: FUNCTION Mask */
|
---|
| 941 |
|
---|
| 942 | /*@}*/ /* end of group CMSIS_DWT */
|
---|
| 943 |
|
---|
| 944 |
|
---|
| 945 | /** \ingroup CMSIS_core_register
|
---|
| 946 | \defgroup CMSIS_TPI Trace Port Interface (TPI)
|
---|
| 947 | \brief Type definitions for the Trace Port Interface (TPI)
|
---|
| 948 | @{
|
---|
| 949 | */
|
---|
| 950 |
|
---|
| 951 | /** \brief Structure type to access the Trace Port Interface Register (TPI).
|
---|
| 952 | */
|
---|
| 953 | typedef struct
|
---|
| 954 | {
|
---|
| 955 | __IO uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */
|
---|
| 956 | __IO uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */
|
---|
| 957 | uint32_t RESERVED0[2];
|
---|
| 958 | __IO uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */
|
---|
| 959 | uint32_t RESERVED1[55];
|
---|
| 960 | __IO uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */
|
---|
| 961 | uint32_t RESERVED2[131];
|
---|
| 962 | __I uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */
|
---|
| 963 | __IO uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */
|
---|
| 964 | __I uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */
|
---|
| 965 | uint32_t RESERVED3[759];
|
---|
| 966 | __I uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER */
|
---|
| 967 | __I uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */
|
---|
| 968 | __I uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */
|
---|
| 969 | uint32_t RESERVED4[1];
|
---|
| 970 | __I uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */
|
---|
| 971 | __I uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */
|
---|
| 972 | __IO uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */
|
---|
| 973 | uint32_t RESERVED5[39];
|
---|
| 974 | __IO uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */
|
---|
| 975 | __IO uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */
|
---|
| 976 | uint32_t RESERVED7[8];
|
---|
| 977 | __I uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */
|
---|
| 978 | __I uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */
|
---|
| 979 | } TPI_Type;
|
---|
| 980 |
|
---|
| 981 | /* TPI Asynchronous Clock Prescaler Register Definitions */
|
---|
| 982 | #define TPI_ACPR_PRESCALER_Pos 0 /*!< TPI ACPR: PRESCALER Position */
|
---|
| 983 | #define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */
|
---|
| 984 |
|
---|
| 985 | /* TPI Selected Pin Protocol Register Definitions */
|
---|
| 986 | #define TPI_SPPR_TXMODE_Pos 0 /*!< TPI SPPR: TXMODE Position */
|
---|
| 987 | #define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */
|
---|
| 988 |
|
---|
| 989 | /* TPI Formatter and Flush Status Register Definitions */
|
---|
| 990 | #define TPI_FFSR_FtNonStop_Pos 3 /*!< TPI FFSR: FtNonStop Position */
|
---|
| 991 | #define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */
|
---|
| 992 |
|
---|
| 993 | #define TPI_FFSR_TCPresent_Pos 2 /*!< TPI FFSR: TCPresent Position */
|
---|
| 994 | #define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */
|
---|
| 995 |
|
---|
| 996 | #define TPI_FFSR_FtStopped_Pos 1 /*!< TPI FFSR: FtStopped Position */
|
---|
| 997 | #define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */
|
---|
| 998 |
|
---|
| 999 | #define TPI_FFSR_FlInProg_Pos 0 /*!< TPI FFSR: FlInProg Position */
|
---|
| 1000 | #define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */
|
---|
| 1001 |
|
---|
| 1002 | /* TPI Formatter and Flush Control Register Definitions */
|
---|
| 1003 | #define TPI_FFCR_TrigIn_Pos 8 /*!< TPI FFCR: TrigIn Position */
|
---|
| 1004 | #define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */
|
---|
| 1005 |
|
---|
| 1006 | #define TPI_FFCR_EnFCont_Pos 1 /*!< TPI FFCR: EnFCont Position */
|
---|
| 1007 | #define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */
|
---|
| 1008 |
|
---|
| 1009 | /* TPI TRIGGER Register Definitions */
|
---|
| 1010 | #define TPI_TRIGGER_TRIGGER_Pos 0 /*!< TPI TRIGGER: TRIGGER Position */
|
---|
| 1011 | #define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */
|
---|
| 1012 |
|
---|
| 1013 | /* TPI Integration ETM Data Register Definitions (FIFO0) */
|
---|
| 1014 | #define TPI_FIFO0_ITM_ATVALID_Pos 29 /*!< TPI FIFO0: ITM_ATVALID Position */
|
---|
| 1015 | #define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */
|
---|
| 1016 |
|
---|
| 1017 | #define TPI_FIFO0_ITM_bytecount_Pos 27 /*!< TPI FIFO0: ITM_bytecount Position */
|
---|
| 1018 | #define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */
|
---|
| 1019 |
|
---|
| 1020 | #define TPI_FIFO0_ETM_ATVALID_Pos 26 /*!< TPI FIFO0: ETM_ATVALID Position */
|
---|
| 1021 | #define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */
|
---|
| 1022 |
|
---|
| 1023 | #define TPI_FIFO0_ETM_bytecount_Pos 24 /*!< TPI FIFO0: ETM_bytecount Position */
|
---|
| 1024 | #define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */
|
---|
| 1025 |
|
---|
| 1026 | #define TPI_FIFO0_ETM2_Pos 16 /*!< TPI FIFO0: ETM2 Position */
|
---|
| 1027 | #define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */
|
---|
| 1028 |
|
---|
| 1029 | #define TPI_FIFO0_ETM1_Pos 8 /*!< TPI FIFO0: ETM1 Position */
|
---|
| 1030 | #define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */
|
---|
| 1031 |
|
---|
| 1032 | #define TPI_FIFO0_ETM0_Pos 0 /*!< TPI FIFO0: ETM0 Position */
|
---|
| 1033 | #define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */
|
---|
| 1034 |
|
---|
| 1035 | /* TPI ITATBCTR2 Register Definitions */
|
---|
| 1036 | #define TPI_ITATBCTR2_ATREADY_Pos 0 /*!< TPI ITATBCTR2: ATREADY Position */
|
---|
| 1037 | #define TPI_ITATBCTR2_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY_Pos*/) /*!< TPI ITATBCTR2: ATREADY Mask */
|
---|
| 1038 |
|
---|
| 1039 | /* TPI Integration ITM Data Register Definitions (FIFO1) */
|
---|
| 1040 | #define TPI_FIFO1_ITM_ATVALID_Pos 29 /*!< TPI FIFO1: ITM_ATVALID Position */
|
---|
| 1041 | #define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */
|
---|
| 1042 |
|
---|
| 1043 | #define TPI_FIFO1_ITM_bytecount_Pos 27 /*!< TPI FIFO1: ITM_bytecount Position */
|
---|
| 1044 | #define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */
|
---|
| 1045 |
|
---|
| 1046 | #define TPI_FIFO1_ETM_ATVALID_Pos 26 /*!< TPI FIFO1: ETM_ATVALID Position */
|
---|
| 1047 | #define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */
|
---|
| 1048 |
|
---|
| 1049 | #define TPI_FIFO1_ETM_bytecount_Pos 24 /*!< TPI FIFO1: ETM_bytecount Position */
|
---|
| 1050 | #define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */
|
---|
| 1051 |
|
---|
| 1052 | #define TPI_FIFO1_ITM2_Pos 16 /*!< TPI FIFO1: ITM2 Position */
|
---|
| 1053 | #define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */
|
---|
| 1054 |
|
---|
| 1055 | #define TPI_FIFO1_ITM1_Pos 8 /*!< TPI FIFO1: ITM1 Position */
|
---|
| 1056 | #define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */
|
---|
| 1057 |
|
---|
| 1058 | #define TPI_FIFO1_ITM0_Pos 0 /*!< TPI FIFO1: ITM0 Position */
|
---|
| 1059 | #define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */
|
---|
| 1060 |
|
---|
| 1061 | /* TPI ITATBCTR0 Register Definitions */
|
---|
| 1062 | #define TPI_ITATBCTR0_ATREADY_Pos 0 /*!< TPI ITATBCTR0: ATREADY Position */
|
---|
| 1063 | #define TPI_ITATBCTR0_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY_Pos*/) /*!< TPI ITATBCTR0: ATREADY Mask */
|
---|
| 1064 |
|
---|
| 1065 | /* TPI Integration Mode Control Register Definitions */
|
---|
| 1066 | #define TPI_ITCTRL_Mode_Pos 0 /*!< TPI ITCTRL: Mode Position */
|
---|
| 1067 | #define TPI_ITCTRL_Mode_Msk (0x1UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */
|
---|
| 1068 |
|
---|
| 1069 | /* TPI DEVID Register Definitions */
|
---|
| 1070 | #define TPI_DEVID_NRZVALID_Pos 11 /*!< TPI DEVID: NRZVALID Position */
|
---|
| 1071 | #define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */
|
---|
| 1072 |
|
---|
| 1073 | #define TPI_DEVID_MANCVALID_Pos 10 /*!< TPI DEVID: MANCVALID Position */
|
---|
| 1074 | #define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */
|
---|
| 1075 |
|
---|
| 1076 | #define TPI_DEVID_PTINVALID_Pos 9 /*!< TPI DEVID: PTINVALID Position */
|
---|
| 1077 | #define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */
|
---|
| 1078 |
|
---|
| 1079 | #define TPI_DEVID_MinBufSz_Pos 6 /*!< TPI DEVID: MinBufSz Position */
|
---|
| 1080 | #define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */
|
---|
| 1081 |
|
---|
| 1082 | #define TPI_DEVID_AsynClkIn_Pos 5 /*!< TPI DEVID: AsynClkIn Position */
|
---|
| 1083 | #define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */
|
---|
| 1084 |
|
---|
| 1085 | #define TPI_DEVID_NrTraceInput_Pos 0 /*!< TPI DEVID: NrTraceInput Position */
|
---|
| 1086 | #define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */
|
---|
| 1087 |
|
---|
| 1088 | /* TPI DEVTYPE Register Definitions */
|
---|
| 1089 | #define TPI_DEVTYPE_MajorType_Pos 4 /*!< TPI DEVTYPE: MajorType Position */
|
---|
| 1090 | #define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */
|
---|
| 1091 |
|
---|
| 1092 | #define TPI_DEVTYPE_SubType_Pos 0 /*!< TPI DEVTYPE: SubType Position */
|
---|
| 1093 | #define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */
|
---|
| 1094 |
|
---|
| 1095 | /*@}*/ /* end of group CMSIS_TPI */
|
---|
| 1096 |
|
---|
| 1097 |
|
---|
| 1098 | #if (__MPU_PRESENT == 1)
|
---|
| 1099 | /** \ingroup CMSIS_core_register
|
---|
| 1100 | \defgroup CMSIS_MPU Memory Protection Unit (MPU)
|
---|
| 1101 | \brief Type definitions for the Memory Protection Unit (MPU)
|
---|
| 1102 | @{
|
---|
| 1103 | */
|
---|
| 1104 |
|
---|
| 1105 | /** \brief Structure type to access the Memory Protection Unit (MPU).
|
---|
| 1106 | */
|
---|
| 1107 | typedef struct
|
---|
| 1108 | {
|
---|
| 1109 | __I uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */
|
---|
| 1110 | __IO uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */
|
---|
| 1111 | __IO uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */
|
---|
| 1112 | __IO uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */
|
---|
| 1113 | __IO uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */
|
---|
| 1114 | __IO uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */
|
---|
| 1115 | __IO uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */
|
---|
| 1116 | __IO uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */
|
---|
| 1117 | __IO uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */
|
---|
| 1118 | __IO uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */
|
---|
| 1119 | __IO uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */
|
---|
| 1120 | } MPU_Type;
|
---|
| 1121 |
|
---|
| 1122 | /* MPU Type Register */
|
---|
| 1123 | #define MPU_TYPE_IREGION_Pos 16 /*!< MPU TYPE: IREGION Position */
|
---|
| 1124 | #define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */
|
---|
| 1125 |
|
---|
| 1126 | #define MPU_TYPE_DREGION_Pos 8 /*!< MPU TYPE: DREGION Position */
|
---|
| 1127 | #define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */
|
---|
| 1128 |
|
---|
| 1129 | #define MPU_TYPE_SEPARATE_Pos 0 /*!< MPU TYPE: SEPARATE Position */
|
---|
| 1130 | #define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */
|
---|
| 1131 |
|
---|
| 1132 | /* MPU Control Register */
|
---|
| 1133 | #define MPU_CTRL_PRIVDEFENA_Pos 2 /*!< MPU CTRL: PRIVDEFENA Position */
|
---|
| 1134 | #define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */
|
---|
| 1135 |
|
---|
| 1136 | #define MPU_CTRL_HFNMIENA_Pos 1 /*!< MPU CTRL: HFNMIENA Position */
|
---|
| 1137 | #define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */
|
---|
| 1138 |
|
---|
| 1139 | #define MPU_CTRL_ENABLE_Pos 0 /*!< MPU CTRL: ENABLE Position */
|
---|
| 1140 | #define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */
|
---|
| 1141 |
|
---|
| 1142 | /* MPU Region Number Register */
|
---|
| 1143 | #define MPU_RNR_REGION_Pos 0 /*!< MPU RNR: REGION Position */
|
---|
| 1144 | #define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */
|
---|
| 1145 |
|
---|
| 1146 | /* MPU Region Base Address Register */
|
---|
| 1147 | #define MPU_RBAR_ADDR_Pos 5 /*!< MPU RBAR: ADDR Position */
|
---|
| 1148 | #define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */
|
---|
| 1149 |
|
---|
| 1150 | #define MPU_RBAR_VALID_Pos 4 /*!< MPU RBAR: VALID Position */
|
---|
| 1151 | #define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */
|
---|
| 1152 |
|
---|
| 1153 | #define MPU_RBAR_REGION_Pos 0 /*!< MPU RBAR: REGION Position */
|
---|
| 1154 | #define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */
|
---|
| 1155 |
|
---|
| 1156 | /* MPU Region Attribute and Size Register */
|
---|
| 1157 | #define MPU_RASR_ATTRS_Pos 16 /*!< MPU RASR: MPU Region Attribute field Position */
|
---|
| 1158 | #define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */
|
---|
| 1159 |
|
---|
| 1160 | #define MPU_RASR_XN_Pos 28 /*!< MPU RASR: ATTRS.XN Position */
|
---|
| 1161 | #define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */
|
---|
| 1162 |
|
---|
| 1163 | #define MPU_RASR_AP_Pos 24 /*!< MPU RASR: ATTRS.AP Position */
|
---|
| 1164 | #define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */
|
---|
| 1165 |
|
---|
| 1166 | #define MPU_RASR_TEX_Pos 19 /*!< MPU RASR: ATTRS.TEX Position */
|
---|
| 1167 | #define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */
|
---|
| 1168 |
|
---|
| 1169 | #define MPU_RASR_S_Pos 18 /*!< MPU RASR: ATTRS.S Position */
|
---|
| 1170 | #define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */
|
---|
| 1171 |
|
---|
| 1172 | #define MPU_RASR_C_Pos 17 /*!< MPU RASR: ATTRS.C Position */
|
---|
| 1173 | #define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */
|
---|
| 1174 |
|
---|
| 1175 | #define MPU_RASR_B_Pos 16 /*!< MPU RASR: ATTRS.B Position */
|
---|
| 1176 | #define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */
|
---|
| 1177 |
|
---|
| 1178 | #define MPU_RASR_SRD_Pos 8 /*!< MPU RASR: Sub-Region Disable Position */
|
---|
| 1179 | #define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */
|
---|
| 1180 |
|
---|
| 1181 | #define MPU_RASR_SIZE_Pos 1 /*!< MPU RASR: Region Size Field Position */
|
---|
| 1182 | #define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */
|
---|
| 1183 |
|
---|
| 1184 | #define MPU_RASR_ENABLE_Pos 0 /*!< MPU RASR: Region enable bit Position */
|
---|
| 1185 | #define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */
|
---|
| 1186 |
|
---|
| 1187 | /*@} end of group CMSIS_MPU */
|
---|
| 1188 | #endif
|
---|
| 1189 |
|
---|
| 1190 |
|
---|
| 1191 | /** \ingroup CMSIS_core_register
|
---|
| 1192 | \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
|
---|
| 1193 | \brief Type definitions for the Core Debug Registers
|
---|
| 1194 | @{
|
---|
| 1195 | */
|
---|
| 1196 |
|
---|
| 1197 | /** \brief Structure type to access the Core Debug Register (CoreDebug).
|
---|
| 1198 | */
|
---|
| 1199 | typedef struct
|
---|
| 1200 | {
|
---|
| 1201 | __IO uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */
|
---|
| 1202 | __O uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */
|
---|
| 1203 | __IO uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */
|
---|
| 1204 | __IO uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */
|
---|
| 1205 | } CoreDebug_Type;
|
---|
| 1206 |
|
---|
| 1207 | /* Debug Halting Control and Status Register */
|
---|
| 1208 | #define CoreDebug_DHCSR_DBGKEY_Pos 16 /*!< CoreDebug DHCSR: DBGKEY Position */
|
---|
| 1209 | #define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */
|
---|
| 1210 |
|
---|
| 1211 | #define CoreDebug_DHCSR_S_RESET_ST_Pos 25 /*!< CoreDebug DHCSR: S_RESET_ST Position */
|
---|
| 1212 | #define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */
|
---|
| 1213 |
|
---|
| 1214 | #define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24 /*!< CoreDebug DHCSR: S_RETIRE_ST Position */
|
---|
| 1215 | #define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */
|
---|
| 1216 |
|
---|
| 1217 | #define CoreDebug_DHCSR_S_LOCKUP_Pos 19 /*!< CoreDebug DHCSR: S_LOCKUP Position */
|
---|
| 1218 | #define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */
|
---|
| 1219 |
|
---|
| 1220 | #define CoreDebug_DHCSR_S_SLEEP_Pos 18 /*!< CoreDebug DHCSR: S_SLEEP Position */
|
---|
| 1221 | #define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */
|
---|
| 1222 |
|
---|
| 1223 | #define CoreDebug_DHCSR_S_HALT_Pos 17 /*!< CoreDebug DHCSR: S_HALT Position */
|
---|
| 1224 | #define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */
|
---|
| 1225 |
|
---|
| 1226 | #define CoreDebug_DHCSR_S_REGRDY_Pos 16 /*!< CoreDebug DHCSR: S_REGRDY Position */
|
---|
| 1227 | #define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */
|
---|
| 1228 |
|
---|
| 1229 | #define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5 /*!< CoreDebug DHCSR: C_SNAPSTALL Position */
|
---|
| 1230 | #define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */
|
---|
| 1231 |
|
---|
| 1232 | #define CoreDebug_DHCSR_C_MASKINTS_Pos 3 /*!< CoreDebug DHCSR: C_MASKINTS Position */
|
---|
| 1233 | #define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */
|
---|
| 1234 |
|
---|
| 1235 | #define CoreDebug_DHCSR_C_STEP_Pos 2 /*!< CoreDebug DHCSR: C_STEP Position */
|
---|
| 1236 | #define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */
|
---|
| 1237 |
|
---|
| 1238 | #define CoreDebug_DHCSR_C_HALT_Pos 1 /*!< CoreDebug DHCSR: C_HALT Position */
|
---|
| 1239 | #define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */
|
---|
| 1240 |
|
---|
| 1241 | #define CoreDebug_DHCSR_C_DEBUGEN_Pos 0 /*!< CoreDebug DHCSR: C_DEBUGEN Position */
|
---|
| 1242 | #define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */
|
---|
| 1243 |
|
---|
| 1244 | /* Debug Core Register Selector Register */
|
---|
| 1245 | #define CoreDebug_DCRSR_REGWnR_Pos 16 /*!< CoreDebug DCRSR: REGWnR Position */
|
---|
| 1246 | #define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */
|
---|
| 1247 |
|
---|
| 1248 | #define CoreDebug_DCRSR_REGSEL_Pos 0 /*!< CoreDebug DCRSR: REGSEL Position */
|
---|
| 1249 | #define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */
|
---|
| 1250 |
|
---|
| 1251 | /* Debug Exception and Monitor Control Register */
|
---|
| 1252 | #define CoreDebug_DEMCR_TRCENA_Pos 24 /*!< CoreDebug DEMCR: TRCENA Position */
|
---|
| 1253 | #define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */
|
---|
| 1254 |
|
---|
| 1255 | #define CoreDebug_DEMCR_MON_REQ_Pos 19 /*!< CoreDebug DEMCR: MON_REQ Position */
|
---|
| 1256 | #define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */
|
---|
| 1257 |
|
---|
| 1258 | #define CoreDebug_DEMCR_MON_STEP_Pos 18 /*!< CoreDebug DEMCR: MON_STEP Position */
|
---|
| 1259 | #define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */
|
---|
| 1260 |
|
---|
| 1261 | #define CoreDebug_DEMCR_MON_PEND_Pos 17 /*!< CoreDebug DEMCR: MON_PEND Position */
|
---|
| 1262 | #define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */
|
---|
| 1263 |
|
---|
| 1264 | #define CoreDebug_DEMCR_MON_EN_Pos 16 /*!< CoreDebug DEMCR: MON_EN Position */
|
---|
| 1265 | #define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */
|
---|
| 1266 |
|
---|
| 1267 | #define CoreDebug_DEMCR_VC_HARDERR_Pos 10 /*!< CoreDebug DEMCR: VC_HARDERR Position */
|
---|
| 1268 | #define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */
|
---|
| 1269 |
|
---|
| 1270 | #define CoreDebug_DEMCR_VC_INTERR_Pos 9 /*!< CoreDebug DEMCR: VC_INTERR Position */
|
---|
| 1271 | #define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */
|
---|
| 1272 |
|
---|
| 1273 | #define CoreDebug_DEMCR_VC_BUSERR_Pos 8 /*!< CoreDebug DEMCR: VC_BUSERR Position */
|
---|
| 1274 | #define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */
|
---|
| 1275 |
|
---|
| 1276 | #define CoreDebug_DEMCR_VC_STATERR_Pos 7 /*!< CoreDebug DEMCR: VC_STATERR Position */
|
---|
| 1277 | #define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */
|
---|
| 1278 |
|
---|
| 1279 | #define CoreDebug_DEMCR_VC_CHKERR_Pos 6 /*!< CoreDebug DEMCR: VC_CHKERR Position */
|
---|
| 1280 | #define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */
|
---|
| 1281 |
|
---|
| 1282 | #define CoreDebug_DEMCR_VC_NOCPERR_Pos 5 /*!< CoreDebug DEMCR: VC_NOCPERR Position */
|
---|
| 1283 | #define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */
|
---|
| 1284 |
|
---|
| 1285 | #define CoreDebug_DEMCR_VC_MMERR_Pos 4 /*!< CoreDebug DEMCR: VC_MMERR Position */
|
---|
| 1286 | #define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */
|
---|
| 1287 |
|
---|
| 1288 | #define CoreDebug_DEMCR_VC_CORERESET_Pos 0 /*!< CoreDebug DEMCR: VC_CORERESET Position */
|
---|
| 1289 | #define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */
|
---|
| 1290 |
|
---|
| 1291 | /*@} end of group CMSIS_CoreDebug */
|
---|
| 1292 |
|
---|
| 1293 |
|
---|
| 1294 | /** \ingroup CMSIS_core_register
|
---|
| 1295 | \defgroup CMSIS_core_base Core Definitions
|
---|
| 1296 | \brief Definitions for base addresses, unions, and structures.
|
---|
| 1297 | @{
|
---|
| 1298 | */
|
---|
| 1299 |
|
---|
| 1300 | /* Memory mapping of Cortex-M3 Hardware */
|
---|
| 1301 | #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
|
---|
| 1302 | #define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */
|
---|
| 1303 | #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */
|
---|
| 1304 | #define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */
|
---|
| 1305 | #define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */
|
---|
| 1306 | #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
|
---|
| 1307 | #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
|
---|
| 1308 | #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
|
---|
| 1309 |
|
---|
| 1310 | #define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */
|
---|
| 1311 | #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
|
---|
| 1312 | #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
|
---|
| 1313 | #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
|
---|
| 1314 | #define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */
|
---|
| 1315 | #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */
|
---|
| 1316 | #define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */
|
---|
| 1317 | #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */
|
---|
| 1318 |
|
---|
| 1319 | #if (__MPU_PRESENT == 1)
|
---|
| 1320 | #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */
|
---|
| 1321 | #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */
|
---|
| 1322 | #endif
|
---|
| 1323 |
|
---|
| 1324 | /*@} */
|
---|
| 1325 |
|
---|
| 1326 |
|
---|
| 1327 |
|
---|
| 1328 | /*******************************************************************************
|
---|
| 1329 | * Hardware Abstraction Layer
|
---|
| 1330 | Core Function Interface contains:
|
---|
| 1331 | - Core NVIC Functions
|
---|
| 1332 | - Core SysTick Functions
|
---|
| 1333 | - Core Debug Functions
|
---|
| 1334 | - Core Register Access Functions
|
---|
| 1335 | ******************************************************************************/
|
---|
| 1336 | /** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
|
---|
| 1337 | */
|
---|
| 1338 |
|
---|
| 1339 |
|
---|
| 1340 |
|
---|
| 1341 | /* ########################## NVIC functions #################################### */
|
---|
| 1342 | /** \ingroup CMSIS_Core_FunctionInterface
|
---|
| 1343 | \defgroup CMSIS_Core_NVICFunctions NVIC Functions
|
---|
| 1344 | \brief Functions that manage interrupts and exceptions via the NVIC.
|
---|
| 1345 | @{
|
---|
| 1346 | */
|
---|
| 1347 |
|
---|
| 1348 | #ifdef CMSIS_NVIC_VIRTUAL
|
---|
| 1349 | #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE
|
---|
| 1350 | #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"
|
---|
| 1351 | #endif
|
---|
| 1352 | #include CMSIS_NVIC_VIRTUAL_HEADER_FILE
|
---|
| 1353 | #else
|
---|
| 1354 | #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping
|
---|
| 1355 | #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping
|
---|
| 1356 | #define NVIC_EnableIRQ __NVIC_EnableIRQ
|
---|
| 1357 | #define NVIC_DisableIRQ __NVIC_DisableIRQ
|
---|
| 1358 | #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ
|
---|
| 1359 | #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ
|
---|
| 1360 | #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ
|
---|
| 1361 | #define NVIC_GetActive __NVIC_GetActive
|
---|
| 1362 | #define NVIC_SetPriority __NVIC_SetPriority
|
---|
| 1363 | #define NVIC_GetPriority __NVIC_GetPriority
|
---|
| 1364 | #define NVIC_SystemReset __NVIC_SystemReset
|
---|
| 1365 | #endif /* CMSIS_NVIC_VIRTUAL */
|
---|
| 1366 |
|
---|
| 1367 | #ifdef CMSIS_VECTAB_VIRTUAL
|
---|
| 1368 | #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE
|
---|
| 1369 | #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"
|
---|
| 1370 | #endif
|
---|
| 1371 | #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE
|
---|
| 1372 | #else
|
---|
| 1373 | #define NVIC_SetVector __NVIC_SetVector
|
---|
| 1374 | #define NVIC_GetVector __NVIC_GetVector
|
---|
| 1375 | #endif /* CMSIS_VECTAB_VIRTUAL */
|
---|
| 1376 |
|
---|
| 1377 | /** \brief Set Priority Grouping
|
---|
| 1378 |
|
---|
| 1379 | The function sets the priority grouping field using the required unlock sequence.
|
---|
| 1380 | The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
|
---|
| 1381 | Only values from 0..7 are used.
|
---|
| 1382 | In case of a conflict between priority grouping and available
|
---|
| 1383 | priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
|
---|
| 1384 |
|
---|
| 1385 | \param [in] PriorityGroup Priority grouping field.
|
---|
| 1386 | */
|
---|
| 1387 | __STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
|
---|
| 1388 | {
|
---|
| 1389 | uint32_t reg_value;
|
---|
| 1390 | uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
|
---|
| 1391 |
|
---|
| 1392 | reg_value = SCB->AIRCR; /* read old register configuration */
|
---|
| 1393 | reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */
|
---|
| 1394 | reg_value = (reg_value |
|
---|
| 1395 | ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
|
---|
| 1396 | (PriorityGroupTmp << 8) ); /* Insert write key and priorty group */
|
---|
| 1397 | SCB->AIRCR = reg_value;
|
---|
| 1398 | }
|
---|
| 1399 |
|
---|
| 1400 |
|
---|
| 1401 | /** \brief Get Priority Grouping
|
---|
| 1402 |
|
---|
| 1403 | The function reads the priority grouping field from the NVIC Interrupt Controller.
|
---|
| 1404 |
|
---|
| 1405 | \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
|
---|
| 1406 | */
|
---|
| 1407 | __STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void)
|
---|
| 1408 | {
|
---|
| 1409 | return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
|
---|
| 1410 | }
|
---|
| 1411 |
|
---|
| 1412 |
|
---|
| 1413 | /** \brief Enable External Interrupt
|
---|
| 1414 |
|
---|
| 1415 | The function enables a device-specific interrupt in the NVIC interrupt controller.
|
---|
| 1416 |
|
---|
| 1417 | \param [in] IRQn External interrupt number. Value cannot be negative.
|
---|
| 1418 | */
|
---|
| 1419 | __STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
|
---|
| 1420 | {
|
---|
| 1421 | NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
|
---|
| 1422 | }
|
---|
| 1423 |
|
---|
| 1424 |
|
---|
| 1425 | /** \brief Disable External Interrupt
|
---|
| 1426 |
|
---|
| 1427 | The function disables a device-specific interrupt in the NVIC interrupt controller.
|
---|
| 1428 |
|
---|
| 1429 | \param [in] IRQn External interrupt number. Value cannot be negative.
|
---|
| 1430 | */
|
---|
| 1431 | __STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
|
---|
| 1432 | {
|
---|
| 1433 | NVIC->ICER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
|
---|
| 1434 | __DSB();
|
---|
| 1435 | __ISB();
|
---|
| 1436 | }
|
---|
| 1437 |
|
---|
| 1438 |
|
---|
| 1439 | /** \brief Get Pending Interrupt
|
---|
| 1440 |
|
---|
| 1441 | The function reads the pending register in the NVIC and returns the pending bit
|
---|
| 1442 | for the specified interrupt.
|
---|
| 1443 |
|
---|
| 1444 | \param [in] IRQn Interrupt number.
|
---|
| 1445 |
|
---|
| 1446 | \return 0 Interrupt status is not pending.
|
---|
| 1447 | \return 1 Interrupt status is pending.
|
---|
| 1448 | */
|
---|
| 1449 | __STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
|
---|
| 1450 | {
|
---|
| 1451 | return((uint32_t)(((NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
|
---|
| 1452 | }
|
---|
| 1453 |
|
---|
| 1454 |
|
---|
| 1455 | /** \brief Set Pending Interrupt
|
---|
| 1456 |
|
---|
| 1457 | The function sets the pending bit of an external interrupt.
|
---|
| 1458 |
|
---|
| 1459 | \param [in] IRQn Interrupt number. Value cannot be negative.
|
---|
| 1460 | */
|
---|
| 1461 | __STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
|
---|
| 1462 | {
|
---|
| 1463 | NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
|
---|
| 1464 | }
|
---|
| 1465 |
|
---|
| 1466 |
|
---|
| 1467 | /** \brief Clear Pending Interrupt
|
---|
| 1468 |
|
---|
| 1469 | The function clears the pending bit of an external interrupt.
|
---|
| 1470 |
|
---|
| 1471 | \param [in] IRQn External interrupt number. Value cannot be negative.
|
---|
| 1472 | */
|
---|
| 1473 | __STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
|
---|
| 1474 | {
|
---|
| 1475 | NVIC->ICPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
|
---|
| 1476 | }
|
---|
| 1477 |
|
---|
| 1478 |
|
---|
| 1479 | /** \brief Get Active Interrupt
|
---|
| 1480 |
|
---|
| 1481 | The function reads the active register in NVIC and returns the active bit.
|
---|
| 1482 |
|
---|
| 1483 | \param [in] IRQn Interrupt number.
|
---|
| 1484 |
|
---|
| 1485 | \return 0 Interrupt status is not active.
|
---|
| 1486 | \return 1 Interrupt status is active.
|
---|
| 1487 | */
|
---|
| 1488 | __STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn)
|
---|
| 1489 | {
|
---|
| 1490 | return((uint32_t)(((NVIC->IABR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
|
---|
| 1491 | }
|
---|
| 1492 |
|
---|
| 1493 |
|
---|
| 1494 | /** \brief Set Interrupt Priority
|
---|
| 1495 |
|
---|
| 1496 | The function sets the priority of an interrupt.
|
---|
| 1497 |
|
---|
| 1498 | \note The priority cannot be set for every core interrupt.
|
---|
| 1499 |
|
---|
| 1500 | \param [in] IRQn Interrupt number.
|
---|
| 1501 | \param [in] priority Priority to set.
|
---|
| 1502 | */
|
---|
| 1503 | __STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
|
---|
| 1504 | {
|
---|
| 1505 | if((int32_t)IRQn < 0) {
|
---|
| 1506 | SCB->SHP[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8 - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
|
---|
| 1507 | }
|
---|
| 1508 | else {
|
---|
| 1509 | NVIC->IP[((uint32_t)(int32_t)IRQn)] = (uint8_t)((priority << (8 - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
|
---|
| 1510 | }
|
---|
| 1511 | }
|
---|
| 1512 |
|
---|
| 1513 |
|
---|
| 1514 | /** \brief Get Interrupt Priority
|
---|
| 1515 |
|
---|
| 1516 | The function reads the priority of an interrupt. The interrupt
|
---|
| 1517 | number can be positive to specify an external (device specific)
|
---|
| 1518 | interrupt, or negative to specify an internal (core) interrupt.
|
---|
| 1519 |
|
---|
| 1520 |
|
---|
| 1521 | \param [in] IRQn Interrupt number.
|
---|
| 1522 | \return Interrupt Priority. Value is aligned automatically to the implemented
|
---|
| 1523 | priority bits of the microcontroller.
|
---|
| 1524 | */
|
---|
| 1525 | __STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
|
---|
| 1526 | {
|
---|
| 1527 |
|
---|
| 1528 | if((int32_t)IRQn < 0) {
|
---|
| 1529 | return(((uint32_t)SCB->SHP[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] >> (8 - __NVIC_PRIO_BITS)));
|
---|
| 1530 | }
|
---|
| 1531 | else {
|
---|
| 1532 | return(((uint32_t)NVIC->IP[((uint32_t)(int32_t)IRQn)] >> (8 - __NVIC_PRIO_BITS)));
|
---|
| 1533 | }
|
---|
| 1534 | }
|
---|
| 1535 |
|
---|
| 1536 |
|
---|
| 1537 | /** \brief Encode Priority
|
---|
| 1538 |
|
---|
| 1539 | The function encodes the priority for an interrupt with the given priority group,
|
---|
| 1540 | preemptive priority value, and subpriority value.
|
---|
| 1541 | In case of a conflict between priority grouping and available
|
---|
| 1542 | priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
|
---|
| 1543 |
|
---|
| 1544 | \param [in] PriorityGroup Used priority group.
|
---|
| 1545 | \param [in] PreemptPriority Preemptive priority value (starting from 0).
|
---|
| 1546 | \param [in] SubPriority Subpriority value (starting from 0).
|
---|
| 1547 | \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
|
---|
| 1548 | */
|
---|
| 1549 | __STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
|
---|
| 1550 | {
|
---|
| 1551 | uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
|
---|
| 1552 | uint32_t PreemptPriorityBits;
|
---|
| 1553 | uint32_t SubPriorityBits;
|
---|
| 1554 |
|
---|
| 1555 | PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
|
---|
| 1556 | SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
|
---|
| 1557 |
|
---|
| 1558 | return (
|
---|
| 1559 | ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
|
---|
| 1560 | ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL)))
|
---|
| 1561 | );
|
---|
| 1562 | }
|
---|
| 1563 |
|
---|
| 1564 |
|
---|
| 1565 | /** \brief Decode Priority
|
---|
| 1566 |
|
---|
| 1567 | The function decodes an interrupt priority value with a given priority group to
|
---|
| 1568 | preemptive priority value and subpriority value.
|
---|
| 1569 | In case of a conflict between priority grouping and available
|
---|
| 1570 | priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
|
---|
| 1571 |
|
---|
| 1572 | \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
|
---|
| 1573 | \param [in] PriorityGroup Used priority group.
|
---|
| 1574 | \param [out] pPreemptPriority Preemptive priority value (starting from 0).
|
---|
| 1575 | \param [out] pSubPriority Subpriority value (starting from 0).
|
---|
| 1576 | */
|
---|
| 1577 | __STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority)
|
---|
| 1578 | {
|
---|
| 1579 | uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
|
---|
| 1580 | uint32_t PreemptPriorityBits;
|
---|
| 1581 | uint32_t SubPriorityBits;
|
---|
| 1582 |
|
---|
| 1583 | PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
|
---|
| 1584 | SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
|
---|
| 1585 |
|
---|
| 1586 | *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);
|
---|
| 1587 | *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL);
|
---|
| 1588 | }
|
---|
| 1589 |
|
---|
| 1590 |
|
---|
| 1591 | /** \brief System Reset
|
---|
| 1592 |
|
---|
| 1593 | The function initiates a system reset request to reset the MCU.
|
---|
| 1594 | */
|
---|
| 1595 | __STATIC_INLINE void __NVIC_SystemReset(void)
|
---|
| 1596 | {
|
---|
| 1597 | __DSB(); /* Ensure all outstanding memory accesses included
|
---|
| 1598 | buffered write are completed before reset */
|
---|
| 1599 | SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
|
---|
| 1600 | (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |
|
---|
| 1601 | SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */
|
---|
| 1602 | __DSB(); /* Ensure completion of memory access */
|
---|
| 1603 | while(1) { __NOP(); } /* wait until reset */
|
---|
| 1604 | }
|
---|
| 1605 |
|
---|
| 1606 | /*@} end of CMSIS_Core_NVICFunctions */
|
---|
| 1607 |
|
---|
| 1608 |
|
---|
| 1609 |
|
---|
| 1610 | /* ################################## SysTick function ############################################ */
|
---|
| 1611 | /** \ingroup CMSIS_Core_FunctionInterface
|
---|
| 1612 | \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
|
---|
| 1613 | \brief Functions that configure the System.
|
---|
| 1614 | @{
|
---|
| 1615 | */
|
---|
| 1616 |
|
---|
| 1617 | #if (__Vendor_SysTickConfig == 0)
|
---|
| 1618 |
|
---|
| 1619 | /** \brief System Tick Configuration
|
---|
| 1620 |
|
---|
| 1621 | The function initializes the System Timer and its interrupt, and starts the System Tick Timer.
|
---|
| 1622 | Counter is in free running mode to generate periodic interrupts.
|
---|
| 1623 |
|
---|
| 1624 | \param [in] ticks Number of ticks between two interrupts.
|
---|
| 1625 |
|
---|
| 1626 | \return 0 Function succeeded.
|
---|
| 1627 | \return 1 Function failed.
|
---|
| 1628 |
|
---|
| 1629 | \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
|
---|
| 1630 | function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
|
---|
| 1631 | must contain a vendor-specific implementation of this function.
|
---|
| 1632 |
|
---|
| 1633 | */
|
---|
| 1634 | __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
|
---|
| 1635 | {
|
---|
| 1636 | if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) { return (1UL); } /* Reload value impossible */
|
---|
| 1637 |
|
---|
| 1638 | SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
|
---|
| 1639 | NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
|
---|
| 1640 | SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
|
---|
| 1641 | SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
|
---|
| 1642 | SysTick_CTRL_TICKINT_Msk |
|
---|
| 1643 | SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
|
---|
| 1644 | return (0UL); /* Function successful */
|
---|
| 1645 | }
|
---|
| 1646 |
|
---|
| 1647 | #endif
|
---|
| 1648 |
|
---|
| 1649 | /*@} end of CMSIS_Core_SysTickFunctions */
|
---|
| 1650 |
|
---|
| 1651 |
|
---|
| 1652 |
|
---|
| 1653 | /* ##################################### Debug In/Output function ########################################### */
|
---|
| 1654 | /** \ingroup CMSIS_Core_FunctionInterface
|
---|
| 1655 | \defgroup CMSIS_core_DebugFunctions ITM Functions
|
---|
| 1656 | \brief Functions that access the ITM debug interface.
|
---|
| 1657 | @{
|
---|
| 1658 | */
|
---|
| 1659 |
|
---|
| 1660 | extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */
|
---|
| 1661 | #define ITM_RXBUFFER_EMPTY 0x5AA55AA5 /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */
|
---|
| 1662 |
|
---|
| 1663 |
|
---|
| 1664 | /** \brief ITM Send Character
|
---|
| 1665 |
|
---|
| 1666 | The function transmits a character via the ITM channel 0, and
|
---|
| 1667 | \li Just returns when no debugger is connected that has booked the output.
|
---|
| 1668 | \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted.
|
---|
| 1669 |
|
---|
| 1670 | \param [in] ch Character to transmit.
|
---|
| 1671 |
|
---|
| 1672 | \returns Character to transmit.
|
---|
| 1673 | */
|
---|
| 1674 | __STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)
|
---|
| 1675 | {
|
---|
| 1676 | if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */
|
---|
| 1677 | ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */
|
---|
| 1678 | {
|
---|
| 1679 | while (ITM->PORT[0].u32 == 0UL) { __NOP(); }
|
---|
| 1680 | ITM->PORT[0].u8 = (uint8_t)ch;
|
---|
| 1681 | }
|
---|
| 1682 | return (ch);
|
---|
| 1683 | }
|
---|
| 1684 |
|
---|
| 1685 |
|
---|
| 1686 | /** \brief ITM Receive Character
|
---|
| 1687 |
|
---|
| 1688 | The function inputs a character via the external variable \ref ITM_RxBuffer.
|
---|
| 1689 |
|
---|
| 1690 | \return Received character.
|
---|
| 1691 | \return -1 No character pending.
|
---|
| 1692 | */
|
---|
| 1693 | __STATIC_INLINE int32_t ITM_ReceiveChar (void) {
|
---|
| 1694 | int32_t ch = -1; /* no character available */
|
---|
| 1695 |
|
---|
| 1696 | if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) {
|
---|
| 1697 | ch = ITM_RxBuffer;
|
---|
| 1698 | ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */
|
---|
| 1699 | }
|
---|
| 1700 |
|
---|
| 1701 | return (ch);
|
---|
| 1702 | }
|
---|
| 1703 |
|
---|
| 1704 |
|
---|
| 1705 | /** \brief ITM Check Character
|
---|
| 1706 |
|
---|
| 1707 | The function checks whether a character is pending for reading in the variable \ref ITM_RxBuffer.
|
---|
| 1708 |
|
---|
| 1709 | \return 0 No character available.
|
---|
| 1710 | \return 1 Character available.
|
---|
| 1711 | */
|
---|
| 1712 | __STATIC_INLINE int32_t ITM_CheckChar (void) {
|
---|
| 1713 |
|
---|
| 1714 | if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) {
|
---|
| 1715 | return (0); /* no character available */
|
---|
| 1716 | } else {
|
---|
| 1717 | return (1); /* character available */
|
---|
| 1718 | }
|
---|
| 1719 | }
|
---|
| 1720 |
|
---|
| 1721 | /*@} end of CMSIS_core_DebugFunctions */
|
---|
| 1722 |
|
---|
| 1723 |
|
---|
| 1724 |
|
---|
| 1725 |
|
---|
| 1726 | #ifdef __cplusplus
|
---|
| 1727 | }
|
---|
| 1728 | #endif
|
---|
| 1729 |
|
---|
| 1730 | #endif /* __CORE_CM3_H_DEPENDANT */
|
---|
| 1731 |
|
---|
| 1732 | #endif /* __CMSIS_GENERIC */
|
---|