1 | /**************************************************************************//**
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2 | * @file core_cm0plus.h
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3 | * @brief CMSIS Cortex-M0+ Core Peripheral Access Layer Header File
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4 | * @version V4.10
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5 | * @date 18. March 2015
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6 | *
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7 | * @note
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8 | *
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9 | ******************************************************************************/
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10 | /* Copyright (c) 2009 - 2015 ARM LIMITED
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11 |
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12 | All rights reserved.
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13 | Redistribution and use in source and binary forms, with or without
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14 | modification, are permitted provided that the following conditions are met:
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15 | - Redistributions of source code must retain the above copyright
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16 | notice, this list of conditions and the following disclaimer.
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17 | - Redistributions in binary form must reproduce the above copyright
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18 | notice, this list of conditions and the following disclaimer in the
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19 | documentation and/or other materials provided with the distribution.
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20 | - Neither the name of ARM nor the names of its contributors may be used
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21 | to endorse or promote products derived from this software without
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22 | specific prior written permission.
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23 | *
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24 | THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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25 | AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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26 | IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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27 | ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
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28 | LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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29 | CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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30 | SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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31 | INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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32 | CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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33 | ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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34 | POSSIBILITY OF SUCH DAMAGE.
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35 | ---------------------------------------------------------------------------*/
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36 |
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37 |
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38 | #if defined ( __ICCARM__ )
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39 | #pragma system_include /* treat file as system include file for MISRA check */
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40 | #endif
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41 |
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42 | #ifndef __CORE_CM0PLUS_H_GENERIC
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43 | #define __CORE_CM0PLUS_H_GENERIC
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44 |
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45 | #ifdef __cplusplus
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46 | extern "C" {
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47 | #endif
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48 |
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49 | /** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
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50 | CMSIS violates the following MISRA-C:2004 rules:
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51 |
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52 | \li Required Rule 8.5, object/function definition in header file.<br>
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53 | Function definitions in header files are used to allow 'inlining'.
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54 |
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55 | \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
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56 | Unions are used for effective representation of core registers.
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57 |
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58 | \li Advisory Rule 19.7, Function-like macro defined.<br>
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59 | Function-like macros are used to allow more efficient code.
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60 | */
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61 |
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62 |
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63 | /*******************************************************************************
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64 | * CMSIS definitions
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65 | ******************************************************************************/
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66 | /** \ingroup Cortex-M0+
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67 | @{
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68 | */
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69 |
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70 | /* CMSIS CM0P definitions */
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71 | #define __CM0PLUS_CMSIS_VERSION_MAIN (0x04) /*!< [31:16] CMSIS HAL main version */
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72 | #define __CM0PLUS_CMSIS_VERSION_SUB (0x00) /*!< [15:0] CMSIS HAL sub version */
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73 | #define __CM0PLUS_CMSIS_VERSION ((__CM0PLUS_CMSIS_VERSION_MAIN << 16) | \
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74 | __CM0PLUS_CMSIS_VERSION_SUB) /*!< CMSIS HAL version number */
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75 |
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76 | #define __CORTEX_M (0x00) /*!< Cortex-M Core */
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77 |
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78 |
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79 | #if defined ( __CC_ARM )
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80 | #define __ASM __asm /*!< asm keyword for ARM Compiler */
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81 | #define __INLINE __inline /*!< inline keyword for ARM Compiler */
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82 | #define __STATIC_INLINE static __inline
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83 |
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84 | #elif defined ( __GNUC__ )
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85 | #define __ASM __asm /*!< asm keyword for GNU Compiler */
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86 | #define __INLINE inline /*!< inline keyword for GNU Compiler */
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87 | #define __STATIC_INLINE static inline
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88 |
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89 | #elif defined ( __ICCARM__ )
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90 | #define __ASM __asm /*!< asm keyword for IAR Compiler */
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91 | #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */
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92 | #define __STATIC_INLINE static inline
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93 |
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94 | #elif defined ( __TMS470__ )
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95 | #define __ASM __asm /*!< asm keyword for TI CCS Compiler */
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96 | #define __STATIC_INLINE static inline
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97 |
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98 | #elif defined ( __TASKING__ )
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99 | #define __ASM __asm /*!< asm keyword for TASKING Compiler */
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100 | #define __INLINE inline /*!< inline keyword for TASKING Compiler */
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101 | #define __STATIC_INLINE static inline
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102 |
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103 | #elif defined ( __CSMC__ )
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104 | #define __packed
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105 | #define __ASM _asm /*!< asm keyword for COSMIC Compiler */
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106 | #define __INLINE inline /*use -pc99 on compile line !< inline keyword for COSMIC Compiler */
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107 | #define __STATIC_INLINE static inline
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108 |
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109 | #endif
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110 |
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111 | /** __FPU_USED indicates whether an FPU is used or not.
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112 | This core does not support an FPU at all
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113 | */
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114 | #define __FPU_USED 0
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115 |
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116 | #if defined ( __CC_ARM )
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117 | #if defined __TARGET_FPU_VFP
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118 | #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
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119 | #endif
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120 |
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121 | #elif defined ( __GNUC__ )
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122 | #if defined (__VFP_FP__) && !defined(__SOFTFP__)
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123 | #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
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124 | #endif
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125 |
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126 | #elif defined ( __ICCARM__ )
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127 | #if defined __ARMVFP__
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128 | #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
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129 | #endif
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130 |
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131 | #elif defined ( __TMS470__ )
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132 | #if defined __TI__VFP_SUPPORT____
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133 | #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
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134 | #endif
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135 |
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136 | #elif defined ( __TASKING__ )
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137 | #if defined __FPU_VFP__
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138 | #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
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139 | #endif
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140 |
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141 | #elif defined ( __CSMC__ ) /* Cosmic */
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142 | #if ( __CSMC__ & 0x400) // FPU present for parser
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143 | #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
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144 | #endif
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145 | #endif
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146 |
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147 | #include <stdint.h> /* standard types definitions */
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148 | #include <core_cmInstr.h> /* Core Instruction Access */
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149 | #include <core_cmFunc.h> /* Core Function Access */
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150 |
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151 | #ifdef __cplusplus
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152 | }
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153 | #endif
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154 |
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155 | #endif /* __CORE_CM0PLUS_H_GENERIC */
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156 |
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157 | #ifndef __CMSIS_GENERIC
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158 |
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159 | #ifndef __CORE_CM0PLUS_H_DEPENDANT
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160 | #define __CORE_CM0PLUS_H_DEPENDANT
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161 |
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162 | #ifdef __cplusplus
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163 | extern "C" {
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164 | #endif
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165 |
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166 | /* check device defines and use defaults */
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167 | #if defined __CHECK_DEVICE_DEFINES
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168 | #ifndef __CM0PLUS_REV
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169 | #define __CM0PLUS_REV 0x0000
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170 | #warning "__CM0PLUS_REV not defined in device header file; using default!"
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171 | #endif
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172 |
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173 | #ifndef __MPU_PRESENT
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174 | #define __MPU_PRESENT 0
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175 | #warning "__MPU_PRESENT not defined in device header file; using default!"
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176 | #endif
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177 |
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178 | #ifndef __VTOR_PRESENT
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179 | #define __VTOR_PRESENT 0
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180 | #warning "__VTOR_PRESENT not defined in device header file; using default!"
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181 | #endif
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182 |
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183 | #ifndef __NVIC_PRIO_BITS
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184 | #define __NVIC_PRIO_BITS 2
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185 | #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
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186 | #endif
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187 |
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188 | #ifndef __Vendor_SysTickConfig
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189 | #define __Vendor_SysTickConfig 0
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190 | #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
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191 | #endif
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192 | #endif
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193 |
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194 | /* IO definitions (access restrictions to peripheral registers) */
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195 | /**
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196 | \defgroup CMSIS_glob_defs CMSIS Global Defines
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197 |
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198 | <strong>IO Type Qualifiers</strong> are used
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199 | \li to specify the access to peripheral variables.
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200 | \li for automatic generation of peripheral register debug information.
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201 | */
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202 | #ifdef __cplusplus
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203 | #define __I volatile /*!< Defines 'read only' permissions */
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204 | #else
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205 | #define __I volatile const /*!< Defines 'read only' permissions */
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206 | #endif
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207 | #define __O volatile /*!< Defines 'write only' permissions */
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208 | #define __IO volatile /*!< Defines 'read / write' permissions */
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209 |
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210 | #ifdef __cplusplus
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211 | #define __IM volatile /*!< Defines 'read only' permissions */
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212 | #else
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213 | #define __IM volatile const /*!< Defines 'read only' permissions */
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214 | #endif
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215 | #define __OM volatile /*!< Defines 'write only' permissions */
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216 | #define __IOM volatile /*!< Defines 'read / write' permissions */
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217 |
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218 | /*@} end of group Cortex-M0+ */
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219 |
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220 |
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221 |
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222 | /*******************************************************************************
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223 | * Register Abstraction
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224 | Core Register contain:
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225 | - Core Register
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226 | - Core NVIC Register
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227 | - Core SCB Register
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228 | - Core SysTick Register
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229 | - Core MPU Register
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230 | ******************************************************************************/
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231 | /** \defgroup CMSIS_core_register Defines and Type Definitions
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232 | \brief Type definitions and defines for Cortex-M processor based devices.
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233 | */
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234 |
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235 | /** \ingroup CMSIS_core_register
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236 | \defgroup CMSIS_CORE Status and Control Registers
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237 | \brief Core Register type definitions.
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238 | @{
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239 | */
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240 |
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241 | /** \brief Union type to access the Application Program Status Register (APSR).
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242 | */
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243 | typedef union
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244 | {
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245 | struct
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246 | {
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247 | uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */
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248 | uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
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249 | uint32_t C:1; /*!< bit: 29 Carry condition code flag */
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250 | uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
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251 | uint32_t N:1; /*!< bit: 31 Negative condition code flag */
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252 | } b; /*!< Structure used for bit access */
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253 | uint32_t w; /*!< Type used for word access */
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254 | } APSR_Type;
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255 |
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256 | /* APSR Register Definitions */
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257 | #define APSR_N_Pos 31 /*!< APSR: N Position */
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258 | #define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */
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259 |
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260 | #define APSR_Z_Pos 30 /*!< APSR: Z Position */
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261 | #define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */
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262 |
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263 | #define APSR_C_Pos 29 /*!< APSR: C Position */
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264 | #define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */
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265 |
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266 | #define APSR_V_Pos 28 /*!< APSR: V Position */
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267 | #define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */
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268 |
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269 |
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270 | /** \brief Union type to access the Interrupt Program Status Register (IPSR).
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271 | */
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272 | typedef union
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273 | {
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274 | struct
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275 | {
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276 | uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
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277 | uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
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278 | } b; /*!< Structure used for bit access */
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279 | uint32_t w; /*!< Type used for word access */
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280 | } IPSR_Type;
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281 |
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282 | /* IPSR Register Definitions */
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283 | #define IPSR_ISR_Pos 0 /*!< IPSR: ISR Position */
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284 | #define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */
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285 |
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286 |
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287 | /** \brief Union type to access the Special-Purpose Program Status Registers (xPSR).
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288 | */
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289 | typedef union
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290 | {
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291 | struct
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292 | {
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293 | uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
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294 | uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */
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295 | uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */
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296 | uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */
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297 | uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
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298 | uint32_t C:1; /*!< bit: 29 Carry condition code flag */
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299 | uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
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300 | uint32_t N:1; /*!< bit: 31 Negative condition code flag */
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301 | } b; /*!< Structure used for bit access */
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302 | uint32_t w; /*!< Type used for word access */
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303 | } xPSR_Type;
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304 |
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305 | /* xPSR Register Definitions */
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306 | #define xPSR_N_Pos 31 /*!< xPSR: N Position */
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307 | #define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */
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308 |
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309 | #define xPSR_Z_Pos 30 /*!< xPSR: Z Position */
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310 | #define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */
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311 |
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312 | #define xPSR_C_Pos 29 /*!< xPSR: C Position */
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313 | #define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */
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314 |
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315 | #define xPSR_V_Pos 28 /*!< xPSR: V Position */
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316 | #define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */
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317 |
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318 | #define xPSR_T_Pos 24 /*!< xPSR: T Position */
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319 | #define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */
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320 |
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321 | #define xPSR_ISR_Pos 0 /*!< xPSR: ISR Position */
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322 | #define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */
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323 |
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324 |
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325 | /** \brief Union type to access the Control Registers (CONTROL).
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326 | */
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327 | typedef union
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328 | {
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329 | struct
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330 | {
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331 | uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */
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332 | uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */
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333 | uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */
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334 | } b; /*!< Structure used for bit access */
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335 | uint32_t w; /*!< Type used for word access */
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336 | } CONTROL_Type;
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337 |
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338 | /* CONTROL Register Definitions */
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339 | #define CONTROL_SPSEL_Pos 1 /*!< CONTROL: SPSEL Position */
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340 | #define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */
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341 |
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342 | #define CONTROL_nPRIV_Pos 0 /*!< CONTROL: nPRIV Position */
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343 | #define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */
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344 |
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345 | /*@} end of group CMSIS_CORE */
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346 |
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347 |
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348 | /** \ingroup CMSIS_core_register
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349 | \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
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350 | \brief Type definitions for the NVIC Registers
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351 | @{
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352 | */
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353 |
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354 | /** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
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355 | */
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356 | typedef struct
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357 | {
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358 | __IO uint32_t ISER[1]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
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359 | uint32_t RESERVED0[31];
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360 | __IO uint32_t ICER[1]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
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361 | uint32_t RSERVED1[31];
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362 | __IO uint32_t ISPR[1]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
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363 | uint32_t RESERVED2[31];
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364 | __IO uint32_t ICPR[1]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
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365 | uint32_t RESERVED3[31];
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366 | uint32_t RESERVED4[64];
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367 | __IO uint32_t IP[8]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */
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368 | } NVIC_Type;
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369 |
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370 | /*@} end of group CMSIS_NVIC */
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371 |
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372 |
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373 | /** \ingroup CMSIS_core_register
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374 | \defgroup CMSIS_SCB System Control Block (SCB)
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375 | \brief Type definitions for the System Control Block Registers
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376 | @{
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377 | */
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378 |
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379 | /** \brief Structure type to access the System Control Block (SCB).
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380 | */
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381 | typedef struct
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382 | {
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383 | __I uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
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384 | __IO uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
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385 | #if (__VTOR_PRESENT == 1)
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386 | __IO uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */
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387 | #else
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388 | uint32_t RESERVED0;
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389 | #endif
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390 | __IO uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
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391 | __IO uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
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392 | __IO uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
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393 | uint32_t RESERVED1;
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394 | __IO uint32_t SHP[2]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */
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395 | __IO uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
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396 | } SCB_Type;
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397 |
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398 | /* SCB CPUID Register Definitions */
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399 | #define SCB_CPUID_IMPLEMENTER_Pos 24 /*!< SCB CPUID: IMPLEMENTER Position */
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400 | #define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
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401 |
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402 | #define SCB_CPUID_VARIANT_Pos 20 /*!< SCB CPUID: VARIANT Position */
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403 | #define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
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404 |
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405 | #define SCB_CPUID_ARCHITECTURE_Pos 16 /*!< SCB CPUID: ARCHITECTURE Position */
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406 | #define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
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407 |
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408 | #define SCB_CPUID_PARTNO_Pos 4 /*!< SCB CPUID: PARTNO Position */
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409 | #define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
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410 |
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411 | #define SCB_CPUID_REVISION_Pos 0 /*!< SCB CPUID: REVISION Position */
|
---|
412 | #define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */
|
---|
413 |
|
---|
414 | /* SCB Interrupt Control State Register Definitions */
|
---|
415 | #define SCB_ICSR_NMIPENDSET_Pos 31 /*!< SCB ICSR: NMIPENDSET Position */
|
---|
416 | #define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */
|
---|
417 |
|
---|
418 | #define SCB_ICSR_PENDSVSET_Pos 28 /*!< SCB ICSR: PENDSVSET Position */
|
---|
419 | #define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
|
---|
420 |
|
---|
421 | #define SCB_ICSR_PENDSVCLR_Pos 27 /*!< SCB ICSR: PENDSVCLR Position */
|
---|
422 | #define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
|
---|
423 |
|
---|
424 | #define SCB_ICSR_PENDSTSET_Pos 26 /*!< SCB ICSR: PENDSTSET Position */
|
---|
425 | #define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
|
---|
426 |
|
---|
427 | #define SCB_ICSR_PENDSTCLR_Pos 25 /*!< SCB ICSR: PENDSTCLR Position */
|
---|
428 | #define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
|
---|
429 |
|
---|
430 | #define SCB_ICSR_ISRPREEMPT_Pos 23 /*!< SCB ICSR: ISRPREEMPT Position */
|
---|
431 | #define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
|
---|
432 |
|
---|
433 | #define SCB_ICSR_ISRPENDING_Pos 22 /*!< SCB ICSR: ISRPENDING Position */
|
---|
434 | #define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
|
---|
435 |
|
---|
436 | #define SCB_ICSR_VECTPENDING_Pos 12 /*!< SCB ICSR: VECTPENDING Position */
|
---|
437 | #define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
|
---|
438 |
|
---|
439 | #define SCB_ICSR_VECTACTIVE_Pos 0 /*!< SCB ICSR: VECTACTIVE Position */
|
---|
440 | #define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */
|
---|
441 |
|
---|
442 | #if (__VTOR_PRESENT == 1)
|
---|
443 | /* SCB Interrupt Control State Register Definitions */
|
---|
444 | #define SCB_VTOR_TBLOFF_Pos 8 /*!< SCB VTOR: TBLOFF Position */
|
---|
445 | #define SCB_VTOR_TBLOFF_Msk (0xFFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */
|
---|
446 | #endif
|
---|
447 |
|
---|
448 | /* SCB Application Interrupt and Reset Control Register Definitions */
|
---|
449 | #define SCB_AIRCR_VECTKEY_Pos 16 /*!< SCB AIRCR: VECTKEY Position */
|
---|
450 | #define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
|
---|
451 |
|
---|
452 | #define SCB_AIRCR_VECTKEYSTAT_Pos 16 /*!< SCB AIRCR: VECTKEYSTAT Position */
|
---|
453 | #define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
|
---|
454 |
|
---|
455 | #define SCB_AIRCR_ENDIANESS_Pos 15 /*!< SCB AIRCR: ENDIANESS Position */
|
---|
456 | #define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
|
---|
457 |
|
---|
458 | #define SCB_AIRCR_SYSRESETREQ_Pos 2 /*!< SCB AIRCR: SYSRESETREQ Position */
|
---|
459 | #define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
|
---|
460 |
|
---|
461 | #define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /*!< SCB AIRCR: VECTCLRACTIVE Position */
|
---|
462 | #define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
|
---|
463 |
|
---|
464 | /* SCB System Control Register Definitions */
|
---|
465 | #define SCB_SCR_SEVONPEND_Pos 4 /*!< SCB SCR: SEVONPEND Position */
|
---|
466 | #define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
|
---|
467 |
|
---|
468 | #define SCB_SCR_SLEEPDEEP_Pos 2 /*!< SCB SCR: SLEEPDEEP Position */
|
---|
469 | #define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
|
---|
470 |
|
---|
471 | #define SCB_SCR_SLEEPONEXIT_Pos 1 /*!< SCB SCR: SLEEPONEXIT Position */
|
---|
472 | #define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
|
---|
473 |
|
---|
474 | /* SCB Configuration Control Register Definitions */
|
---|
475 | #define SCB_CCR_STKALIGN_Pos 9 /*!< SCB CCR: STKALIGN Position */
|
---|
476 | #define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */
|
---|
477 |
|
---|
478 | #define SCB_CCR_UNALIGN_TRP_Pos 3 /*!< SCB CCR: UNALIGN_TRP Position */
|
---|
479 | #define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
|
---|
480 |
|
---|
481 | /* SCB System Handler Control and State Register Definitions */
|
---|
482 | #define SCB_SHCSR_SVCALLPENDED_Pos 15 /*!< SCB SHCSR: SVCALLPENDED Position */
|
---|
483 | #define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
|
---|
484 |
|
---|
485 | /*@} end of group CMSIS_SCB */
|
---|
486 |
|
---|
487 |
|
---|
488 | /** \ingroup CMSIS_core_register
|
---|
489 | \defgroup CMSIS_SysTick System Tick Timer (SysTick)
|
---|
490 | \brief Type definitions for the System Timer Registers.
|
---|
491 | @{
|
---|
492 | */
|
---|
493 |
|
---|
494 | /** \brief Structure type to access the System Timer (SysTick).
|
---|
495 | */
|
---|
496 | typedef struct
|
---|
497 | {
|
---|
498 | __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
|
---|
499 | __IO uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
|
---|
500 | __IO uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
|
---|
501 | __I uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
|
---|
502 | } SysTick_Type;
|
---|
503 |
|
---|
504 | /* SysTick Control / Status Register Definitions */
|
---|
505 | #define SysTick_CTRL_COUNTFLAG_Pos 16 /*!< SysTick CTRL: COUNTFLAG Position */
|
---|
506 | #define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
|
---|
507 |
|
---|
508 | #define SysTick_CTRL_CLKSOURCE_Pos 2 /*!< SysTick CTRL: CLKSOURCE Position */
|
---|
509 | #define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
|
---|
510 |
|
---|
511 | #define SysTick_CTRL_TICKINT_Pos 1 /*!< SysTick CTRL: TICKINT Position */
|
---|
512 | #define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
|
---|
513 |
|
---|
514 | #define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */
|
---|
515 | #define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */
|
---|
516 |
|
---|
517 | /* SysTick Reload Register Definitions */
|
---|
518 | #define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */
|
---|
519 | #define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */
|
---|
520 |
|
---|
521 | /* SysTick Current Register Definitions */
|
---|
522 | #define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */
|
---|
523 | #define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */
|
---|
524 |
|
---|
525 | /* SysTick Calibration Register Definitions */
|
---|
526 | #define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */
|
---|
527 | #define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
|
---|
528 |
|
---|
529 | #define SysTick_CALIB_SKEW_Pos 30 /*!< SysTick CALIB: SKEW Position */
|
---|
530 | #define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
|
---|
531 |
|
---|
532 | #define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */
|
---|
533 | #define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */
|
---|
534 |
|
---|
535 | /*@} end of group CMSIS_SysTick */
|
---|
536 |
|
---|
537 | #if (__MPU_PRESENT == 1)
|
---|
538 | /** \ingroup CMSIS_core_register
|
---|
539 | \defgroup CMSIS_MPU Memory Protection Unit (MPU)
|
---|
540 | \brief Type definitions for the Memory Protection Unit (MPU)
|
---|
541 | @{
|
---|
542 | */
|
---|
543 |
|
---|
544 | /** \brief Structure type to access the Memory Protection Unit (MPU).
|
---|
545 | */
|
---|
546 | typedef struct
|
---|
547 | {
|
---|
548 | __I uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */
|
---|
549 | __IO uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */
|
---|
550 | __IO uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */
|
---|
551 | __IO uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */
|
---|
552 | __IO uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */
|
---|
553 | } MPU_Type;
|
---|
554 |
|
---|
555 | /* MPU Type Register */
|
---|
556 | #define MPU_TYPE_IREGION_Pos 16 /*!< MPU TYPE: IREGION Position */
|
---|
557 | #define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */
|
---|
558 |
|
---|
559 | #define MPU_TYPE_DREGION_Pos 8 /*!< MPU TYPE: DREGION Position */
|
---|
560 | #define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */
|
---|
561 |
|
---|
562 | #define MPU_TYPE_SEPARATE_Pos 0 /*!< MPU TYPE: SEPARATE Position */
|
---|
563 | #define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */
|
---|
564 |
|
---|
565 | /* MPU Control Register */
|
---|
566 | #define MPU_CTRL_PRIVDEFENA_Pos 2 /*!< MPU CTRL: PRIVDEFENA Position */
|
---|
567 | #define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */
|
---|
568 |
|
---|
569 | #define MPU_CTRL_HFNMIENA_Pos 1 /*!< MPU CTRL: HFNMIENA Position */
|
---|
570 | #define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */
|
---|
571 |
|
---|
572 | #define MPU_CTRL_ENABLE_Pos 0 /*!< MPU CTRL: ENABLE Position */
|
---|
573 | #define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */
|
---|
574 |
|
---|
575 | /* MPU Region Number Register */
|
---|
576 | #define MPU_RNR_REGION_Pos 0 /*!< MPU RNR: REGION Position */
|
---|
577 | #define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */
|
---|
578 |
|
---|
579 | /* MPU Region Base Address Register */
|
---|
580 | #define MPU_RBAR_ADDR_Pos 8 /*!< MPU RBAR: ADDR Position */
|
---|
581 | #define MPU_RBAR_ADDR_Msk (0xFFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */
|
---|
582 |
|
---|
583 | #define MPU_RBAR_VALID_Pos 4 /*!< MPU RBAR: VALID Position */
|
---|
584 | #define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */
|
---|
585 |
|
---|
586 | #define MPU_RBAR_REGION_Pos 0 /*!< MPU RBAR: REGION Position */
|
---|
587 | #define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */
|
---|
588 |
|
---|
589 | /* MPU Region Attribute and Size Register */
|
---|
590 | #define MPU_RASR_ATTRS_Pos 16 /*!< MPU RASR: MPU Region Attribute field Position */
|
---|
591 | #define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */
|
---|
592 |
|
---|
593 | #define MPU_RASR_XN_Pos 28 /*!< MPU RASR: ATTRS.XN Position */
|
---|
594 | #define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */
|
---|
595 |
|
---|
596 | #define MPU_RASR_AP_Pos 24 /*!< MPU RASR: ATTRS.AP Position */
|
---|
597 | #define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */
|
---|
598 |
|
---|
599 | #define MPU_RASR_TEX_Pos 19 /*!< MPU RASR: ATTRS.TEX Position */
|
---|
600 | #define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */
|
---|
601 |
|
---|
602 | #define MPU_RASR_S_Pos 18 /*!< MPU RASR: ATTRS.S Position */
|
---|
603 | #define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */
|
---|
604 |
|
---|
605 | #define MPU_RASR_C_Pos 17 /*!< MPU RASR: ATTRS.C Position */
|
---|
606 | #define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */
|
---|
607 |
|
---|
608 | #define MPU_RASR_B_Pos 16 /*!< MPU RASR: ATTRS.B Position */
|
---|
609 | #define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */
|
---|
610 |
|
---|
611 | #define MPU_RASR_SRD_Pos 8 /*!< MPU RASR: Sub-Region Disable Position */
|
---|
612 | #define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */
|
---|
613 |
|
---|
614 | #define MPU_RASR_SIZE_Pos 1 /*!< MPU RASR: Region Size Field Position */
|
---|
615 | #define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */
|
---|
616 |
|
---|
617 | #define MPU_RASR_ENABLE_Pos 0 /*!< MPU RASR: Region enable bit Position */
|
---|
618 | #define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */
|
---|
619 |
|
---|
620 | /*@} end of group CMSIS_MPU */
|
---|
621 | #endif
|
---|
622 |
|
---|
623 |
|
---|
624 | /** \ingroup CMSIS_core_register
|
---|
625 | \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
|
---|
626 | \brief Cortex-M0+ Core Debug Registers (DCB registers, SHCSR, and DFSR)
|
---|
627 | are only accessible over DAP and not via processor. Therefore
|
---|
628 | they are not covered by the Cortex-M0 header file.
|
---|
629 | @{
|
---|
630 | */
|
---|
631 | /*@} end of group CMSIS_CoreDebug */
|
---|
632 |
|
---|
633 |
|
---|
634 | /** \ingroup CMSIS_core_register
|
---|
635 | \defgroup CMSIS_core_base Core Definitions
|
---|
636 | \brief Definitions for base addresses, unions, and structures.
|
---|
637 | @{
|
---|
638 | */
|
---|
639 |
|
---|
640 | /* Memory mapping of Cortex-M0+ Hardware */
|
---|
641 | #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
|
---|
642 | #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
|
---|
643 | #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
|
---|
644 | #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
|
---|
645 |
|
---|
646 | #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
|
---|
647 | #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
|
---|
648 | #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
|
---|
649 |
|
---|
650 | #if (__MPU_PRESENT == 1)
|
---|
651 | #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */
|
---|
652 | #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */
|
---|
653 | #endif
|
---|
654 |
|
---|
655 | /*@} */
|
---|
656 |
|
---|
657 |
|
---|
658 |
|
---|
659 | /*******************************************************************************
|
---|
660 | * Hardware Abstraction Layer
|
---|
661 | Core Function Interface contains:
|
---|
662 | - Core NVIC Functions
|
---|
663 | - Core SysTick Functions
|
---|
664 | - Core Register Access Functions
|
---|
665 | ******************************************************************************/
|
---|
666 | /** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
|
---|
667 | */
|
---|
668 |
|
---|
669 |
|
---|
670 |
|
---|
671 | /* ########################## NVIC functions #################################### */
|
---|
672 | /** \ingroup CMSIS_Core_FunctionInterface
|
---|
673 | \defgroup CMSIS_Core_NVICFunctions NVIC Functions
|
---|
674 | \brief Functions that manage interrupts and exceptions via the NVIC.
|
---|
675 | @{
|
---|
676 | */
|
---|
677 |
|
---|
678 | /* Interrupt Priorities are WORD accessible only under ARMv6M */
|
---|
679 | /* The following MACROS handle generation of the register offset and byte masks */
|
---|
680 | #define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL)
|
---|
681 | #define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) )
|
---|
682 | #define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) )
|
---|
683 |
|
---|
684 |
|
---|
685 | /** \brief Enable External Interrupt
|
---|
686 |
|
---|
687 | The function enables a device-specific interrupt in the NVIC interrupt controller.
|
---|
688 |
|
---|
689 | \param [in] IRQn External interrupt number. Value cannot be negative.
|
---|
690 | */
|
---|
691 | __STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
|
---|
692 | {
|
---|
693 | NVIC->ISER[0] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
|
---|
694 | }
|
---|
695 |
|
---|
696 |
|
---|
697 | /** \brief Disable External Interrupt
|
---|
698 |
|
---|
699 | The function disables a device-specific interrupt in the NVIC interrupt controller.
|
---|
700 |
|
---|
701 | \param [in] IRQn External interrupt number. Value cannot be negative.
|
---|
702 | */
|
---|
703 | __STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
|
---|
704 | {
|
---|
705 | NVIC->ICER[0] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
|
---|
706 | __DSB();
|
---|
707 | __ISB();
|
---|
708 | }
|
---|
709 |
|
---|
710 |
|
---|
711 | /** \brief Get Pending Interrupt
|
---|
712 |
|
---|
713 | The function reads the pending register in the NVIC and returns the pending bit
|
---|
714 | for the specified interrupt.
|
---|
715 |
|
---|
716 | \param [in] IRQn Interrupt number.
|
---|
717 |
|
---|
718 | \return 0 Interrupt status is not pending.
|
---|
719 | \return 1 Interrupt status is pending.
|
---|
720 | */
|
---|
721 | __STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
|
---|
722 | {
|
---|
723 | return((uint32_t)(((NVIC->ISPR[0] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
|
---|
724 | }
|
---|
725 |
|
---|
726 |
|
---|
727 | /** \brief Set Pending Interrupt
|
---|
728 |
|
---|
729 | The function sets the pending bit of an external interrupt.
|
---|
730 |
|
---|
731 | \param [in] IRQn Interrupt number. Value cannot be negative.
|
---|
732 | */
|
---|
733 | __STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
|
---|
734 | {
|
---|
735 | NVIC->ISPR[0] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
|
---|
736 | }
|
---|
737 |
|
---|
738 |
|
---|
739 | /** \brief Clear Pending Interrupt
|
---|
740 |
|
---|
741 | The function clears the pending bit of an external interrupt.
|
---|
742 |
|
---|
743 | \param [in] IRQn External interrupt number. Value cannot be negative.
|
---|
744 | */
|
---|
745 | __STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
|
---|
746 | {
|
---|
747 | NVIC->ICPR[0] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
|
---|
748 | }
|
---|
749 |
|
---|
750 |
|
---|
751 | /** \brief Set Interrupt Priority
|
---|
752 |
|
---|
753 | The function sets the priority of an interrupt.
|
---|
754 |
|
---|
755 | \note The priority cannot be set for every core interrupt.
|
---|
756 |
|
---|
757 | \param [in] IRQn Interrupt number.
|
---|
758 | \param [in] priority Priority to set.
|
---|
759 | */
|
---|
760 | __STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
|
---|
761 | {
|
---|
762 | if((int32_t)(IRQn) < 0) {
|
---|
763 | SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
|
---|
764 | (((priority << (8 - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
|
---|
765 | }
|
---|
766 | else {
|
---|
767 | NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
|
---|
768 | (((priority << (8 - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
|
---|
769 | }
|
---|
770 | }
|
---|
771 |
|
---|
772 |
|
---|
773 | /** \brief Get Interrupt Priority
|
---|
774 |
|
---|
775 | The function reads the priority of an interrupt. The interrupt
|
---|
776 | number can be positive to specify an external (device specific)
|
---|
777 | interrupt, or negative to specify an internal (core) interrupt.
|
---|
778 |
|
---|
779 |
|
---|
780 | \param [in] IRQn Interrupt number.
|
---|
781 | \return Interrupt Priority. Value is aligned automatically to the implemented
|
---|
782 | priority bits of the microcontroller.
|
---|
783 | */
|
---|
784 | __STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
|
---|
785 | {
|
---|
786 |
|
---|
787 | if((int32_t)(IRQn) < 0) {
|
---|
788 | return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8 - __NVIC_PRIO_BITS)));
|
---|
789 | }
|
---|
790 | else {
|
---|
791 | return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8 - __NVIC_PRIO_BITS)));
|
---|
792 | }
|
---|
793 | }
|
---|
794 |
|
---|
795 |
|
---|
796 | /** \brief System Reset
|
---|
797 |
|
---|
798 | The function initiates a system reset request to reset the MCU.
|
---|
799 | */
|
---|
800 | __STATIC_INLINE void NVIC_SystemReset(void)
|
---|
801 | {
|
---|
802 | __DSB(); /* Ensure all outstanding memory accesses included
|
---|
803 | buffered write are completed before reset */
|
---|
804 | SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
|
---|
805 | SCB_AIRCR_SYSRESETREQ_Msk);
|
---|
806 | __DSB(); /* Ensure completion of memory access */
|
---|
807 | while(1) { __NOP(); } /* wait until reset */
|
---|
808 | }
|
---|
809 |
|
---|
810 | /*@} end of CMSIS_Core_NVICFunctions */
|
---|
811 |
|
---|
812 |
|
---|
813 |
|
---|
814 | /* ################################## SysTick function ############################################ */
|
---|
815 | /** \ingroup CMSIS_Core_FunctionInterface
|
---|
816 | \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
|
---|
817 | \brief Functions that configure the System.
|
---|
818 | @{
|
---|
819 | */
|
---|
820 |
|
---|
821 | #if (__Vendor_SysTickConfig == 0)
|
---|
822 |
|
---|
823 | /** \brief System Tick Configuration
|
---|
824 |
|
---|
825 | The function initializes the System Timer and its interrupt, and starts the System Tick Timer.
|
---|
826 | Counter is in free running mode to generate periodic interrupts.
|
---|
827 |
|
---|
828 | \param [in] ticks Number of ticks between two interrupts.
|
---|
829 |
|
---|
830 | \return 0 Function succeeded.
|
---|
831 | \return 1 Function failed.
|
---|
832 |
|
---|
833 | \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
|
---|
834 | function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
|
---|
835 | must contain a vendor-specific implementation of this function.
|
---|
836 |
|
---|
837 | */
|
---|
838 | __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
|
---|
839 | {
|
---|
840 | if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) {return (1UL);} /* Reload value impossible */
|
---|
841 |
|
---|
842 | SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
|
---|
843 | NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
|
---|
844 | SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
|
---|
845 | SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
|
---|
846 | SysTick_CTRL_TICKINT_Msk |
|
---|
847 | SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
|
---|
848 | return (0UL); /* Function successful */
|
---|
849 | }
|
---|
850 |
|
---|
851 | #endif
|
---|
852 |
|
---|
853 | /*@} end of CMSIS_Core_SysTickFunctions */
|
---|
854 |
|
---|
855 |
|
---|
856 |
|
---|
857 |
|
---|
858 | #ifdef __cplusplus
|
---|
859 | }
|
---|
860 | #endif
|
---|
861 |
|
---|
862 | #endif /* __CORE_CM0PLUS_H_DEPENDANT */
|
---|
863 |
|
---|
864 | #endif /* __CMSIS_GENERIC */
|
---|