[374] | 1 | /**************************************************************************//**
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| 2 | * @file irq_ctrl_gic.c
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| 3 | * @brief Interrupt controller handling implementation for GIC
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| 4 | * @version V1.0.1
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| 5 | * @date 9. April 2018
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| 6 | ******************************************************************************/
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| 7 | /*
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| 8 | * Copyright (c) 2017 ARM Limited. All rights reserved.
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| 9 | *
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| 10 | * SPDX-License-Identifier: Apache-2.0
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| 11 | *
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| 12 | * Licensed under the Apache License, Version 2.0 (the License); you may
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| 13 | * not use this file except in compliance with the License.
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| 14 | * You may obtain a copy of the License at
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| 15 | *
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| 16 | * www.apache.org/licenses/LICENSE-2.0
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| 17 | *
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| 18 | * Unless required by applicable law or agreed to in writing, software
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| 19 | * distributed under the License is distributed on an AS IS BASIS, WITHOUT
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| 20 | * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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| 21 | * See the License for the specific language governing permissions and
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| 22 | * limitations under the License.
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| 23 | */
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| 24 |
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| 25 | #include <stddef.h>
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| 26 |
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| 27 | #include "RTE_Components.h"
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| 28 | #include CMSIS_device_header
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| 29 |
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| 30 | #include "irq_ctrl.h"
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| 31 |
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| 32 | #if defined(__GIC_PRESENT) && (__GIC_PRESENT == 1U)
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| 33 |
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| 34 | /// Number of implemented interrupt lines
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| 35 | #ifndef IRQ_GIC_LINE_COUNT
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| 36 | #define IRQ_GIC_LINE_COUNT (1020U)
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| 37 | #endif
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| 38 |
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| 39 | extern IRQHandler_t IRQTable[IRQ_GIC_LINE_COUNT];
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| 40 | static uint32_t IRQ_ID0;
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| 41 |
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| 42 | /// Initialize interrupt controller.
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| 43 | __WEAK int32_t IRQ_Initialize (void) {
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| 44 | uint32_t i;
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| 45 |
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| 46 | for (i = 0U; i < IRQ_GIC_LINE_COUNT; i++) {
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| 47 | IRQTable[i] = (IRQHandler_t)NULL;
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| 48 | }
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| 49 | GIC_Enable();
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| 50 | return (0);
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| 51 | }
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| 52 |
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| 53 |
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| 54 | /// Register interrupt handler.
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| 55 | __WEAK int32_t IRQ_SetHandler (IRQn_ID_t irqn, IRQHandler_t handler) {
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| 56 | int32_t status;
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| 57 |
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| 58 | if ((irqn >= 0) && (irqn < (IRQn_ID_t)IRQ_GIC_LINE_COUNT)) {
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| 59 | IRQTable[irqn] = handler;
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| 60 | status = 0;
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| 61 | } else {
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| 62 | status = -1;
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| 63 | }
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| 64 |
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| 65 | return (status);
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| 66 | }
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| 67 |
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| 68 |
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| 69 | /// Get the registered interrupt handler.
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| 70 | __WEAK IRQHandler_t IRQ_GetHandler (IRQn_ID_t irqn) {
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| 71 | IRQHandler_t h;
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| 72 |
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| 73 | // Ignore CPUID field (software generated interrupts)
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| 74 | irqn &= 0x3FFU;
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| 75 |
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| 76 | if ((irqn >= 0) && (irqn < (IRQn_ID_t)IRQ_GIC_LINE_COUNT)) {
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| 77 | h = IRQTable[irqn];
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| 78 | } else {
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| 79 | h = (IRQHandler_t)0;
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| 80 | }
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| 81 |
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| 82 | return (h);
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| 83 | }
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| 84 |
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| 85 |
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| 86 | /// Enable interrupt.
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| 87 | __WEAK int32_t IRQ_Enable (IRQn_ID_t irqn) {
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| 88 | int32_t status;
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| 89 |
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| 90 | if ((irqn >= 0) && (irqn < (IRQn_ID_t)IRQ_GIC_LINE_COUNT)) {
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| 91 | GIC_EnableIRQ ((IRQn_Type)irqn);
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| 92 | status = 0;
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| 93 | } else {
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| 94 | status = -1;
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| 95 | }
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| 96 |
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| 97 | return (status);
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| 98 | }
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| 99 |
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| 100 |
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| 101 | /// Disable interrupt.
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| 102 | __WEAK int32_t IRQ_Disable (IRQn_ID_t irqn) {
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| 103 | int32_t status;
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| 104 |
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| 105 | if ((irqn >= 0) && (irqn < (IRQn_ID_t)IRQ_GIC_LINE_COUNT)) {
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| 106 | GIC_DisableIRQ ((IRQn_Type)irqn);
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| 107 | status = 0;
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| 108 | } else {
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| 109 | status = -1;
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| 110 | }
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| 111 |
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| 112 | return (status);
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| 113 | }
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| 114 |
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| 115 |
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| 116 | /// Get interrupt enable state.
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| 117 | __WEAK uint32_t IRQ_GetEnableState (IRQn_ID_t irqn) {
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| 118 | uint32_t enable;
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| 119 |
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| 120 | if ((irqn >= 0) && (irqn < (IRQn_ID_t)IRQ_GIC_LINE_COUNT)) {
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| 121 | enable = GIC_GetEnableIRQ((IRQn_Type)irqn);
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| 122 | } else {
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| 123 | enable = 0U;
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| 124 | }
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| 125 |
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| 126 | return (enable);
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| 127 | }
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| 128 |
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| 129 |
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| 130 | /// Configure interrupt request mode.
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| 131 | __WEAK int32_t IRQ_SetMode (IRQn_ID_t irqn, uint32_t mode) {
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| 132 | uint32_t val;
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| 133 | uint8_t cfg;
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| 134 | uint8_t secure;
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| 135 | uint8_t cpu;
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| 136 | int32_t status = 0;
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| 137 |
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| 138 | if ((irqn >= 0) && (irqn < (IRQn_ID_t)IRQ_GIC_LINE_COUNT)) {
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| 139 | // Check triggering mode
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| 140 | val = (mode & IRQ_MODE_TRIG_Msk);
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| 141 |
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| 142 | if (val == IRQ_MODE_TRIG_LEVEL) {
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| 143 | cfg = 0x00U;
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| 144 | } else if (val == IRQ_MODE_TRIG_EDGE) {
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| 145 | cfg = 0x02U;
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| 146 | } else {
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| 147 | cfg = 0x00U;
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| 148 | status = -1;
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| 149 | }
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| 150 |
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| 151 | // Check interrupt type
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| 152 | val = mode & IRQ_MODE_TYPE_Msk;
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| 153 |
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| 154 | if (val != IRQ_MODE_TYPE_IRQ) {
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| 155 | status = -1;
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| 156 | }
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| 157 |
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| 158 | // Check interrupt domain
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| 159 | val = mode & IRQ_MODE_DOMAIN_Msk;
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| 160 |
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| 161 | if (val == IRQ_MODE_DOMAIN_NONSECURE) {
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| 162 | secure = 0U;
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| 163 | } else {
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| 164 | // Check security extensions support
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| 165 | val = GIC_DistributorInfo() & (1UL << 10U);
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| 166 |
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| 167 | if (val != 0U) {
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| 168 | // Security extensions are supported
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| 169 | secure = 1U;
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| 170 | } else {
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| 171 | secure = 0U;
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| 172 | status = -1;
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| 173 | }
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| 174 | }
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| 175 |
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| 176 | // Check interrupt CPU targets
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| 177 | val = mode & IRQ_MODE_CPU_Msk;
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| 178 |
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| 179 | if (val == IRQ_MODE_CPU_ALL) {
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| 180 | cpu = 0xFFU;
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| 181 | } else {
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| 182 | cpu = val >> IRQ_MODE_CPU_Pos;
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| 183 | }
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| 184 |
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| 185 | // Apply configuration if no mode error
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| 186 | if (status == 0) {
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| 187 | GIC_SetConfiguration((IRQn_Type)irqn, cfg);
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| 188 | GIC_SetTarget ((IRQn_Type)irqn, cpu);
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| 189 |
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| 190 | if (secure != 0U) {
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| 191 | GIC_SetGroup ((IRQn_Type)irqn, secure);
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| 192 | }
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| 193 | }
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| 194 | }
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| 195 |
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| 196 | return (status);
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| 197 | }
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| 198 |
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| 199 |
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| 200 | /// Get interrupt mode configuration.
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| 201 | __WEAK uint32_t IRQ_GetMode (IRQn_ID_t irqn) {
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| 202 | uint32_t mode;
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| 203 | uint32_t val;
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| 204 |
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| 205 | if ((irqn >= 0) && (irqn < (IRQn_ID_t)IRQ_GIC_LINE_COUNT)) {
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| 206 | mode = IRQ_MODE_TYPE_IRQ;
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| 207 |
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| 208 | // Get trigger mode
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| 209 | val = GIC_GetConfiguration((IRQn_Type)irqn);
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| 210 |
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| 211 | if ((val & 2U) != 0U) {
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| 212 | // Corresponding interrupt is edge triggered
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| 213 | mode |= IRQ_MODE_TRIG_EDGE;
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| 214 | } else {
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| 215 | // Corresponding interrupt is level triggered
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| 216 | mode |= IRQ_MODE_TRIG_LEVEL;
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| 217 | }
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| 218 |
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| 219 | // Get interrupt CPU targets
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| 220 | mode |= GIC_GetTarget ((IRQn_Type)irqn) << IRQ_MODE_CPU_Pos;
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| 221 |
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| 222 | } else {
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| 223 | mode = IRQ_MODE_ERROR;
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| 224 | }
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| 225 |
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| 226 | return (mode);
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| 227 | }
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| 228 |
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| 229 |
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| 230 | /// Get ID number of current interrupt request (IRQ).
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| 231 | __WEAK IRQn_ID_t IRQ_GetActiveIRQ (void) {
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| 232 | IRQn_ID_t irqn;
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| 233 | uint32_t prio;
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| 234 |
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| 235 | /* Dummy read to avoid GIC 390 errata 801120 */
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| 236 | GIC_GetHighPendingIRQ();
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| 237 |
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| 238 | irqn = GIC_AcknowledgePending();
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| 239 |
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| 240 | __DSB();
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| 241 |
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| 242 | /* Workaround GIC 390 errata 733075 (GIC-390_Errata_Notice_v6.pdf, 09-Jul-2014) */
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| 243 | /* The following workaround code is for a single-core system. It would be */
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| 244 | /* different in a multi-core system. */
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| 245 | /* If the ID is 0 or 0x3FE or 0x3FF, then the GIC CPU interface may be locked-up */
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| 246 | /* so unlock it, otherwise service the interrupt as normal. */
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| 247 | /* Special IDs 1020=0x3FC and 1021=0x3FD are reserved values in GICv1 and GICv2 */
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| 248 | /* so will not occur here. */
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| 249 |
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| 250 | if ((irqn == 0) || (irqn >= 0x3FE)) {
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| 251 | /* Unlock the CPU interface with a dummy write to Interrupt Priority Register */
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| 252 | prio = GIC_GetPriority((IRQn_Type)0);
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| 253 | GIC_SetPriority ((IRQn_Type)0, prio);
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| 254 |
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| 255 | __DSB();
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| 256 |
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| 257 | if ((irqn == 0U) && ((GIC_GetIRQStatus ((IRQn_Type)irqn) & 1U) != 0U) && (IRQ_ID0 == 0U)) {
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| 258 | /* If the ID is 0, is active and has not been seen before */
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| 259 | IRQ_ID0 = 1U;
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| 260 | }
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| 261 | /* End of Workaround GIC 390 errata 733075 */
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| 262 | }
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| 263 |
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| 264 | return (irqn);
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| 265 | }
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| 266 |
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| 267 |
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| 268 | /// Get ID number of current fast interrupt request (FIQ).
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| 269 | __WEAK IRQn_ID_t IRQ_GetActiveFIQ (void) {
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| 270 | return ((IRQn_ID_t)-1);
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| 271 | }
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| 272 |
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| 273 |
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| 274 | /// Signal end of interrupt processing.
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| 275 | __WEAK int32_t IRQ_EndOfInterrupt (IRQn_ID_t irqn) {
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| 276 | int32_t status;
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| 277 | IRQn_Type irq = (IRQn_Type)irqn;
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| 278 |
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| 279 | irqn &= 0x3FFU;
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| 280 |
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| 281 | if ((irqn >= 0) && (irqn < (IRQn_ID_t)IRQ_GIC_LINE_COUNT)) {
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| 282 | GIC_EndInterrupt (irq);
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| 283 |
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| 284 | if (irqn == 0) {
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| 285 | IRQ_ID0 = 0U;
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| 286 | }
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| 287 |
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| 288 | status = 0;
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| 289 | } else {
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| 290 | status = -1;
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| 291 | }
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| 292 |
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| 293 | return (status);
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| 294 | }
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| 295 |
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| 296 |
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| 297 | /// Set interrupt pending flag.
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| 298 | __WEAK int32_t IRQ_SetPending (IRQn_ID_t irqn) {
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| 299 | int32_t status;
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| 300 |
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| 301 | if ((irqn >= 0) && (irqn < (IRQn_ID_t)IRQ_GIC_LINE_COUNT)) {
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| 302 | GIC_SetPendingIRQ ((IRQn_Type)irqn);
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| 303 | status = 0;
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| 304 | } else {
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| 305 | status = -1;
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| 306 | }
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| 307 |
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| 308 | return (status);
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| 309 | }
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| 310 |
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| 311 | /// Get interrupt pending flag.
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| 312 | __WEAK uint32_t IRQ_GetPending (IRQn_ID_t irqn) {
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| 313 | uint32_t pending;
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| 314 |
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| 315 | if ((irqn >= 16) && (irqn < (IRQn_ID_t)IRQ_GIC_LINE_COUNT)) {
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| 316 | pending = GIC_GetPendingIRQ ((IRQn_Type)irqn);
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| 317 | } else {
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| 318 | pending = 0U;
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| 319 | }
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| 320 |
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| 321 | return (pending & 1U);
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| 322 | }
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| 323 |
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| 324 |
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| 325 | /// Clear interrupt pending flag.
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| 326 | __WEAK int32_t IRQ_ClearPending (IRQn_ID_t irqn) {
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| 327 | int32_t status;
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| 328 |
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| 329 | if ((irqn >= 16) && (irqn < (IRQn_ID_t)IRQ_GIC_LINE_COUNT)) {
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| 330 | GIC_ClearPendingIRQ ((IRQn_Type)irqn);
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| 331 | status = 0;
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| 332 | } else {
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| 333 | status = -1;
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| 334 | }
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| 335 |
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| 336 | return (status);
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| 337 | }
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| 338 |
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| 339 |
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| 340 | /// Set interrupt priority value.
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| 341 | __WEAK int32_t IRQ_SetPriority (IRQn_ID_t irqn, uint32_t priority) {
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| 342 | int32_t status;
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| 343 |
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| 344 | if ((irqn >= 0) && (irqn < (IRQn_ID_t)IRQ_GIC_LINE_COUNT)) {
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| 345 | GIC_SetPriority ((IRQn_Type)irqn, priority);
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| 346 | status = 0;
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| 347 | } else {
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| 348 | status = -1;
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| 349 | }
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| 350 |
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| 351 | return (status);
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| 352 | }
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| 353 |
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| 354 |
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| 355 | /// Get interrupt priority.
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| 356 | __WEAK uint32_t IRQ_GetPriority (IRQn_ID_t irqn) {
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| 357 | uint32_t priority;
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| 358 |
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| 359 | if ((irqn >= 0) && (irqn < (IRQn_ID_t)IRQ_GIC_LINE_COUNT)) {
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| 360 | priority = GIC_GetPriority ((IRQn_Type)irqn);
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| 361 | } else {
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| 362 | priority = IRQ_PRIORITY_ERROR;
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| 363 | }
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| 364 |
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| 365 | return (priority);
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| 366 | }
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| 367 |
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| 368 |
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| 369 | /// Set priority masking threshold.
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| 370 | __WEAK int32_t IRQ_SetPriorityMask (uint32_t priority) {
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| 371 | GIC_SetInterfacePriorityMask (priority);
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| 372 | return (0);
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| 373 | }
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| 374 |
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| 375 |
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| 376 | /// Get priority masking threshold
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| 377 | __WEAK uint32_t IRQ_GetPriorityMask (void) {
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| 378 | return GIC_GetInterfacePriorityMask();
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| 379 | }
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| 380 |
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| 381 |
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| 382 | /// Set priority grouping field split point
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| 383 | __WEAK int32_t IRQ_SetPriorityGroupBits (uint32_t bits) {
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| 384 | int32_t status;
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| 385 |
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| 386 | if (bits == IRQ_PRIORITY_Msk) {
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| 387 | bits = 7U;
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| 388 | }
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| 389 |
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| 390 | if (bits < 8U) {
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| 391 | GIC_SetBinaryPoint (7U - bits);
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| 392 | status = 0;
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| 393 | } else {
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| 394 | status = -1;
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| 395 | }
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| 396 |
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| 397 | return (status);
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| 398 | }
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| 399 |
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| 400 |
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| 401 | /// Get priority grouping field split point
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| 402 | __WEAK uint32_t IRQ_GetPriorityGroupBits (void) {
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| 403 | uint32_t bp;
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| 404 |
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| 405 | bp = GIC_GetBinaryPoint() & 0x07U;
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| 406 |
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| 407 | return (7U - bp);
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| 408 | }
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| 409 |
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| 410 | #endif
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